Journal ArticleDOI
A BiCMOS dynamic carry lookahead adder circuit for VLSI implementation of high-speed arithmetic unit
Jui-Chang Kuo,H.J. Liao,Hung-Wei Chen +2 more
- Vol. 28, Iss: 3, pp 375-378
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TLDR
A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented and shows a more than five times improvement in speed as compared to the CMOS Manchester carryLookahead (MCLA) circuit.Abstract:
A BiCMOS dynamic carry lookahead circuit that is free from race problems is presented. A 16 b full-adder test circuit, which has been designed based on a 2 mu m BiCMOS technology, shows a more than five times improvement in speed as compared to the CMOS Manchester carry lookahead (MCLA) circuit. The speed advantage of the BiCMOS dynamic carry lookahead circuit is even greater in a 32- or 64-b adder. >read more
Citations
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Journal ArticleDOI
A high-performance encoder with priority lookahead
José G. Delgado-Frias,J. Nyathi +1 more
TL;DR: A priority encoder that uses a novel priority lookahead (PL) scheme to reduce delays associated with priority propagation and one without and the other with a PL scheme are presented.
Journal ArticleDOI
A 64-bit carry look ahead adder using pass transistor BiCMOS gates
TL;DR: In this paper, a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate was described, which has a rail-to-rail output voltage.
Proceedings ArticleDOI
A VLSI high-performance encoder with priority lookahead
José G. Delgado-Frias,J. Nyathi +1 more
TL;DR: A VLSI priority encoder that uses a novel priority lookahead scheme to reduce the delay for the worst case operation of the circuit, while maintaining a very low transistor count is introduced.
Proceedings ArticleDOI
FPGA implementation of synchronous section-carry based carry look-ahead adders
K. Preethi,P. Balasubramanian +1 more
TL;DR: FPGA based realization of high-speed carry look-ahead adders based on the concept of section-carry with improvements in speed of 14.9%, 12.1% and 13% for Type 1, Type 2 and Mixed topologies respectively, for simulations targeting a 90nm FPGA device.
Journal ArticleDOI
A 1.5 V BiCMOS dynamic logic circuit using a "BiPMOS pull-down" structure for VLSI implementation of full adders
TL;DR: Using the 1.5 V BiCMOS dynamic logic circuit, a 16-bit full adder circuit, which is composed of half adders and a carry look-ahead circuit, shows a 1.7 times improvement in speed as compared to the CMOS static one.
References
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Journal ArticleDOI
High-speed CMOS circuit technique
Jiren Yuan,Christer Svensson +1 more
TL;DR: It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process, and a precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used.
Journal ArticleDOI
High-speed compact circuits with CMOS
TL;DR: A new circuit type, the CMOS domino circuit, is described, which involves the connection of dynamic CMOS gates in such a way that a single clock edge can be used to turn on all gates in the circuit at once.
Journal ArticleDOI
NORA: a racefree dynamic CMOS technique for pipelined logic structures
N.F. Goncalves,H. De Man +1 more
TL;DR: A new dynamic CMOS technique which is fully racefree, yet has high logic flexibility, and logic inversion is provided, which means higher logic flexibility and less transistors for the same function.
Journal ArticleDOI
A 4-ns 4K*1-bit two-port BiCMOS SRAM
TL;DR: A two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage is introduced, allowing access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays.
Journal ArticleDOI
Perspective on BiCMOS VLSIs
TL;DR: By combining bipolar and CMOS devices in unit circuits of VLSIs, Hi-BiCMOS provides both speed performance competitive with bipolar LSIs and integration density close to that of CMOS LSIs.