Showing papers on "Carry-lookahead adder published in 2018"

Comparative evaluation of quasi-delay-insensitive asynchronous adders corresponding to return-to-zero and return-to-one handshaking

Abstract: This article makes a comparative evaluation of quasi-delay-insensitive (QDI) asynchronous adders, realized using the delay-insensitive dual-rail code, which adhere to 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshake protocols. The QDI adders realized correspond to the following adder architectures: i) ripple carry adder, ii) carry lookahead adder, and iii) carry select adder. The QDI adders correspond to three different timing regimes viz. strong-indication, weak-indication and early output. They are physically implemented using a 32/28nm CMOS process. The comparative evaluation shows that, overall, QDI adders which correspond to the 4-phase RTO handshake protocol are better than the QDI adder counterparts which correspond to the 4-phase RTZ handshake protocol in terms of latency, area, and average power dissipation.

Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Abstract: Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Abstract: Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

Performance Comparison of some Synchronous Adders.

Abstract: This technical note compares the performance of some synchronous adders which correspond to the following architectures: i) ripple carry adder (RCA), ii) recursive carry lookahead adder (RCLA), iii) hybrid RCLA-RCA with the RCA used in the least significant adder bit positions, iv) block carry lookahead adder (BCLA), v) hybrid BCLA-RCA with the RCA used in the least significant adder bit positions, and vi) non-uniform input partitioned carry select adders (CSLAs) without and with the binary to excess-1 code (BEC) converter. The 32-bit addition was considered as an example operation. The adder architectures mentioned were implemented by targeting a typical case PVT specification (high threshold voltage, supply voltage of 1.05V and operating temperature of 25 degrees Celsius) of the Synopsys 32/28nm CMOS technology. The comparison leads to the following observations: i) the hybrid CCLA-RCA is preferable to the other adders in terms of the speed, the power-delay product, and the energy-delay product, ii) the non-uniform input partitioned CSLA without the BEC converter is preferable to the other adders in terms of the area-delay product, and iii) the RCA incorporating the full adder present in the standard digital cell library is preferable to the other adders in terms of the power-delay-area product.

Performance metrics on ultra low power polyphase decimation filter using carbon nanotube field effect transistor technology

Abstract: Low power consumption and abatement in area are the most pre-eminent criteria to scheme the digital signal processor. Multi-rate signal processing studies digital signal processing systems which include conversion. Filters are the substantial building blocks of DSP. The polyphase filters are the momentous component in crafting of various filter structures. Polyphase structure employs FIR filter that terminates to very efficacious implementation. The polyphase decimation filter is generally built with multipliers, parallel in serial out shift register, serial in parallel out shift register, ripple carry adder, carry lookahead adder and parallel in parallel out shift registers as a delay element. To accomplish the desired results in performance parameters of the multiplier, a potent adder is proposed and embodied in the multiplier. The carbon nanotube field effect transistor (CNTFET) is an ameliorating new device that may trample some of the restraints of a silicon-based MOSFET. The circuits are designed in 32 nm CMOS and CNTFET technology in Synopsys HSpice. Performance parameters such as power, delay and power delay product are assayed and compared in both the technologies.

Memristor Adder Design

Abstract: In this paper, the design of adders implemented with memristors is discussed. Memristor based designs for standard adder architectures (ripple carry adder, carry lookahead adder and parallel prefix adders) are explained. The area and latency are compared. Surprisingly, the Radix-2 CLA has a complexity very similar to the parallel prefix adders. It is shown that the Kogge-Stone design has the best metric in terms of delay and area among the parallel prefix adders.

Design and Implementation of 64-bit Carry Lookahead Adders Using Fixed and Variable Stage Structure

Abstract: Adders are basic integral part of arithmetic circuits. The adders have been realized with two styles: fixed stage and variable stage size. This paper presents the correlation investigation of execution examination of 64-bit Carry Lookahead Adders utilizing conventional and hierarchical structure styles with fixed stages and variable stages. We utilize different diverse parameter to evaluate conventional carry lookahead adder (CLA) and hierarchical carry lookahead adder (HCLA) and variable stage carry lookahead adder. Our outline is actualized into Zedboard Xilinx Zynq XC7Z020-1CLG484. Our intrigued of investigation are delay, area, and power. In this paper we show conventional CLA required small area using radix-2, while in hierarchical CLA delay is diminished to a great extent. Furthermore, we demonstrated variable stages CLA would be able to tradeoff between the area, delay and power.

ALU circuit in FPGA

Abstract: The invention discloses an ALU circuit in an FPGA and relates to the field of integrated circuit design. The ALU circuit comprises M addition units and a carry lookahead adder, wherein M is an integergreater than or equal to 8; each addition unit comprises a three-input full adder, a first selector, a second selector and a third selector, and output of the second selector and output of the thirdselector of each addition unit are used as output of the corresponding addition unit; each three-input full adder is provided with three input ends and two output ends, namely a sum value data outputend and a carry data output end; a sum value output end of the carry lookahead adder is connected with a first input end of a fourth selector and also connected with a second input end of the fourth selector through an inverter, and an output end of the fourth selector serves as a third output end of the ALU circuit; and the carry lookahead adder is also provided with a first output end used for outputting first carry data and a second output end used for outputting second carry data. Through the ALU circuit, a high-efficiency small-area DSP module is realized.

IC Layout Design of Carry Lookahead Adder at 90nm Technology using GNU/Electric

Abstract: Adder circuits have many applications in addition, multiplication, division, and in address calculation. Carry Look Ahead Adder is one of the most efficient adder since it can conserve the time of propagating the carry bits. In this paper we have discussed the review of design of an Integrated Circuit(IC) layout for different bits of Carry Look Ahead Adder using full custom method with 90nm scaling. The layout will be designed by using an open source software namely Electric-9.07 VLSI EDA tool. In order to produce the layout, the basic knowledge of fabrication process and IC design rule check is necessary. The layout will undergo Design Rule Check set by the Electric VLSI tool to check for any Design Rule Error. Both layout and schematic circuit of CLA were then going to simulate through LVS (Layout Versus Schematic) to ensure they both are identical. LT Spice will be used as a simulator to carry out the simulation work and verifying the validity of the circuit function.

Asynchronous Early Output Block Carry Lookahead Adder with Improved Quality of Results

Abstract: A new asynchronous early output, relative-timed block carry lookahead adder (BCLA) incorporating redundant carries is proposed. Compared to the best of existing semi-custom asynchronous carry lookahead adders (CLAs) employing delay-insensitive data encoding and following a 4-phase handshaking, the proposed BCLA with redundant carries achieves 14.9% reduction in cycle time and 12.3% reduction in area with no power penalty. A hybrid variant involving a ripple carry adder (RCA) in the least significant stages i.e. BCLA-RCA is also considered that achieves 15.2% reduction in cycle time and 11.2% reduction in area over the best of existing hybrid CLARCA variants without power penalty.

Comparative Analysis of Various Design Implementations of CLA Carry Chains

Abstract: This paper presents a comparative research of Carry Lookahead Adder (CLA) carry chains of various design implementations, in terms of propagation delay and transistor count. Two different design implementations of CLA carry generation circuit are discussed and compared based on their speed and transistor count. The representative designs compared are Complementary Metal Oxide Semiconductor (CMOS) Conventional CLA (CCLA) carry generation structure and proposed structure of CLA carry generation, named VpAn. To yield optimized delay for the proposed VpAn Design, transistor resizing has been done. A comprehensive comparison and analysis of performance of four, eight and sixteen bit carry chains are carried out. All the schematics of the CLA carry chains are designed using 0.25um process. The simulations of the schematics of CMOS conventional CLA generation circuits and the proposed CLA carry generation designs are performed using LTspice based on 250nm CMOS technology and 2.5V supply voltage to yield realistic rise and fall times. The speed of each circuit is evaluated and our proposed model reduces the propagation delay by 75% compared to the results of CCLA before sizing. This paper establishes, how the physical implementation of circuits relate to their performance.