Showing papers on "Clock synchronization published in 1988"

A new fault-tolerant algorithm for clock synchronization

Abstract: We describe a new fault-tolerant algorithm for solving a variant of Lamport's clock synchronization problem. The algorithm is designed for a system of distributed processes that communicate by sending messages. Each process has its own read-only physical clock whose drift rate from real time is very small. By adding a value to its physical clock time, the process obtaines its local time. The algorithm solves the problem of maintaining closely synchronized local times, assuming that processes' local times are closely synchronized initially. The algorithm is able to tolerate the failure of just under one-third of the participating processes. It maintains synchronization to within a small constant, whose magnitude depends upon the rate of clock drift, the message delivery time and its uncertainty, and the initial closeness of synchronization. We also give a characterization of how far the clocks drift from real time. Reintegration of a repaired process can be accomplished using a slight modification of the basic alborithm. A similar style algorithm can also be used to achieve synchronization initially.

Synchronization of fault-tolerant clocks in the presence of malicious failures

Abstract: The problem of achieving global clock synchronization in fault-tolerant clocks by preventing so-called multiple cliques in the presence of malicious clock failures (i.e. clock failures that are perceived differently by different nonfaulty clocks) is addressed. A solution to the problem, referred to as the averaging rule, is developed, and its use is analytically justified using the notions of clock partitions and generalized clock partitions. Experimental characterization of the multiple cliques problem has been undertaken, and certain conditions that induce their occurrence in practical hardware implementation are identified. The effects of clock-receiver triggering variations and phase-detector operating range on the instantaneous frequencies of the clock modules are investigated. The efficacy of the averaging rule is established not only by analysis but also by means of simulations and experimentation with hardware clock implementations. >

Partially distributed method for clock synchronization

Abstract: In a distributed system comprising a plurality of processors coupled to one another, each processor comprises a controllable clock circuit which indicates a local time. Clock synchronization methods are based on the idea in which randomly selected M processors out of the total N processors cooperate to adjust the controllable clock circuits of all processors in the distributed system. Three types of methods are described. In a first one of the methods, all processors randomly selects M processors, respectively, at time instants which are different from one another, and each processor adjusts its own controllable clock circuit to an average of the local times of the selected M processors. In a second method, each processor transmits its own local time to randomly selected M processors and adjusts its own controllable clock circuit to the average of received local times. In a third method, all processors adjust their controllable clock circuits to the average of received local times issued by randomly selected M processors. Fault tolerance against each processor is taken into account in their methods. Their methods can be applied to a sufficient large distributed system because of a small number of messages exchanged among processors.

Method for referencing multiple data processors to a common time reference

Abstract: A master (virtual) clock is situated at a central data gathering station, and slave (physical) clocks are situated at one or more (functionally or spatially) remote stations. Time signals are exchanged between the master clock at the central station and each slave clock at each corresponding remote station. From these signals (i) the ratio between the frequencies of the central station master clock and the corresponding remote station slave clock is determined, (ii) the difference in reference (starting) time value between the central station master clock and the corresponding remote station slave clock is determined, and (iii) the transmission time between the central station master clock and the corresponding remote station slave clock is determined. Averages of the clock ratio, reference time, and transmission time are determined across successive time signals to provide improved accuracy. The clock ratio and reference time values are used to derive data referenced to the master clock at the central station from data collected via the slave clock at the remote stations so that the time and data values associated with the data correspond to time and data values generated by the master clock at the central station. If desired, a (virtual) master clock can be determined having time values which are the average of the master clock and all slave clock time values.

Checkpointing and rollback recovery in a distributed system using common time base

Abstract: An approach to checkpointing and rollback recovery in a distributed computing system using a common time base is proposed. First, a common time base is established in the system using a hardware clock synchronization algorithm. This common time base is coupled with a pseudorecovery block approach to develop a checkpointing algorithm that has the following advantages: (i) maximum process autonomy, (ii) no wait for commitment for establishing recovery lines, (iii) fewer messages to be exchanged, and (iv) less memory requirement. >

Method for adjusting clocks of multiple data processors to a common time base

Abstract: A master clock is situated at a central data gathering station, and slave clocks are situated at one or more (functionally or spatially) remote stations. Time signals are exchanged between the master clock at the central station and each slave clock at the corresponding remote station. From these signals (i) the transmission time between the central station and the corresponding remote station is determined, and (ii) the ratio between the frequencies of the central station master clock and the corresponding remote station slave clock is determined. The transmission time and clock ratio so determined are averaged between successive determinations to provide improved accuracy. The transmission time value is used to set the slave clock to a reference value accurately corresponding to the time kept by the master clock; and thereafter the clock ratio value is used to insure that the slave clock is incremented at a rate corresponding to the frequency of the oscillator in the master clock. If desired, the master clock can be synchronized to a reference time which is the average of the reference times of the various clocks, and/or to a frequency which is the average of the frequencies of the oscillators in the various clocks.

Relativistic effects in GPS

Abstract: Relativistic effects in GPS are twofold: first is the effect on orbit and signal propagation, second is that on the clock. The first part has an effect of up to 0.001 ppm in positioning. The second part affects the clock frequency on the order of 10−10, but only the periodic fluctuation in it is of interest. This term is completely canceled out by between-station differences, hence it is harmless for relative positioning, but it directly affects the clock synchronization and causes substantial error in single point positioning. By adopting a Keplerian orbit, most of this fluctuation can be corrected. The ammount of non-Keplerian part is estimated to be less than 0.6 ns (18 cm).

Clock recovery and hold circuit for digital TDM mobile radio

Abstract: A clock recovery circuit for a digital TDM mobile radio transceiver is disclosed. In the "acquisition mode", a first phase-locked loop is configured to acquire synchronization with the input data signal, and a second phase-locked loop is coupled to the first PLL's output signal, thereby providing the recovered clock signal. The controller monitors the transmit control line and the received signal strength so as to switch the clock recovery circuit into a second configuration during a TDM transmit burst or a received signal fade. In this "hold mode", the second PLL is configured to free-run within a specified tolerance, while the first PLL is coupled to the second PLL's output signal. The controller maintains this "hold" configuration until the received signal is again present, and until the first PLL again acquires synchronization to the input data signal. In this manner, the controller prevents the recovered clock signal from losing bit synchronization or phase synchronization during transmit bursts, during the transmit-to-receive synthesizer out-of-lock period, or during Rayleigh fades. The present invention is particularly adapted for use in a TDM system utilizing 0.2 GMSK modulation, wherein there is less apparent clock signal available for clock recovery.

Transmission delays in hardware clock synchronization

Abstract: Various methods, both with software and hardware, have been proposed to synchronize a set of physical clocks in the system. Software methods are very flexible and economical but suffer an excessive time overhead, whereas hardware methods require no time overhead but are unable to handle transmission delays in clock signals. The effects of nonzero transmission delays in synchronization have been studied extensively in the communication area in the absence of malicious or Byzantine faults. The authors show that it is easy to incorporate the ideas from the communication area into the existing hardware clock synchronization algorithms in order to take into account the presence of both malicious faults and nonzero transmission delays. >

Real-time simulation clock

Abstract: The invention is a Clock for synchronizing operations within a high-speed, distributed data processing network The clock is actually a distributed system comprising a Central Clock and multiple Site Clock Interface Units (SCIU's) which are connected by means of a fiber optic star network and which operate under control of separate clock software The presently preferred embodiment is as a part of the flight simulation system now in current use at the National Aeronautics and Space Administration (NASA) Langley Research Center (LaRC), Hampton, Va

Adaptive clock synchronization schemes for real-time traffic in broadband packet networks

Abstract: The authors illustrate the phenomenon of packet jitter using a simple example and propose methods by which the destination clock frequency can be adjusted, so that it follows the source clock frequency asymptotically while minimizing the effects of packet jitter on the outgoing packet stream. They provide a comprehensive asymptotic analysis of the estimation and control algorithms and discuss their implementation. The authors provide a systematic design procedure for choosing the relevant parameters for implementation and discuss the sensitivity of the performance with respect to these parameters. >

Understanding Clock Skew in Synchronous Systems

Abstract: Clock distribution and synchronization in synchronous systems are important issues especially as the size of the system and/or the clock rate increase. Minimization of clock skew has always been a major concern for the designers. Many factors contribute to clock synchronization and skew in a synchronous system. Among the major factors are: the clock distribution network, choice of clocking scheme, the underlying technology, the size of the system and level of integration, the type of material used in distributing the clock, clock buffers, and the clock rate. To be able to get around the problems related to clock skew and synchronization, one has to understand the effect that clock skew can have on the operation of a given system. In this paper we derive simple and practical formulations of these effects in terms of a few time-parameters that can be considered as properties of the individual modules and the clock network in a synchronous system. Knowing these time-parameters, one can determine the maximum throughput of a given system as well as its reaction to a change in clock skew. Three different clocking schemes, namely, edge-triggered, single-phase level sensitive, and two-phase clocking are considered. However, using the approaches discussed in this paper, the effect of clock skew for any other clocking scheme can be analyzed and formulated.

A survey of provably correct fault-tolerant clock synchronization techniques

Abstract: Six provably correct fault-tolerant clock synchronization algorithms are examined. These algorithms are all presented in the same notation to permit easier comprehension and comparison. The advantages and disadvantages of the different techniques are examined and issues related to the implementation of these algorithms are discussed. The paper argues for the use of such algorithms in life-critical applications.

A simple algorithm for clock synchronization in transputer networks

Abstract: In a distributed system based on Transputer components there is one clock for each processing element, and the definition of the global system time requires the choice of a hardware or software synchronization method. This paper describes the RING_SYNC algorithm, based on a ring-structured synchronization scheme. RING_SYNC has no provision for fault tolerance, but it introduces little overhead, thanks to the optimization of both the number of messages exchanged at sync time and the resynchronization frequency. The implementation of the algorithm together with the tests performed for measuring the synchronization error and their results are discussed extensively, and some typical applications are pointed out.

Optimum clock generator in data communication

Abstract: A clock generator in a data receiver for generating an optimum PN code clock used by a spectrum spread (55) communication receiver. The generator comprises a clock generator for generating a plurality of clocks having different phases; a synchronization signal detection circuit for detecting a synchronization signal within a received signal; an optimum clock discrimination circuit for discriminating a first active clock from the plurality of clocks after the synchronization signal detection circuit detected the synchronization signal; and a clock selection circuit for selecting and outputting the clock discriminated from the plurality of clocks by the optimum clock discrimination circuit.

A probabilistic model for clock skew

Abstract: A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation. >

Initialization and synchronization method for a two-way communication link

Abstract: An initialization or synchronization method in which at least a predetermined number of synchronization messages are sent out over a two-way communication line. The receipt of a synchronization message is awaited before terminating the transmission of synchronization message. After the transmission of synchronization messages has been terminated the receipt of a non-synchronization message will complete the synchronization process. However, certain conditions may cause synchronization to be restarted such as a predetermined number of consecutive error messages, failure to receive any message in a predetermined number of clock signals, receiving more than a predetermined number of synchronization signals, or a reset command.

Comparisons and improvements of designs of data slicers and clock synchronization circuits for broadcast teletext decoders operating in a multipath environment

Abstract: It is shown that multipath propagation imposes a serious performance degradation on broadcast teletext systems designed according to the North American Basic Teletext Specifications. By using both analysis and a comprehensive computer simulation model of the teletext broadcast system, it was found that very significant gains in performance could be obtained by improving slicing level and clock synchronization circuit designs. Several slicing level and clock synchronization (also called bit timing recovery (BTR)) circuits were modeled and simulated and their performances compared. These included peak detecting, averaging, modified averaging, adaptive and ideal slicers. The averaging and adaptive slicers used with the correlator BTR circuit were found to give the best performance, but the complexity and cost of an adaptive slicer reduce the advantages of system implementation. >

Sound quality controller

Abstract: PURPOSE:To make the sound quality control variable in response to a volume step or the like while preventing the saturation of sound by constituting each sound quality control circuit in a digital signal processor (DSP) and controlling each function from a control microcomputer in the lump. CONSTITUTION:Various commands such as sound source selection, sound volume adjustment and sound quality control are inputted to a CPU 4 from a key pad matrix 6. A program memory (ROM) 21, a program counter 22, an I/O interface 23 and a clock oscillator 24 are connected to a program bus 20 and the interface 23 is connected to a control microcomputer 4 and A/D, D/A converters 8, 11. On the other hand, a data memory (RAM) 25, an address counter 26 or a multiplier 27, an adder 28, an accumulator 29, an arithmetic unit 30 are connected to the data bus 31. The communication between the DSP 10 and the CPU 4 are executed by the serial clock synchronization system using 8-bit address and 10-bit data and the address is the RAM address in the DSP defined by the DSP program.

Processor/coprocessor interface apparatus including microinstruction clock synchronization

Abstract: An information processing system includes a first data processing device 10 and a second data processing device 12 each of which is capable if independent instruction execution during instruction cycles having a period which is a multiple of a periodic unit clock signal period. The devices are disclosed to be an arithmetic unit and a central processor which are coupled together by an interface 14. Each of the data processing devices include a clock generation device 180 having an input coupled to the unit clock signal for generating an associated instruction cycle clock signal which has a period which is a multiple of the unit clock signal period. The clock generation device is further operable for suspending the generation of the instruction cycle clock signal and for beginning a next instruction cycle clock signal in synchronism with a transition of the unit clock signal. The devices 10 and 12 each request synchronization of their respective clocks which are then automatically synchronized to the other devices clock during a transition of the unit clock, allowing for instructions and operands to be synchronously passed between the central processor to the arithmetic unit.

Clock synchronization on the factory floor (FMS)

Abstract: The coordination of flexible manufacturing systems (FMS) in an automated factory requires that synchronization amongst the manufacturing processes be based on a common clock. The synchronization requirements on the factory floor are described, and several clock synchronization algorithms, their theoretical bounds, and the results of the authors' work are discussed. Measurement results based on the implementation of such synchronization algorithms on local area networks (LAN) are presented. For hierarchical LANs, an algorithm is developed and its behavior simulated. >

Non-byzantine clock synchronization—a programming experiment

Abstract: Introduction. Much of the work on distributed systems uses a functional programming paradigm. Thus each node behaves as a function, receiving an argument in a message, computing the value of the function depending on that argument, and either returning the resulting value to the original message sender, or forwarding it to another node. In particular remote procedure call models, dataflow models, and systolic array models are essentially using the functional programming approach to programming a distributed system.

Horizontal synchronization, clock synchronization, D.C. restoration and gain control scheme for an analog TV system

Abstract: An analog TV system includes a transmitter which produces a horizontal unique pulse sequence during each horizontal blanking interval. The pulse sequence is amplitude modulated between two levels to define a horizontal unique word for horizontal synchronization. The frequency of the pulse sequence is selected for use by the receiver section as the color subcarrier phase reference. The average level of the pulse sequence is set at the transmitter and used at the receiver for DC restoration in a clamping circuit. The peak amplitude of the pulses of the pulse sequence define a reference level against which a receiver producing local reference is compared for AGC. As four separate functions are accomplished by a single unique pulse sequence transmitted during the horizontal blanking interval, which four functions are typically accomplished using four separate signals transmitted sequentially during the horizontal blanking interval, a substantial portion of the horizontal blanking interval remains available for other data.

Optimal Synchronization of ABD Networks

Abstract: We present a simple and efficient synchronizer for ABD networks, asynchronous networks with bounded delay message delivery. The algorithms improve on an earlier algorithm [Ch87]. Using a mathematical model for this type of synchronizer we achieve optimality results for ABD synchronizers.

Fault-tolerant clock synchronization techniques for avionics systems

Abstract: This paper examines six provably correct fault-tolerant clock synchronization algorithms. These algorithms are all presented in the same notation to enable easier comprehension and comparison. The advantages and disadvantages of the different techniques are examined and issues related to the implementation of these algorithms are discussed. The paper argues for the use of such algorithms in life-critical applications.

Synchronisation arrangements for a digital telecommunications exchange system

Abstract: The synchronization arrangement includes a waveform and synchronization information generator to supply synchronization information for transmission with a data stream over digital switching networks. The synchronization information includes two different patterns, phased displaced with respect to each other. Interfaces connect peripheral devices to the networks and are adapted to detect a validate the synchronization information. The checks made are in respect of detecting both patterns, the amount of phase displacement, and the correct sequence. If the synchronization information is invalid, the detecting interface selects a data stream from another network exclusively for use by the corresponding peripheral device.

Method and apparatus for transmission of synchronization signals between microprocessors in video system

Abstract: In order to couple together vertical-frequency synchronization signals generated by a computer connected to an data transmission system, the synchronization signals are generated by counting the clock pulses. A reference signal is transmitted to the computer or processor; the reference has a frequency which is a whole-number fraction of the desired frequency. Upon receipt in the processor (16) of the reference signal, a counter (19) provided for counting of the clock pulses is preset.

On the graceful degradation of phase-locked clocks

Abstract: The use of phase-locked clocks to limit clock skews to fractions of the clock period while keeping the algorithm overhead very small is investigated. The number of clocks in the system required to ensure that up to m arbitrary failures can be tolerated with all the good clocks still in synchrony has been shown to be N>or=3m+1. It is shown here that, if N >

Critical issues in the design of distributed, fault-tolerant, hard real-time systems

Abstract: In this thesis we study four important problems associated with the design of Distributed, Fault-Tolerant, Hard Real-Time systems: Agreement, Clock Synchronization, Reliability Modelling, and Task Scheduling. Previous models of Agreement in distributed systems have made the unrealistic assumption that either all faults are arbitrary or all faults are not arbitrary. By introducing a unique and natural fault classification we have developed a 'Unified' model of Interactive Consistency. Our model takes advantage of the fact that both non-malicious faults and some malicious faults do not have to satisfy the $N > 3t$ requirement. We do not require that the system designer make unrealistic or extreme assumptions; both arbitrary and non-arbitrary faults are allowed. Most reliability models of ultra-reliable systems have not considered the interactive consistency requirement in a rigorous manner; distributed fault-tolerant systems have been modelled simply as redundant systems. We have obtained closed form expressions for the reliability and the Mean Time to Failure of distributed fault-tolerant systems. These reliability models are based on our 'Unified' fault model. These expressions explicitly include the contribution of the interactive consistency algorithm, and the types of faults. Our models allow the system designer to predict reliability far more accurately than previously possible. Clock synchronization is a fundamental requirement of fault-tolerant systems used for real-time control applications. Using the concepts of Interactive Convergence and Approximate Agreement we derive the maximum synchronization skew for the MAFT system. Then we develop a new fault model for clock faults, analagous to the 'Unified' model, and show that tighter synchronization and higher clock subsystem reliability are possible. Currently there are no methods which guarantee that a non-periodic task can complete within its deadline in a hard real-time system. We consider this problem in the context of a redundant system and introduce a novel technique which can allow a non-periodic task to execute within its deadline. This is accomplished by dynamically varying the redundancy of tasks. With the use of modelling we show that the impact on system reliability is minimal.

Precise clock distribution for synchronous broadband transmission network

Abstract: System considerations and precise clock distribution technology are discussed for high-speed fiber-optic systems such as broadband ISDN (integrated services digital network). A precise oscillator is in the central office provides a frequency standard. In each local office, a precise phase-locked loop recovers the standard clock signal. Methods are proposed for fast phase-locking and reducing the slip that occurs when the standard clock signal input is absent. >