Showing papers on "Comparator applications published in 1997"

Simple high-speed CMOS current comparator

Abstract: A simple modification to an existing current comparator is proposed, which enables a very low response time to be achieved with a minimal increase in circuit complexity. Circuit simulations allowed the design approach to be validated and the comparator performance to be compared to those of two other existing comparators.

Random binary number generator

Abstract: A random number generator includes a plurality of fully differential amplifiers (30) configured as a ring oscillator (22). The output of the ring oscillator (22) is input to a comparator/latch circuit (32) for determining the zero crossing for the ring oscillator. The ring oscillator is a self-oscillating structure that has an oscillation frequency with jitter superimposed thereon. This jitter is a result of the internal thermal noise associated with the integrated circuits that are utilized to realize the amplifiers (30). Each of the amplifiers (30) that make up the ring oscillator operate on a substantially constant current and are subsequently isolated from changes in the power supply. As such, the variations in the frequency thereof are caused solely by thermal noise. The comparator/latch circuit (32) is operable to compare the difference on the output of the last stage of the ring oscillator (22) and the output of the comparator/latch (32) is then sampled by a CPU (12) that is operated on a separate master clock (18). This allows the master clock (18), upon which the sample operation is based, to be completely separate from the ring oscillator (22).

Switching amplifier closed loop dual comparator modulation technique

Abstract: The invention relates to switching Class D audio amplifiers and, in particular, to full bridge dual comparator audio Class D amplifiers. A dual comparator pwm audio amplifier comprises a differential-to-single ended feedback amplifier 40 coupled to an integrating amplifier 42 to provide more precise feedback control for the comparators 12, 16.

Inexpensive motion control using DC motors

Abstract: Disclosed herein is a motion monitoring system for monitoring movement of a brush-type DC motor. The system includes an electrical comparator having first and second differential inputs. A current detector is connected to provide a drive current signal to the first differential input of the comparator. A low-pass filter is connected to provide an averaged drive current signal to the second differential input of the comparator. When a drive current is applied to the motor, the comparator produces a stream of binary logic-level pulses corresponding to motor movement. The pulses can be used to determine motor position and velocity.

A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection

Abstract: A fully differential comparator is described. It uses a switched-capacitor differencing circuit that provides common-mode rejection. The comparator has been tested by building a 3-b flash analog-to-digital converter (ADC) in a 2-/spl mu/m CMOS process. With a supply voltage of 3.3 V, a sampling rate of 25 MHz, and full-scale sinusoidal inputs up to 7 MHz, the signal-to-distortion ratio of the ADC when the input is single ended is about 1-2 dB less than when the input is differential. In a 2-/spl mu/m CMOS process, the comparator occupies 0.25 mm/sup 2/ and dissipates 1.05 mW.

Alternating current power control device

Abstract: An alternating current power control device including a phase comparison controller for comparing a phase of an input voltage with that of a first reference voltage, a single-winding transformer for varying the input voltage, a mutual induction reactor for lowering the input voltage by a desired level in response to an output voltage from the single-winding transformer, an output voltage comparator for comparing an output voltage with a second reference voltage, an output current comparator for comparing an output current with a reference current, an OR logic controller for performing an OR operation with respect to output signals from the phase comparison controller and output current comparator, and a switch array for selectively transferring the output voltage from the single-winding transformer to the mutual induction reactor in response to output signals from the output voltage comparator and OR logic controller. According to the present invention, the mutual induction reactor is implemented on the basis of the principle of a linear transformer and has a small capacity corresponding to about 1/10 of a load power. Therefore, a proper power necessary to the saving of energy can be supplied by using the mutual induction reactor.

IC (current-capacitor) precision oscillator having frequency and duty cycle controls

Abstract: A precision oscillator circuit having a wide adjustable operating frequency range and an adjustable duty cycle. The precision oscillator use a window comparator circuit for monitoring a voltage of a capacitive element. The window comparator circuit has a first operating voltage edge and a second operating voltage edge wherein the first operating voltage edge latches an output signal of the window comparator circuit at one level when the voltage of the capacitive element is greater than the first operating voltage edge. The second operating voltage edge brings the output signal of the window comparator circuit back to an initial level when the voltage of the capacitive element is greater than the second operating voltage edge. A precision current reference source is coupled to the capacitive element and to the window comparator circuit. The precision current reference is used for generating currents which are insensitive to temperature, supply voltage, and process variations. The currents are used for charging and discharging the capacitive element. The currents are adjustable in order to vary an amount of time it takes to charge and discharge the capacitive element. This allows for the altering of the frequency as well as the duty cycle of the output signal of the window comparator circuit.

Multivalued FSK demodulation window comparator

Abstract: A multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator, a reception electric field strength detector, and a reference voltage generating circuit. The MSB comparator determines at least the polarity of a frequency shift of a radio frequency. The LSB comparator determines the absolute value of the frequency shift of the radio frequency. The reception electric field strength detector detects the strength of a radio signal and outputs a signal corresponding to the detected strength. The reference voltage generating circuit changes the reference voltages of the LSB comparator in accordance with an output voltage from the reception electric field strength detector. When the output voltage from the reception electric field strength detector is not higher than a predetermined level, a reference voltage from the reference voltage generating circuit changes.

Auto-reference pseudo-flash analog to digital converter

Abstract: The n-bit A/D converter of the present invention includes a resistor network, n comparators, and (2 n -1-n) multiplexers. The resistor network generates a plurality of reference voltages characterized by uniform voltage increments between two fixed voltages. The n comparators are coupled to the resistor network. Each comparator receives a reference voltage and an analog input signal. Based on these inputs, an ith comparator generates an ith bit output in the n-bit digital signal where i ranges from 1 to n with the first bit being the most-significant-bit and the nth bit being the least-significant-bit. The (2 n -1-n) multiplexers are coupled between the resistor network and the ith comparator. In response to the output of comparators (except for the first comparator) associated with the more significant bits, the (2 i-1 -1) multiplexers select a reference voltage and transmit it to the ith comparator. The ith comparator then compares the selected reference voltage with the analog input signal and generates the ith bit output.

Median reference voltage selection circuit

Abstract: A comparator circuit performs at least three compare operations, wherein in each compare operation the comparator compares two of at least three reference voltages to one another and provides a signal to indicate which of the two reference voltages is greater. A decode logic circuit in response to the signals provided by the comparator circuit in the at least three compare operations selects the median reference voltage from among the at least three reference voltages, and causes a multiplexer to transfer the median reference voltage to an output terminal of the mux.

Phase locked loop and multi-stage phase comparator

Abstract: The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.

Pll frequency synthesizer and method for controlling the pll frequency synthesizer

Abstract: A PLL frequency synthesizer which is provided with a voltage detector (9) which detects the present value of a control voltage applied to a voltage-controlled oscillator (6), a storage device (7) which stores in advance the set values of a plurality of control voltages corresponding to the set values of a plurality of frequency dividing numbers set in a frequency divider (2) and outputs the set value of the control voltage corresponding to the frequency dividing number set in the frequency divider by selecting the set value out of the set values of the control voltages, a voltage value comparator (8) which compares the present value of the control voltage detected by the detector (9) with the set value of the control voltage outputted from the device (7), and a switching circuit (10) which outputs either the phase difference signal generated by means of a phase comparator (3) and representing the phase difference between the phase of a frequency dividing signal outputted from the divider (2) and that of a reference frequency signal or the output signal of the comparator (8) by switching. The comparator (8) controls the circuit (10) so that a charge pump (4) can be driven with its own output signal when the difference between the present value of the detected control voltage and the set value of the control voltage from the device (7) is larger than a prescribed value or with the phase different signal from the phase comparator (3) when the difference is not larger than the prescribed value.

Step-up continuous mode DC-to-DC converter with integrated fuzzy logic current control

Abstract: A step-up continuous-mode DC-to-DC converter with integrated current control, comprising a comparator for comparing a voltage signal output from the converter and a reference signal for generating an error signal and circuitry for generating a compensation ramp which generates a ramp signal which is added to a signal which is proportional to a current ramp that flows across the converter. The signal output from the comparator and the signal obtained from the sum are sent to an additional comparator, the output whereof, together with an oscillator signal, is used for driving a power transistor of the converter. A fuzzy logic control unit is interposed between the comparator and the additional comparator, the fuzzy logic control unit receiving at its input the error signal output by the comparator and emitting in an output signal which depends on the variation of the error signal over time to be sent to the additional

Phase comparator circuit for high speed signals in delay locked loop circuit

Abstract: A phase comparator compares the phases of first and second signals with each other. The phase comparator has a first control circuit, a second control circuit, and a phase comparator unit. The first control circuit divides the frequency of the first signal by n in response to a third signal where n is an integer equal to or larger than 2. The second control circuit divides the frequency of the second signal by n in response to the third signal. The phase comparator unit compares the phases of signals provided by the first and second control circuits with each other. The phase comparator unit is capable of correctly comparing the phases of even high-speed signals with each other, and therefore, is applicable to a DLL circuit that operates on high-speed clock signals.

Method and circuit for current limiting of DC-DC regulators

Abstract: A method and circuit (10) for limiting current (I COIL ) in a load (16). The current limiting circuit (10) includes a sensing circuit (12) having a current indicator output terminal (20) connected to an inverting input of a comparator (11). A reference voltage node (24) of a reference voltage generator (13) is connected to the non-inverting input of the comparator (11). The comparator (11) generates an output signal in accordance with the current flowing in the load (16). If an overcurrent condition exists, the signal from the comparator (11) disables a control circuit (14) which turns off the sensing circuit (12). With the control circuit (14) disabled and sensing circuit (14) off, the current (I COIL ) is prevented from flowing through the load (16).

Comparator for semiconductor testing device

Abstract: A comparator circuit for differential output signals which is not affected by a common mode noise on the differential signals. The comparator circuit is advantageously used for testing differential output signals from a device under test (DUT). The comparator circuit includes an offset circuit for receiving differential signals from the DUT and generating a pair of balanced output signals which is provided with a predetermined offset voltage therebetween, and a comparator for receiving the pair of output signals from the offset circuit and comparing voltages between the output signals.

Offset compensation circuit for integrated logarithmic amplifiers

Abstract: A circuit for compensating for the input offset voltage of a logarithmic amplifier includes a digital comparator, a logic circuit, and a digital-to-analog converter (DAC) in a feedback loop. The comparator is connected to the output of the log amplifier and digitally indicates the polarity of the input offset voltage when the amplifier input is set to zero. The logic circuit uses the digital output of the comparator to form an adjustable digital compensation signal. This digital compensation signal is applied to the DAC to generate an analog compensation signal that is injected into the input of the logarithmic amplifier to cancel the input offset voltage. The process is repeated until the proper or best compensation signal is produced.

Differential comparator with fixed and controllable hysteresis

Abstract: A differential comparator having a low-offset comparator and two processing paths, each of which receives one of the two primary inputs to the differential comparator and generates one of the two inputs to the low-offset comparator. The output of the low-offset comparator is the output of the differential comparator. Each processing path is capable of (1) generating an offset voltage and (2) turning on and off the generation of that offset voltage. In a preferred embodiment, each processing path has a passive resistor that generates the offset voltage and a pair of shunt transistors that selectively shorts out the passive resistor. The output of the low-offset comparator is connected (either directly or indirectly through an inverter) to the gates of the shunt transistors. The shunt transistors are therefore controlled by the output of the low-offset comparator. In each of two modes of operation, a different one of the passive resistors is "on" while the other passive resistor is "off." The result is a differential comparator that operates with hysteresis. The currents passing through the passive resistors to generate the offset voltages are mirrored from a current source that is controlled by a reference voltage. As such, the offset voltages can be controlled by adjusting the reference voltage. The differential comparator is capable therefore of operating with fixed and controllable hysteresis.

Robust high-accuracy high-speed continuous-time CMOS current comparator

Abstract: The authors present a CMOS current comparator which employs nonlinear negative feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns at 50 nA). The new structure features a speed improvement of more than two orders of magnitude for a 1 nA input current, when compared to the fastest reported to date.

Memory suitable for operation at low power supply voltages and sense amplifier therefor

Abstract: A memory (400) includes a sense amplifier (500) formed with current-to-voltage converters (512, 513) connected to multiple bit lines, with a common current source (548) forming a current reference, and a common latching comparator (530). A column decode select circuit (515) which selects one of the multiple bit lines is interposed between the current-to-voltage converters (512, 513) and an input of the latching comparator (530). The distribution of the components of the sense amplifier (500) allows operation at low power supply voltages. The sense amplifier (500) uses a clamp and a loading device to establish a first discharge rate on a reference input of the latching comparator (530). The state of the selected memory cell establishes a second discharge rate on another input of the latching comparator (530), which is greater or less than the first discharge rate depending on the state of the memory cell. Portions of the comparator (530) also double as latches during a program mode.

Method and apparatus for performing digital thermal asperity detection

Abstract: An improved thermal asperity detector is disclosed for detecting short thermal asperities using a variable time threshold. The thermal asperity detector includes a saturation detector, and a comparator system. The comparator system may include a polarity latch, a processor, a level comparator and a timing comparator. The saturation detector compares a programmable saturation threshold to an A/D sample to generate an enable signal in response to the A/D sample exceeding the saturation threshold. The polarity latch receives the A/D sample and the enable signal, and records the most significant bit of the A/D sample to identify the polarity of the saturation and to provide an output signal representative thereof in response to the enable signal. The processor generates a threshold level control signal based upon a programmable level threshold and the polarity latch output signal. The level comparator compares the A/D sample and the output from the polarity latch in response to the enable signal, and generates a timing output signal to a timing comparator in response to the comparison of the A/D sample and the output from the polarity latch. The timing output signal represents a number of succeeding A/D samples that surpasses the dynamically shifted level threshold. The timing comparator compares the timing output signal from the level comparator and a programmable time threshold in response to the enable signal. Finally, the timing comparator generates a thermal asperity indication when the succeeding A/D samples surpass the dynamically shifted level threshold for the programmable time threshold.

A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS

Abstract: This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V.

Multi level comparator for demodulator

Abstract: In a demodulator circuit including a multi-level comparator, the demodulator circuit obtaining output data through comparison, made in a four-level comparator and a NRZ comparator, of a signal obtained by subjecting a received signal to a process of detection and predetermined threshold levels, comprises a level detector circuit for detecting the level of the received signal transmitted through the process of detection and a control circuit for controlling relative magnitudes of the level detected in the level detector circuit of the signal transmitted through the process of detection and the predetermined threshold levels for the four-level comparator and the NRZ comparator, whereby stabilized output data conforming to changes in the level of the detected output are made obtainable.

Voltage comparator with floating gate MOS transistor

Abstract: This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.

Analog-to-digital converter using weighted capacitor array and interpolating comparator

Abstract: A charge redistribution analog-to-digital converter uses an interpolative comparator to determine multiple bits in a single comparator decision cycle. The result is a speed improvement in the conversion period with little or no increase in power dissipation.

Chopper comparator and A/D converter

Abstract: A chopper comparator is constructed by connecting current control transistors Q 15 to Q 17 comprising p-channel MOSFETs between CMOS inverters 3 to 5 and a power source 7 to supply a power voltage V DD . A control signal V C to control a current flowing in the CMOS inverters 3 to 5 is supplied to gates of the current control transistors Q 15 to Q 17 . In case of constructing the A/D converter, the chopper comparator is used.

Driver having inductance-controlled current slew rate

Abstract: A control system for minimizing and controlling the current slew rate of an output device by using inductance to directly measure the current slew rate is provided. The control system may, for example, be used to control and minimize the current slew rate through signal drivers and allow for faster drivers and/or larger numbers of drivers on integrated circuit chips. In accordance with one embodiment of the invention, an inductor is serially coupled with an output device. A predriver is coupled to the gate of the output device for providing a voltage slew rate at the output device gate. A comparator is coupled to the inductor for sensing a voltage indicative of a current slew rate through the inductor and outputing a signal indicating whether the current slew rate exceeds or falls below a desired level. A controller responsive to the comparator is provided for controlling the driver to increase and decrease the voltage slew rate at the output device gate when the comparator signal indicates that the current slew rate respectively falls below and exceeds the desired level, thereby controlling the current slew rate through the inductor and through the output device.

Investigation of the signal resolution of a high-T/sub c/ balanced comparator

Abstract: The use of high-T/sub c/ Josephson junctions for digital applications requires a careful study of the influence of thermal noise on circuit performance. We investigated a balanced current comparator, which contains a basic component of all RSFQ circuits: two overdamped Josephson junctions connected in series. The dependence of the dc-voltage across the Josephson junctions on signal current was measured to determine the threshold uncertainty of switching of the comparator. The experimental data obtained at different sampling pulse frequencies, in a temperature range from 10 to 50 K, were compared with a theoretical model, taking into account the influence of thermal noise as well as of sampling pulse frequency.

A/D converter with auto-zeroed latching comparator and method

Abstract: An A/D converter has an auto-zeroed latching comparator with an input offset voltage. The latching comparator is repetitively switched between an offset adjustment mode and a conversion mode. When the comparator is in the offset adjustment mode, the comparator compares the reference voltage to itself and generates an offset measurement output based on the comparison. A feedback circuit adjusts the input offset voltage based on the offset measurement output. When the comparator is in the conversion mode, the comparator compares the input signal to the reference voltage and generates the digital output signal based on the comparison.

Voltage regulator circuit

Abstract: A power regulation circuit features an improved regulation circuit for use with a voltage multiplier circuit, such as a Vccp pump for a DRAM The power regulation circuit includes: a high-gain differential comparator, dual input level translators, and a constant current bias generator The dual input level translators lower the respective voltage levels of a reference voltage level and the output of the power regulation circuit, which is monitored to provide the desired regulation The translated input signals are coupled as inputs to the differential comparator Translation keeps the inputs within the input common mode range of the differential comparator The differential comparator acts in concert with the constant current bias generator to regulate the output of the power regulation circuit at a constant and steady level Using current mirrors, the constant current bias generator provides a fixed voltage for ensuring that approximately the same amount of current passes through each of the dual level translators Feedback is provided from the output of the regulation circuit to the differential comparator to provide the desired level of hysterisis control