Showing papers on "Comparator applications published in 2006"

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Abstract: A comparator-based switched-capacitor circuit (CBSC) technique is presented for the design of analog and mixed-signal circuits in scaled CMOS technologies. The technique involves replacing the operational amplifier in a standard switched-capacitor circuit with a comparator and a current source. During charge transfer, the comparator detects the virtual ground condition in place of the opamp which normally forces the virtual ground condition. A prototype 1.5-bit/stage 10-bit 7.9-MS/s pipeline ADC was designed using the comparator-based switched-capacitor technique. The prototype ADC was implemented in 0.18-mum CMOS. It achieves an ENOB of 8.6 bits for a 3.8-MHz input signal and dissipates 2.5 mW

Method and apparatus for AD conversion, semiconductor device for detecting distribution of physical quantity, and electronic apparatus

Abstract: A column analog-to-digital converter having a voltage comparator and a counter is arranged for each a vertical signal line. The voltage comparator compares a pixel signal inputted via the vertical signal line at each row control signal line with a reference voltage, thereby generating a pulse signal having a length in time axis corresponding to the magnitude of a reset component and a signal component. The counter counts a clock to measure the width of the pulse signal until the end of the comparison operation of the comparator, and stores a count at the end of the comparison. A communication and timing controller controls the voltage comparator and the counter so that, in a first process, the voltage comparator performs a comparison operation on a reset component with the counter performing a down-counting operation, and so that, in a second process, the voltage controller performs the comparison operation on a signal component with the counter performing an up-counting operation.

A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS

Abstract: A 5-bit flash ADC incorporates 20 ?m by 20 ?m inductors to improve both comparator pre-amplification bandwidth and regeneration speed. A switched-cascode scheme reduces comparator kickback. Offset cancellation is achieved by modifying the comparator reference voltages without degrading high-speed performance. The ADC achieves a measured SNDR of 27.5 dB for a 5 MHz input at 4 GS/s, and 23.6 dB for a 1 GHz input at 3.5 GS/s. The power consumption (including clock buffer and ladder) is 227 mW at 3.5 GS/s. The active area is 0.658 mm2.

A New High Precision Low Offset Dynamic Comparator for High Resolution High Speed ADCs

Abstract: A new low offset dynamic comparator for high resolution high speed analog-to-digital application has been designed. Inputs are reconfigured from the typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta-stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs. Simulation based sensitivity analysis is performed to demonstrate the robustness of the new comparator with respect to stray capacitances, common mode voltage errors and timing errors in a TSMC 0.18? process. Less than l0mV offset can be easily achieved with the proposed structure making it favorable for flash and pipeline data conversion applications.

Synchronous rectifier having precise on/off switching times

Abstract: A synchronous rectifier, including an energy storage element having a terminal; a power supply input, connected to the terminal of the storage element in a first time interval; a reference line connected to the terminal of the storage element in a second time interval; and a zero comparator, coupled to the terminal of the storage element to detect a current flowing in the energy storage element and disconnect the terminal of the storage element from the reference line upon detecting a zero current, the zero comparator having an offset and a propagation time; the zero comparator further having an offset control input and an output. An offset regulating loop is coupled between the output of the zero comparator and the offset control input and regulates the offset of the zero comparator to compensate the propagation time.

Switching Regulator Capable of Compensating Output Errors

Abstract: A switching regulator includes a power stage, an output capacitor, a first reference voltage generator, a comparator, a constant-time trigger, an error amplifier, and an operator. The power stage includes a first switch, a second switch, and an output inductor. The comparator is coupled to the output inductor and the operator for receiving an output voltage and a compensation reference voltage. The error amplifier is coupled to the output inductor and the reference voltage generator. The constant-time trigger is coupled to the comparator and the power stage. The operator is coupled to the reference voltage generator and the error amplifier.

Multi-mode ADC and its application to CMOS image sensors

Abstract: An analog-to-digital converter apparatus for analog source signals of one polarity, includes one comparator formed from transistors, a block of digitally addressable voltage sources to set a reference voltage of the comparator, an asynchronous n-bit digital counter, a block of digitally addressable voltage sources to set the potential to be applied to the signal source, a digital control unit, a block storing the calibration data for an input capacitor of the comparator, and a base-2 multiplier block, being interconnected by lines, including a line connecting the input analog signal to the drain of a pass transistor, a line connecting the block of voltage sources to be connected to the signal source, a line connecting the digital control unit to transistor gates, and a line carrying the signal Vref from the block of digitally addressed voltage sources to the comparator.

System and method for an adaptive synchronous switch in switching regulators

Abstract: Techniques for an adaptive synchronous switch in switching regulators are described, one aspect of which is to achieve a more optimal on/off timing of a synchronous switch that is controlled by the comparator in a feedback control loop and thereby improves power conversion efficiency and system performance; One approach samples a node in the output of the switching regulator and generates a sampled error signal that is analyzed to determine if the current comparator offset is too high or too low relative to a target switching regulator output value at least in part based on the sampled error signal value, and accordingly generates a compensated feedback error signal and applied to the compensated feedback error signal to an input of the comparator to have the effect of a comparator offset adjustment signal.

Low-gain current-mode voltage regulator

Abstract: In a low-gain current-mode voltage regulator having a PWM comparator in response to the varying output voltage and inductor current of the voltage regulator to produce a PWM signal to regulate the output voltage, an offset signal is derived from a subtraction between the inputs of the PWM comparator, and the offset signal is injected into the PWM comparator to cancel the output offset of the voltage regulator.

Comparator-based switched capacitor circuit for scaled semiconductor fabrication processes

Abstract: Described is a switched capacitor circuit for performing an analog circuit function. Unlike conventional switched capacitor circuits employing operational amplifiers, the switched capacitor circuit uses a comparator and does not require direct feedback between the input and output of the comparator. The switched capacitor circuit includes a first and a second switched capacitance network, a comparator and a current source. The first switched capacitance network has an input terminal to receive a circuit input voltage during a first phase. The comparator has an input terminal in communication with the first switched capacitance network and an output terminal in communication with the second switched capacitance network through a switched terminal. The current source communicates with the switched capacitance networks and supplies a current to charge the networks during a second phase. The circuit can be used, for example, to provide high gain amplification in integrated circuits.

Half-bridge for capacitive sensing

Abstract: Methods and apparatus are provided for measuring a ratio of capacitances. The apparatus include a comparator including a comparator input, a comparator output, and a reference voltage; a first capacitive element including a first capacitance, a first electrode coupled to the comparator input, and a second electrode; a first biasing element coupled to the first electrode; a digitally-controlled voltage waveform generator for generating a varying waveform, the voltage waveform generator including a voltage waveform generator output coupled to the second electrode; a second capacitive element including a second capacitance and a third electrode coupled to the comparator input; and a controller coupled to the comparator output, the controller configured to control the digitally-controlled voltage waveform generator, wherein an output signal of the comparator is dependent on a ratio comprising the first capacitance and the second capacitance, and the first capacitive element and/or the second capacitive element has a variable capacitance.

Asymmetric comparator for use in pixel oversaturation detection

Abstract: An imaging circuit using an asymmetric comparator to detect an oversaturated pixel is disclosed. The comparator employs a transistor differential pair which are fabricated to be slightly unbalanced. By varying the channel widths of the two transistors during fabrication, the voltage required to trigger the comparator can be raised or lowered as desired to set an oversaturation level which triggers the comparator.

Step-down switching regulator

Abstract: In a control circuit which turns on/off the switching device elements included in a synchronous rectifier step-down switching regulator, a hysteresis comparator compares the detection voltage that corresponds to the output voltage of the step-down switching regulator with a first threshold voltage and a second threshold voltage. A light-load detection circuit detects whether or not a load is in the light-load state. A driver circuit turns on/off the switching device elements according to the pulse signal output from the hysteresis comparator. Upon the light-load detection circuit detecting the light-load state, the hysteresis comparator shifts the second threshold voltage toward the higher-voltage side by a predetermined voltage difference.

Circuit with Q-enhancement cell having feedback loop

Abstract: According to an example embodiment, an amplitude feedback loop may include an RF amplifier, a detector, a comparator, and a Q-enhancement cell. In an example embodiment, the RF amplifier has an output signal, and the detector has an input coupled to the output signal of the RF amplifier and is configured to detect a level of the output signal of the RF amplifier. The comparator circuit may receive as inputs a reference voltage and the output of the detector. Also, the comparator circuit is configured to output a control signal based on a difference between the reference voltage and the output signal of the power detector. The Q-enhancement cell may be coupled to the RF amplifier and have an input coupled to an output of the comparator circuit. A bias current of the Q-enhancement cell may be adjusted based on the control signal output by the comparator circuit.

Novel comparator circuit with schmitt trigger hysteresis character

Abstract: A circuit and a method are provided to produce a novel comparator with Schmitt trigger hysteresis character. The circuit includes a current source which controls the magnitude of current flow through this comparator circuit. It has a first logic device which is turned ON by a reference voltage, and a second logic device is turned ON by a comparator input voltage. A first feedback device is turned ON by a negative comparator output. A first parallel resistor is connected in parallel to the first feedback device. A second feedback device is turned ON by a positive comparator output. A second parallel resistor is connected in parallel to the second feedback device. The first and second parallel resistors are used to provide the differential comparator with switching voltage offsets which result in the Schmitt trigger hysteresis character.

PWM/burst mode switching regulator with automatic mode change

Abstract: A switching regulator automatically operates in pulse width modulation (“PWM”) mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.

Switching regulator for fixing a frequency

Abstract: A switching regulator includes a power stage, an output capacitor, a first reference voltage generator, a comparator, a constant-time trigger, a frequency-to-voltage converter, and an error amplifier. The power stage includes a first switch, a second switch coupled to the first switch, and an output inductor. The comparator is coupled to the output capacitor, and output inductor, and the first reference voltage generator. The constant-time trigger is coupled to the comparator and the power stage. The error amplifier includes a first input end coupled to the frequency-to-voltage converter, a second input end, and an output end coupled to the constant-time trigger.

Comparator and a/d converter

Abstract: In a comparator for use in a parallel A/D converter, the comparator (100) is provided with reset transistors (mra, mrb). When the comparator (100) is in reset state, the PMOS transistors (mra, mrb) are provided with the inverted signal /CLK of a clock signal and the voltages at two internal nodes (Va, Vb) becoming a differential pair are reset forcibly to a predetermined reset voltage by the reset transistors (mra, mrb). The inverted signal /CLK of a clock signal is generated with a predetermined time lag. When the comparator (100) is in reset state, reset release timing of the internal nodes (Va, Vb) is delayed behind the comparison operation timing of the comparator. Consequently, even if the frequency of the clock signal and the frequency of an analog input signal are increased, voltage balance is improved at the internal nodes forming a differential pair when the comparator is in reset state, and voltage comparison precision is enhanced.

High Linearity Modulation System and Modulation Method

Abstract: A modulation system and method having a high linearity. The system is a PWM modulator or a class D amplifier and includes an integrator, a low pass filter (LPF), a comparator, and an output circuit. The LPF is located before the comparator. Jitter noise produced by the comparator and/or switching noise of the output circuit are removed by feedback to the input. Thus, the linearity of the modulation system is provided.

Offset correction during correlated double sampling in CMOS image sensor

Abstract: For correlated double sampling in an image sensor, a comparator receives and compares a reset signal and a sensing signal from a pixel of the image sensor. Also, a controller adjusts a voltage at a controlled input of the comparator to compensate for offset of the comparator from feed-back of an output of the comparator. The controller includes at least one charging current source and at least one discharging current source that are controlled to adjust such a voltage.

Apparatus and method for increasing a slew rate of an operational amplifier

Abstract: An apparatus and method for increasing a slew rate of an operational amplifier are provided. It only requires an operational amplifier, a monitoring control device, a push-pull output device, and a second input current source pair. It uses a monitoring control device controlled by the output stage to control the supplementary device and the second input current source pair in order to increase a slew rate of an operational amplifier. This operational amplifier also provides the rail-to-rail output function. In addition, because it does not require additional circuit to increase the slew rate, the chip size is smaller. With respect to the circuit structure, it is very simple and can be applied to the pre-existing operational amplifier without re-designing the operational amplifier and thus can keep the original characteristics of the operational amplifier.

Analog-to-digital converter with reduced power consumption in CMOS image sensor

Abstract: An analog-to-digital converter includes a comparator, a latch, and a bias control unit. The comparator is turned on by an applied bias voltage for comparing an analog voltage with a ramp voltage. The latch activates an end signal when the ramp voltage becomes greater than the analog voltage as indicated by the comparator. The bias control unit uncouples the bias voltage from the comparator when the end signal is activated for reducing power consumption.

High speed comparator offset correction

Abstract: An offset canceling buffer receives a reference voltage, and provides a modified reference voltage to a comparator. The modified reference voltage operates to cancel any comparator offset. The offset canceling buffer includes a digitally controllable current source to steer current in different paths based on comparator offset.

Insulation resistance detecting apparatus

Abstract: There is provided an insulation resistance detecting apparatus that accurately calculates an insulation resistance value in real time. The insulation resistance detecting apparatus includes: pulse generator 10 , comparator 11 to which reference voltage V REF is supplied as one input and an output from pulse generator 10 is supplied as the other input, comparator 11 that outputs a low-level signal when the level of the other input exceeds reference voltage V REF , and that outputs a high-level signal when the level of the other input is lower than reference voltage V REF ; resistance R 1 provided on the output line of pulse generator 10 in series; coupling capacitor C 2 one end of which is connected to the other input line of comparator 11 and the other end of which is connected to the output line of high-voltage DC power supply 21 ; capacitor C 1 one end of which is connected to the other input line of comparator 11 and the other end of which is connected to a ground; and pulse width measuring device 12 that calculates the value of insulation resistance on the output line of high-voltage DC power supply 21 from the duty ratio of an output waveform of comparator 11.

A Low-Power 4GHz Comparator in 120nm CMOS Technology with a Technique to tune Resolution

Abstract: This paper presents a comparator with the capability of a high decision speed, but static power consumption was avoided. Furthermore the circuit implements a technique to enhance resolution while keeping the ability of a high switching speed. During the reset phase the comparator is pulled to ground level, which defines a logic voltage level. A test chip with the comparator was manufactured in a 120nm CMOS technology with a supply-voltage of 1.5V. For a bit-error-rate (BER) of 10-9 the presented comparator is able to detect 11.2mV at 2GHz, 20mV at 3GHz, 26mV at 3.5GHz and 118mV at 4GHz. The power consumption was 788muW at 3.5GHz and 812muW at 4GHz

Power detection circuit for non-contact IC card or RFID tag

Abstract: A power detection circuit has a first comparator block, a charge controller block, and a second comparator block. The first comparator block compares a supply voltage with a first threshold value, and the charge controller block controls the charging of a first capacitor according to an output signal of the first comparator block. The second comparator block compares the charge in the first capacitor with a second threshold value so as to produce a power detection signal, and wherein a second capacitor is interposed between the charge controller block and the first capacitor.

Frequency modulator and FM transmission circuit using the same

Abstract: An input signal is input via a first resistor to an inverting input terminal of an operational amplifier. A second resistor is provided on a feedback path between an output terminal and the inverting input terminal of the operational amplifier. A control voltage Vcnt output from the operational amplifier is input to a VCO. A frequency divider frequency-divides an output signal Sout of the VCO. A phase comparator compares an output signal from the frequency divider with a reference clock signal and outputs a voltage according to a phase difference. A loop filter removes a high-frequency component of an output voltage Vcp of the phase comparator and outputs the voltage to a non-inverting input terminal of the operational amplifier.

High Speed Low Power CMOS Comparator for Pipeline ADCs

Abstract: This paper describes and analyzes a low power and high speed differential comparator. The designed comparator is intended to be implemented in a 10bit 20MHz pipeline analog-to-digital converter dedicated to RF WLAN applications. This comparator is based on the switched capacitor network using a two-phase nonoverlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8mum CMOS AMS process parameters, with a power supply voltage of 5V and an input common mode of 2-3V, show that this comparator exhibits a propagation delay of 17.3ns, a good accuracy and a low power consumption of about 0.8mW

Magnetic sensor signal detection circuit using a counter

Abstract: A signal detection circuit of a magnetic sensor includes a differential amplifier to which an output voltage of a detecting coil of the magnetic sensor is applied; a comparator to which the output of the differential amplifier is input, the comparator outputting a digital signal having one logical value during a time period between two adjacent spike voltages included in the output voltage; and a counter that counts the number of pulses of a clock in a period when the output of the comparator has one logical value.

Method for accurate current sensing in power converters

Abstract: A simple digital-to-analog converter (DAC) may be used to monitor a load current. The DAC may be configured to generate a voltage corresponding to an estimate of an average value of the load current. A comparator may be used to compare that voltage with a sense voltage corresponding to the actual load current. The estimate may then be adjusted based on a sample of the comparator output, allowing the estimate to track the load current over time, thus providing an average measurement capability without using a fast analog-to-digital converter. The DAC may additionally be configured to generate respective voltages corresponding to specified over-current (OC) and under-current (UC) values. The comparator may then be used to compare these respective voltages with the sense voltage to respectively detect OC and UC faults. Noise immunity may be increased by integrating a number of comparator samples instead of a single comparator sample before adjusting the estimate. Increased noise immunity may also provide a measure of the error between the estimate and the actual load current, improving the efficiency of monitoring the load current.