Showing papers on "Current divider published in 2004"

Dual loop architecture useful for a programmable clock source and clock multiplier applications

Abstract: A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.

55GHz CMOS frequency divider with 3.2GHz locking range

Abstract: LC-resonator frequency dividers are used for high-speed operation. In particular a differential injection locking frequency divider is promising as a millimeter-wave-band divider However, its locking range is narrow and insufficient for practical use. In this paper, several layout techniques are described to improve the performance of the frequency divider, and the performance improvement is verified using a five-layer-metal and 0.2-/spl mu/m-gate CMOS process. Measurement results reveal the minimum and maximum operating frequencies to be 52.7 GHz and 55.9 GHz with 10.1 mW at a supply voltage of 1.0 V.

Circuit and method for detecting insulation faults

Abstract: A circuit for monitoring the resistance between the terminals of a battery and a first reference potential has two inputs which are each to be connected to one of the terminals of the battery, and a voltage divider. The voltage devider has two external connections each of which is connected to one of the inputs, and a central connection which is to be connected to the first reference potential. First and second switches are arranged in series in a connection between one of the external connections of the voltage divider and one of the inputs. A measuring instrument is connected to the external connections of the voltage divider, for supplying a monitoring signal which is representative of the voltage between the external connections.

Methods and apparatus for producing a three-state single wire control

Abstract: Systems, methods and devices are described that provide a three-state control signal across a single electrical conductor. A three-position switch provides an output signal that selects between the first reference voltage, a second reference voltage and an intermediate voltage. The output from the switch is transmitted to a voltage divider circuit that produces a predetermined result when the switch output corresponds to the intermediate state. The output of the voltage divider is then provided to an analog-to-digital converter to decode the state of the switch. The three-state control signal may be used, for example, to place a vehicle component such as a windshield temperature controller or rear-window defogger into a desired one of three operating states. Similarly, the three-state concepts may be widely applied in many automotive, industrial, consumer electronics and other settings.

Precision three-stage 1000 V/50 Hz inductive voltage divider

Abstract: A separately excited three-stage inductive voltage divider (IVD) has been designed for voltages up to 1000 V at frequencies from 50 Hz to 1000 Hz. The IVD provides output to input voltage ratios of 0.001 to 0.01 with in-phase and quadrature uncertainty of the ratio better than 1 /spl times/ 10/sup -6/.

Boost-biased level shifter

Abstract: A boost-biased level shifter is described. In the preferred embodiments of the present invention, a voltage divider circuit divides the high voltage applied on the receiver circuit that receives the input signal, a refresh and self-bias circuit maintains and refreshes a bias voltage that is high enough to turn on the transistors in the voltage divider circuit, and a voltage output circuit outputs a signal having the amplitude of a higher power supply source, which is higher than the input signal amplitude. The preferred embodiments can operate at input signals having a lower amplitude. The performance is improved.

Current driver and display device

Abstract: A current driver to which image data including a plurality of grayscale values is input and which outputs an electric current according to the grayscale values of the image data, the current driver comprising: a first input section to which a first reference current is input, a current value of the first reference current being changed according to the grayscale values of the image data; a second input section to which a second reference current is input, the second reference current having a current value different from that of the first reference current; and a current divider circuit which uses the second reference current and the first reference current to output an electric current, the electric current having a value equal to or higher than that of the first reference current and equal to or lower than that of the second reference current.

Bias current generators with wide dynamic range

Abstract: This paper describes CMOS circuits that generate a wide-ranging set of fixed bias currents, spanning at least 6 decades down to picoamperes. A master current generated by a bootstrapped current reference is successively divided by a current splitter to generate the desired references. An unpublished startup circuit and a power control mechanism are described. Measurements from a 0.35/spl mu/m implementation are presented and non-idealities are investigated. Readers are directed to a design kit that makes it simple to generate the layout for a bias generator with a set of desired currents for scalable MOSIS CMOS processes.

A new single-phase multilevel current-source inverter

Abstract: A new single-phase multilevel current-source inverter (CSI) topology is proposed. The structure of this new topology is very simple. The switching strategy that can ensure equal current division among the branches and current harmonics reduction is presented. Simulations as well as practical experiments analyze the characteristics of this new topology.

Analysis and experimentation of a new three-phase multilevel current-source inverter

Abstract: Multilevel converter technology has been mainly used for voltage-source inverters (VSI) by now. But with the development of the superconducting magnetic energy storage (SMES) technology, superconducting inductors can be used as higher efficiency energy storage elements, the application of current source multilevel inverters (CSI's) in power systems will be more and more popular. A new kind of three-phase multilevel CSI topology is presented in this paper. The new multilevel CSI's synthesize the staircase current wave from several levels of balance inductor currents. The switching strategy that can ensure equal current division among the branches and current harmonics reduction is presented. A three-phase 6-level CSI and a three-phase CSI using the new topology are discussed by the simulations. An experimental prototype of a three-phase 6-level CSI has been built to practise the proposition in the paper.

Dual stage voltage regulation circuit

Abstract: A voltage regulator (Fig. 1), for supplying a high current load and a low current load, employs a feedback loop to supply the low current load with a fine degree of regulation and a feed forward arrangement to supply the high current load with a coarse degree of regulation. The feedback loop employs a bandgap reference source (13) feeding a comparator (17), with an output driver transistor (21) drawing current from a common supply (Vcclext) and having an output electrode (Vcc- int) connected to a voltage divider (31, 33), allowing a sample of the output to be fed back (39) to the comparator to maintain the desired output voltage. The output electrode also feeds (35, 45) a control transistor (47) for the feed forward arrangement that also draws current from the common supply and supplies the high current load directly.

Method and apparatus for monitoring a photo-detector

Abstract: In an embodiment of the invention the circuit for monitoring an optical signal detector comprises a current divider current mirror and a current multiplier current mirror. The current divider current mirror has a mirror leg and a primary leg. The primary leg is coupled to the optical signal detector. The current divider current mirror is configured to generate mirror leg current corresponding with a fraction of the primary leg current. The current multiplier current mirror has a mirror leg and a primary leg coupled to the mirror leg of the current divider current mirror. The current multiplier current mirror is configured to generate mirror leg current corresponding with a multiple of the primary leg current. In another embodiment the circuit comprises a first and second current mirror. The first current mirror has a primary current leg and a mirror current leg with the primary current leg exhibiting a resistance corresponding with a fractional part of the resistance exhibited by the mirror current leg, and with the primary current leg of the first current mirror series coupled between the optical signal detector and one of an electrical source and an electrical sink. The second current mirror has a primary current leg and a mirror current leg with the mirror current leg of the second current mirror exhibiting a resistance corresponding with a fractional part of the resistance exhibited by the primary current leg of the second current mirror, and with the primary current leg of the second current mirror series coupled with the mirror current leg of the first current mirror.

Wide-band CMOS VCO and frequency divider design for quadrature signal generation

Abstract: We present the design, implementation, and measurement of a fully integrated wide-band (3.3GHz-4GHz) CMOS VCOs and frequency divider, as well as the analysis and comparison of VCO topologies for their uniform phase noise performance in the wide tuning range. In addition, the dynamic range of the frequency divider is analyzed based on experimental results for the first time. The different VCO topologies have been investigated by using the measured results. It is demonstrated that the NMOS-PMOS VCO (NP-core VCO) without a current source has as low as 2dB of phase noise variation in the entire tuning range of 650MHz as well as achieving superior phase noise performance of -118.5 dBc/Hz at 1MHz offset compared to the NMOS VCO (N-core VCO) which shows severe phase noise degradation of 17dB due to AM-FM conversion in the high varactor gain region. A frequency divider is designed to generate the quadrature signal for direct conversion. The measured results exhibit the dynamic range limit of the frequency divider along with sensitivity curve of the divider. To the best of our knowledge, this is the first report analyzing the dynamic range of the frequency divider based on the experimental results.

System and method for synthesizing a clock at digital wrapper (FEC) and base frequencies using one precision resonator

Abstract: A precision PLL based transceiver having a single precision SAW or crystal resonator is configured to lock onto multiple different input frequencies and output generated clocks at the multiple different frequencies. The input reference frequency may be higher or lower than the resonator frequency. A fraction of two whole numbers describing a ratio of the resonator frequency to a given input frequency reference is first obtained. One of the numerator or denominator in the fraction is used to set the divide value of a first frequency divider coupling a VFO based on the resonator to a feedback input on a PFD. The other of the numerator or denominator is used to set a second frequency divider coupling the input frequency reference signal to the PFD. A first frequency multiplier is given a multiplication factor matching the divide value of the second frequency divider, and used to couple the output of the first frequency divider to the output of the PLL. Alternatively, a second frequency divider may be inserted between the reference frequency input and the PFD to match the frequency, or a multiple thereof, of the VFO output, which may bypass the first frequency divider in the feedback path to the PFD.

Programmable frequency divider with symmetrical output

Abstract: A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to provide flexibility. The frequency divider can dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, providing even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic network decomposed into multiple stages to realize a maximum latch-to-latch operational latency of one gate delay regardless of the size of the LFSR.

Method and circuit for adjusting a reference voltage signal

Abstract: A voltage trim circuit, in accordance with one embodiment of the invention, includes an operational amplifier, a transistor, a voltage divider and a bias current circuit. The operational amplifier is coupled to an input. The transistor is coupled to the operational amplifier and a first potential. The voltage divider circuit is coupled to the operational amplifier, the transistor and an output. The bias current circuit is coupled to the voltage divider circuit and a second potential. The voltage divider generates an output voltage as a function of a selectable divider ratio and provides a substantially constant feedback path to the operational amplifier. The bias current circuit provides for selectively adjusting a load resistance of the transistor to maintain a substantially constant load current through the transistor.

A phased array antenna with extended resonance power divider/phase shifter circuit

Abstract: A phased array for generating a directed radiation pattern includes a plurality of power divider ports (port nN), a first tunable element connected in series between each pair of adjacent power divider ports, an antenna connected to each of the power divider ports, and a second tunable element connected in parallel with each antenna. The phased array can include equal phase differences between successive power divider ports, equal amplitude of the signal at each antenna, an equal amount of successive phase change in a signal at each antenna, a source connectible to at least one power divider port including an alternating power supply through a quarter-wave transformer, the first tunable element being either an inductor or a capacitor, the second tunable element being either an inductor or a capacitor, and/or each antenna separated by a successive antenna by a half wavelength.

Digitally controlled CMOS balanced output transconductor based on novel current-division network and its applications

Abstract: In this paper, a novel digitally controlled CMOS balanced output transconductor (DCBOTA) is proposed. The digital control of the transconductance of this DCBOTA is achieved using novel current division network (CDN). The proposed DCBOTA operates under low supply voltage of /spl plusmn/1.5 V. Application of the DCBOTA is realizing variable gain amplifier VGA and second order active filter. PSPICE simulation confirms the performance of the proposed blocks and its applications.

Dynamic current limit adjustments

Abstract: A system, method, and apparatus are arranged to provide for current limit adjustments in a switching regulator that includes an inductor. A switched voltage divider circuit is selectively activated according to the actuation of various switching circuits in the regulator. The output of the switched voltage divider circuit is compared to a reference signal from a reference circuit to determine when a current limit is reached. At least one of the voltage divider ratio and the reference signal is adjustable in response to measurements related to the inductor saturation such that the current limit is changed to match inductor characteristics.

Code-controlled voltage divider

Abstract: A code-controlled voltage divider (20) is disclosed. The voltage divider (20) includes an upper portion with a resistor (22) and a dummy switching transistors (23), which is biased to be in an on-state. A lower portion of the voltage divider (20) includes multiple parallel legs, each including a resistor (24) and a corresponding switching transistor (26) that has its gate receiving one bit of a digital control word. A decoder (30) may be provided within the voltage divider (20) to generate the digital control word from an incoming code word, for example from a central processing unit (10). The lower portion resistors (24) of the voltage divider (20) are binary-weighted, and the sizes of the corresponding switching transistors (26) are binary-weighted so that the portion of the series resistance of each parallel leg that is due to the on-resistance of the switching transistor (26) is substantially constant over all of the parallel legs. The upper resistor (22) has a resistance that is related to one of the resistors (24) in the lower portion, and the size of the dummy switching transistor (23) is similarly related to the switching transistor (26) to that resistor's switching resistor (24).

Circuit arrangement for voltage regulation

Abstract: Circuit arrangement for voltage regulation having a voltage divider and a regulating circuit. The voltage divider is arranged between a first potential and a reference-ground potential and has a plurality of diodes connected in series, wherein an output voltage is tapped off at a terminal of one of the diodes. The regulating circuit, to which the output voltage and a reference voltage are applied, regulates the first potential based on a comparison of the output voltage with the reference voltage. The divider ratio of the voltage divider is altered by activating or deactivating one or more of the diodes, and is additionally altered by setting a magnitude of a voltage drop across at least one of the diodes.

Apparatus and method for calibrating a bandgap reference voltage

Abstract: An apparatus and method for producing an output reference voltage is provided. A voltage divider is configured to provide the output reference voltage from a bandgap reference voltage. The bandgap reference voltage is applied across a biased portion of the voltage divider. Additionally, a second-order temperature coefficient (TC) of the impedance of a controllable portion of the voltage divider is adjusted in response to a second-order trim signal. The first and zeroth order TCs of the controllable portion of the voltage divider are substantially independent of the second-order trim signal. In one embodiment, the controllable portion includes a resistor digital-to-analog converter (DAC) that is responsive to the second-order trim signal. The resistor DAC includes at least two different types of resistors. The second-order TCs of the two different types of resistors are substantially different.

Method and apparatus for a low jitter dual-loop fractional -n synthesizer

Abstract: A first phase-locked loop (PLL) circuit (301) includes an input for receiving a timing reference signal from an oscillator 303, a controllable oscillator circuit (805) supplying an oscillator output signal, and a multi-modulus feedback divider circuit (809). A second control loop circuit is selectably coupled through a select circuit 853 to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit (335). While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage (317), the stored control value corresponding to a desired frequency of the oscillator output signal.

Current difference divider circuit

Abstract: A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.

Oscillation circuit and radio communication device using the same

Abstract: A power divider (5) and an SAW resonator (6) are provided in a feedback path (3) of an amplifier (2). The SAW resonator (6) is connected to the input side of the amplifier (2) and the power divider (5) is connected to the output side of the amplifier (2) so as to reduce the input power input to the SAW resonator (6) and to secure an output power output from an output terminal (4) of the power divider.

Direct current detection circuit

Abstract: A direct current detection circuit has a zero-phase current transformer with source lines inserted therethrough for detecting current differences among them and generates a comparison voltage value based on a divided voltage value obtained between the zero-phase current transformer and a voltage divider resistor according to a change in the self-impedance of the zero-phase current transformer. An offset current is passed through the zero-phase current transformer to make it possible to detect on the basis of the comparison voltage value a direct current value in a range which is otherwise difficult to detect accurately on the basis of the comparison voltage value because of influence of hysteresis characteristic of the zero-phase current transformer. A control circuit detects a present direct current value based on the comparison voltage value and the value of the offset current.

Current output stages

Abstract: Current output stages are provided In accordance with an embodiment, a current output stage includes a voltage follower circuit, a first current mirror and a second current mirror A node of the voltage follower circuit provides a voltage that follows a voltage at the output of the current output stage An input of the first current mirror is connected (eg, by a current path of a transistor) to the node of the voltage follower circuit that follows the voltage at the output of the current output stage An output of the first current mirror is connected to an input of the second current mirror An output of the second current mirror is connected to the input of the current output stage

Low power stabilized voltage divider network

Abstract: A voltage divider network in combination with a voltage multiplier circuit voltage biases the electrodes of a photomultiplier tubes or related device. The circuit exploits the several voltage levels produced at successive stages of a voltage multiplier circuit in order to optimize the voltage divider network with respect to power consumption, current draw from the power supply, operating stability, and linear operation of the photomultiplier tube.

Light-receiving circuit capable of compensating a temperature dependence of an optical sensitivity of a photodiode

Abstract: The present light-receiving circuit provides a function capable of adjusting the temperature dependence and the output of the bias supply circuit independently. The light-receiving circuit includes a bias supply circuit, a voltage divider and a temperature compensation circuit that adjusts a division ratio of the voltage divider so as to depend linearly on the temperature. The temperature compensation circuit has a differential amplifier operating in the inverting mode, and a temperature-sensing resistor that connects the inverting input to the output of the differential amplifier. Since the temperature-sensing resistor has a linear dependence on the temperature and is connected as a feedback resistor, the output of the differential amplifier also depend linearly on the temperature.

1 V 10 GHz CMOS frequency divider with low power consumption

Abstract: A low supply voltage and low power ultra-high frequency divider is investigated. The proposed inverter of the frequency divider is able to operate at higher frequencies with enhanced output voltage swing and lower power consumption under an ultra-low supply voltage compared to that of existing divide-by-2 units. The frequency divider implemented with this inverter using the Chartered 0.18 /spl mu/m CMOS process is capable of operating up to 10 GHz for a 1 V supply voltage with 1.3 mW power consumption.