Showing papers on "Design for testing published in 2021"

A review paper on memory fault models and test algorithms

Abstract: Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory

Abstract: CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption, can be used in a large-scale memory system. In this article, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers the faults caused by the open and bridge defects and parametric variations during its fabrication. Analysis results show that the test time of the proposed test algorithm is reduced significantly compared with the enhanced methods of March-MOM and March C* for CMOL architectures. The write time is reduced approximately $5n/4\times$ 5 n / 4 × and $n\times$ n × , respectively, where $n$ n is the number of memristors attached to a nanowire segment. The read time is also reduced drastically. Finally, a design for testability (DFT) architecture is proposed to adapt the parallel March-like test algorithm. In compare with the short write time testing scheme, the proposed DFT can achieve 35.4 percent of reduction in area overhead, with 14.52 percent more power overhead kept the same delay in a CMOL circuit with 64 memory cells.

A Bypassable Scan Flip-flop for Low Power Testing with Data Retention Capability

Abstract: The power consumption of modern highly complex chips during scan test is significantly higher than the power consumed during functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures of the integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) is proposed for low-power IC test. The proposed flip-flop contains two secondary latches. The output of the “function” secondary latch goes to the following combinational circuits, while the other “shadow” secondary latch is used to shift test vectors during scan test. By gating the output of the function secondary latch, the redundant switching activity in the combinational circuits is eliminated during scan shift, thereby reducing the test power consumption significantly. The suppressed switching activity also leads to lower IR drop across the chip, increasing the chip manufacturing yield. Furthermore, the shadow latch is reused for data retention in the sleep mode while performing power gating, thereby alleviating the area cost of the shadow latch. The proposed BPS-DRFF also eases the hold time sign-off in the test mode due to the elongated clock-to-Q contamination delay that is brought in by the shadow latch. The proposed design is applied to an AES-128 crypto core in a UMC 55-nm low power CMOS technology. Experiment results show that 68.5% power is saved during scan test with the proposed BPS-DRFF, compared to the standard scan retention flip-flop.

Designing a 2048-Chiplet, 14336-Core Waferscale Processor

Abstract: Waferscale processor systems can provide the large number of cores, and memory bandwidth required by today’s highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based architecture where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost benefits. However, designing such a system has several challenges such as power delivery, clock distribution, waferscale-network design, design for testability and fault-tolerance. In this work, we discuss these challenges and the solutions we employed to design a 2048-chiplet, 14,336-core waferscale processor system.

A Novel Framework Design for Test Case Authoring and Auto Test Scripts Generation

Abstract: Every product has defects and identifying defects in the process of development and rectifying them before the launch of the product is very important. Embedded software testing process find the bugs in the software and report to the developer to fix issues. Sometimes to meet the product release deadlines, test engineers will not get much time to cover all test cases. That is why most software testing depends on test automation. In this paper, we focused on the area of automotive and home appliances embedded software test automation. Test automation is the only solution to improve the test phase and meet the timeline of the product launch. There are many test Automation tools like LabVIEW, test stand, and automation desk to automate testing embedded software. However, there is still manual efforts are required to use these tools. This paper deals automate those manual efforts. This Works shows how to generate test scripts from test cases to reduce the manual efforts, time, and cost.

An Efficient Design for Testability Approach of Reversible Logic Circuits

Abstract: Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and...

Secured Test Pattern Generators for BIST

Abstract: With the development in IC technology, testing the designs is becoming more and more complex. In the design, process testing consumes 60-80% of the time. The basic testing principle is providing the circuit under test (CUT) with input patterns, observing output responses, and comparing against the desired response called the golden response. As the density of the device are rising leads to difficulty in examining the sub-circuit of the chip. So, testing of design is becoming a time-consuming and costly process. Attaching additional logic to the circuit resolves the issue by testing itself. BIST is a relatively a design for testability technique to facilitate thorough testing of ICs and it comprises the test pattern generator, circuit under test, and output response analyzer. Quick diagnosis and very high fault coverage can be ensured by BIST. As complexity in the circuit is increasing, testing urges TPGs (Test Pattern Generators) to generate the test patterns for the CUT to sensitize the faults. TPGs are vulnerable to malicious activities such as scan-based side-channel attacks. Secret data saved on the chip can be extracted by an attacker by scanning out the test outcomes. These threats lead to the emergence of securing TPGs. This work demonstrates providing a secured test pattern generator for BIST circuits by locking the logic of TPG with a password or key generated by the key generation circuit. Only when the key is provided test patterns are generated. This provides versatile protection to TPG from malicious attacks such as scan-based side-channel attacks, Intellectual Property (IP) privacy, and IC overproduction.

Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits

Abstract: An intense trade-off arises between testing, hardware and speed of electronic circuits. An efficient design for testability methodology for the detection of stuck-at faults in reversible circuits is presented in this paper by exploiting the properties of Toffoli and Fredkin gates. An ( $$n+1$$ ) dimensional general test set depicted in the paper is found complete for the detection of single and multiple stuck-at faults in the modified circuit. A set of benchmark circuits are taken for experimentation where the proposed work achieved a reduction up to $$25.0\%$$ in gate cost and $$35.8\%$$ in quantum cost when compared to the existing work of the area that proves its efficacy towards the reduction in hardware cost with limited degradation in speed.

A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key

Abstract: Scan-based Design for Testability (DFT) is widely used in industry as it consistently provides high fault coverage. However, scan-based DFT is prone to security vulnerabilities where attackers use the scan design to obtain secret information from the system-on-chip. Existing countermeasures for such attacks contribute to enhancing the security of the scan design but cannot prevent the loss of debuggability because scan dumps are also treated as a type of attack even though they provide debuggers with high observability after a chip has been packaged. Therefore, it is necessary for secure scan architectures to effectively defend various existing attacks without losing the debuggability of the scan dump. In this paper, we propose a secure scan architecture using a skew-based lock and key to enhance the security of the scan design while maintaining the debuggability of the scan dump. The proposed architecture builds up an invisible barrier against the attacker by combining the physical information into a lock and key scheme. While the security is improved effectively with the new barrier by only a few key flip-flops, the scan dump, which has been treated as an attack, is protected separately in the acquisition and analysis steps using secure software in the proposed architecture. Performance evaluations show that the area and the test time overhead in the proposed architecture are negligible while achieving both a high level of security and scan dump protection.

A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices

Abstract: Secure devices embed analog sensors in order to measure some physical/environmental parameters which can alter its behavior such as temperature, voltage and electromagnetic field. To ensure the device security all along its lifetime, it is necessary to rely on those analog sensors. Consequently, test solutions must be designed and proceed at each step of the system life cycle, considering inherent constraints of each cycle, i.e., absent or defective software in the chip or chip in user’s hand for example. In this paper, we present a plug and play digital ABIST controller which allows to run external or internal autonomous built-in self-test phases on a temperature sensor used as case study. The external test mode is fully compliant with the IEEE Std. 1149.1 while the internal test one is controlled by the embedded CPU through a system bus.

Defenses Against Satisfiability Based Attacks

Abstract: Satisfiability based attacks discussed in the previous chapter formulate the attack as a satisfiability problem and use SAT solvers to find a netlist to layout mapping or to recover the missing BEOL nets. In this chapter, we discuss several defense methods to thwart the SAT attacks. In general, these methods attempt to increase the computational cost of the SAT attack to the point where it is no longer feasible. Several of these defense methods can defend the IC design against both SAT attacks and design constraint attacks. Some of these methods effectively combine other defense techniques such as logic locking and layout camouflaging with SM to improve the overall security against multiple attack models. We discuss the following defense methods: greedy wire lifting based on satisfiability, simultaneous wire lifting and cell insertion, combined layout camouflaging and SM for 2D and 3D designs, combined logic locking and SM, and combined SM and DFT (Design for Testability).

Design for test and qualification through activity-based modelling in product architecture design

Abstract: Test and qualification (T&Q) phases take a significant portion of the time to market for critical products in the space industry, especially when introducing new technologies. Since T&Q are treated as standard procedures, they tend to be independent of the architectural design phases and kept away from design decisions. However, when introducing new technologies, qualification procedures may differ from those established in regular design scenarios, and the estimation of qualification costs and duration is problematic. There is a lack of design for qualification methods capable of modelling these activities in early phases and use those models to support the architecture design of products with affordable test and qualification phases. In this article, a computer-assisted, model-based design method to model T&Q activities concerning early product architecture designs is proposed. Product architecture alternatives, test schedules and cost are connected through the quantification of T&Q drivers and driver rates. The design method is demonstrated using a case study about electric propulsion for satellites. The method is applicable for design situations where the choice of technology has a strong dependence on the qualification procedure.

Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits*

Abstract: Monolithic 3D (M3D) integration has the potential to achieve significantly higher device density compared to TSV-based 3D stacking. Sequential integration of transistor layers enables high-density vertical interconnects, known as inter-layer vias (ILVs), However, high integration density and aggressive scaling of the inter-layer dielectric make M3D integrated circuits especially prone to process variations and manufacturing defects. We explore the impact of these fabrication imperfections on chip-performance and present the associated test challenges. We introduce two M3D-specific design-for-test solutions - a low-cost built-in self-test architecture for the defect-prone ILVs and a tier-level fault localization method for yield learning. We describe the impact of defects on the efficiency of delay fault testing and highlight solutions for test generation under constraints imposed by the 3D power distribution network.

Designof Efficient Scan Flip-Flop

Abstract: Design For Testability (DFT) is a technique used while designing the Integrated Circuit (IC) to add features to the hardware design which helps in testing the design. Scan insertion is one of the DFT techniques which is used in sequential circuits. It is most popularly used as the testability of the circuit will be much better and the design can be easily tested. Scan insertion involves the insertion of scan flip-flop consisting of a D flip-flop with an extra multiplexer and additional scan input and scan output pins. The addition of extra circuitry increases the area, delay and power consumption which is undesirable. Hence, there is increase in the amount of silicon used and in the test time, which leads to lower profits. In this paper, two novel and efficient Scan flip-flop designs have been implemented consuming less power, area and delay. The two unique Scan flip-flop designs namely Gate Diffusion Input based D flip-flop and modified Transmission Gate based Scan flip-flop have been developed in Cadence Virtuoso. An improvement of 42.12% and 27.38% was observed in speed during functional and test modes respectively. A decrease of 47% and 56.73% was observed in peak-power consumption in functional and test modes respectively.

A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs

Abstract: Through Silicon Vias (TSVs) are crucial elements for the reliable operation and yield of three dimensional integrated circuits (3D ICs). Defects are a serious concern in TSV structures. A post-bond, parallel testing and diagnosis scheme is proposed in this work, for the detection and location of resistive open or short to substrate defects in TSVs, which is based on easily synthesizable all digital testing circuitry. The new testing method provides tolerance over process and temperature variations that may influence the embedded circuits. Extensive typical model simulations and Monte-Carlo analysis results, using the 65 nm technology of TSMC, prove the effectiveness of the new method. Additionally, two representative methods from the literature are simulated and compared to the proposed one, in terms of effectiveness, robustness, tolerance, cost and design for testability effort. The proposed scheme is proven to perform better based on all presented criteria.

Method to improve testability using 2-dimensional exclusive or (XOR) grids

Abstract: Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (“TAT”), test data volume, tester memory and cost associated with design for test (“DFT”), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

A Comprehensive Comparison Between Design for Testability Techniques for Total Dose Testing of Flash-Based FPGAs

Abstract: A comprehensive comparison between different design for testability (DFT) techniques for total-ionizing-dose (TID) testing of flash-based field-programmable gate arrays (FPGAs) is made to help designers choose the best suitable DFT technique depending on their application. The comparison includes muxed D scan, clocked scan, and enhanced scan DFT techniques. The comparison is done using ISCAS’89 benchmarks circuits. Points of comparisons include FPGA resources utilization, difficulty in design bring-up, added delay by DFT logic, and robust testable paths in each technique. We verified the results of each technique experimentally using Microsemi ProASIC3 FPGA’s and Cobalt 60 facility. The experimental results show a close total-dose failure level for all techniques when using worst-case test vectors (WCTVs) in total-dose testing of FPGA devices.