Showing papers on "Drain-induced barrier lowering published in 1970"

A New Instability in MOS Transistor Caused by Hot Electron and Hole Injection from Drain Avalanche Plasma into Gate Oxide

Abstract: Results of an experimental study are reported of a new instability found in p- and n-channel MOS transistors. This phenomenon is that when a higher voltage in an excess of a brakdown voltage is applied to the drain electrode the breakdown voltage drifts to a higher value and the drain current also increases. The origin of this instability is investigated by extensive measurements and analyses of the electrical characteristics of the transistors. It is concluded that 1) the semiconductor surface near the drain becomes p-like in the p-channel transistors and n-like in the n-channel transistors and thus the active channel length is shortened, 2) this is caused by charging of the gate oxide due to injection of electrons or holes generated during the drain avalanche breakdown, and 3) electron and hole injection is much affected by electric field across the oxide over the drain junction.

Floating gate transistor and method for charging and discharging same

Abstract: A floating gate transistor comprising a floating silicon or metal gate in a field effect transistor which is particularly useful in a read-only memory is disclosed. The gate which is surrounded by an insulative material such as SiO2 is charged by transferring charged particles (i.e., electrons) across the insulation from the substrate during an avalanche (breakdown) condition in the source or drain junctions of the transistor.

Fabrication of insulated gate field-effect transistors involving ion implantation

Abstract: An insulated gate field-effect transistor is made which utilizes both Schottky barrier connections and ion-implanted zones. The resultant structure incorporates source and drain zones, which are formed by ion implantation and whose spacing is fixed by the gate electrode, and source and drain electrodes which make ohmic connection to the implanted source and drain zones and rectifying connections to unimplanted material.

An analysis of current saturation mechanism of junction field-effect transistors

Abstract: A two-dimensional numerical analysis has been amde for junction field-effect transistors with small and large values of length-to-width ratio. Comparison of the results for different drain bias voltages shows the cause of the saturation of the drain current and the finite differential drain conductance in the saturation region. The effects of the geometry of the device and the field dependent mobility to the drain characteristics are clarified. Detailed pictures of the free carrier density distribution are presented, and the minimum channel width and the channel length are given for various bias conditions. A conduction path from the source to the drain with appreciable free carrier density has been found for bias conditions normally considered as pinched-off conditions. The drain characteristic with gate bias voltage is seen to be equivalent to that of a device with correspondingly smaller width and zero gate bias.

Self-aligned gate field effect transistor with schottky barrier drain and source

Abstract: A LOW PARASITIC CAPACITANCE FIELD EFFECT TRANSISTOR IS FABRICATED BY THE UTILIZATION OF A SELF-ALIGNING GATE TECHNIQUE. A METAL GATE IS FORMED AND THEN, EMPLOYING THE GATE AS A MASK, LOW TEMPERATURE SCHOTTKY BARRIER SOURCE AND DRAIN JUNCTIONS ARE FORMED. THE TECHNIQUE IS PARTICULARLY USEFUL IN THE FABRICATION OF THE FIELD EFFECT TRNASISTOR AS AN ELEMENT OF A LARGE INTEGRATED CIRCUIT WHERE MANY SUCH ALIGNMENTS MUST BE MADE SIMULTANTEOUSLY. D R A W I N G

Field-effect transistor with reduced drain-to-substrate capacitance

Abstract: A field-effect transistor having reduced drain-to-substrate capacitance is described as comprising a semiconductor substrate having a region of substantially lower resistivity than the substrate in the vicinity of the drain electrode. The region of low resistivity is of comparable depth to the drain region and produces devices having low drain-to-substrate capacitance and a higher drain-to-source ''''punch-through'''' voltage breakdown.

Potential, field and carrier distribution in the channel of junction field-effect transistors

Abstract: The operation mechanism of field-effect transistors (FET) was investigated by the measurements of the potential distribution in the channel using a tungsten needle as a probe in alloyed junction type FET in operation. The field distribution and the free carrier distribution were obtained as the first and the second derivative of the measured potential distribution. It is clear that, before the current saturation, from the source to the drain the electrically neutral channel exists. In this region the ionized impurity density and the carrier density are equal and the field toward the gate can be neglected. Contrary to this, in the channel at the drain side after the current saturation, the space charge layer extending from the gates reaches near the channel centre and the field to the gate direction becomes extremely high. In this region, an effective channel is formed in which the free carriers decrease toward the gate. At the centre of the effective channel, the electrical neutrality almost holds. Almost all of the voltage after the current saturation are spent in this region which is independent of the source side. In this short high field region, the field seems to be even in the velocity saturation region ( E >1·5×10 4 V/cm) of the carriers. The highest field region is rather outside of the gates. The potential and the carrier distribution in the channel at the drain side show a fairly good agreement with the theoretical calculation analysed in this paper.

Planar junction-gate field-effect transistors

Abstract: A junction-gate field-effect transistor is provided with its channel extending from the source to the drain in a direction normal to the plane of the substrate. The length of the channel is thereby substantially shorter than where the channel extends parallel to the plane of the substrate. The shorter channel provides faster switching speed and increased transconductance of the transistor.

Thin film power fet

Abstract: This disclosure is concerned with a thin film, power field effect transistor having a power dissipation capability of 80 watts/cm2 The transistor has a thin film interdigitated source and drain used in conjunction with a thick film source and drain leads The thick film source and drain leads essentially eliminates negative feedback resulting from a voltage drop in the source and drain

Insulated gate type field effect semiconductor device having narrow channel and method of fabricating same

Abstract: A method for fabricating an integrated gate field effect transistor is disclosed wherein an induced conduction region is formed between the source and drain regions by the application of a suitable potential between the gate electrode and substrate. The surface of the device is irradiated by a high-energy beam, thereby to form a narrow channel in the conduction region which defines the gate channel of the field effect transistor.

Insulated gate field-effect transistor with variable gain

Abstract: An insulated gate field-effect transistor comprising a source and drain which define the ends of a plurality of current carrying paths of controllable conductivity, and a gate separated from the current paths by an insulator. The width of the gate is less than the length of some of the current paths below it and is spaced from the drain in a direction parallel to the current paths with a spacing that varies along the length of the drain; and, therefore, different drain voltages are required to achieve conduction along different ones of the current-carrying paths for any given gate voltage. This permits varying the drain voltage to achieve a variable gain.

Non-volatile memory element and array

Abstract: A metal insulated semiconductor (MIS) field effect transistor is operated in a gate-to-source mode. The voltage threshold of conduction of the transistor is variable and is switched between two different stable threshold conditions in response to application of corresponding, different predetermined values of polarizing voltages applied between the gate and source terminals. Determination of the threshold condition to which the transistor is switched is effected by applying a read voltage to the gate of the transistor intermediate the voltage threshold levels and sensing the current flow between the source and drain. Since the sense voltage is less than the polarizing voltage for either condition of switching, the preset threshold condition is maintained. The transistor therefore exhibits a non-volatile memory capability. A plurality of the transistors are employed in a memory array and may be readily fabricated in integrated circuit form.

Integrated mnos memory organization

Abstract: A semiconductor memory array consists of an array of MNOS transistors. Each transistor possesses an hystereris relationship between the gate voltage required to turn on the transistor and a previously applied gate voltage. Thus each MNOS transistor stores, by itself, one bit of information. A binary "1" is written into a transistor by applying a voltage of a first selected magnitude to the gate of the MNOS transistor while grounding its source and drain. Applying simultaneously a negative voltage to the drain of the MNOS transistor lowers the voltage across the dielectric beneath the MNOS transistor's gate electrode and prevents the storage of a binary "1." No electrical isolation is required between the MNOS transistors.

Excess gate current in a junction-gate field-effect transistor

Abstract: Approximate potential distribution near the drain of the junction-gate field-effect transistor (JFET) is found and is used to deduce the excess reverse gate current, based on the assumption that such current is caused by an avalanche multiplication of carriers in the channel. Theory agrees well with measurement.

Changes of mobility along a depletion type MOS transistor channel

Abstract: The characteristics of a depletion type N-channel MOS transistor, with a built-in inversion layer, show considerable deviation from the behaviour expected of a device with a constant effective mobility along its channel. Experiment indicates reduction of the mobility in the direction of the drain due to the action of the drain induced field. A functional dependence of mobility on this field leading to a constant velocity is assumed and a set of equations describing this method is derived for various ranges of drain voltage. A special device, with voltage probes situated along its channel, was constructed and the drain characteristics, saturation point and potential distribution along the channel for the drain-field dependent mobility model and the constant mobility model were compared with experimental results obtained from it. The variable mobility model was shown to be in much better agreement with experiment.

Method of making a junction type field effect transistor

Abstract: A METHOD OF MAKING A DIFFUSED JUNCTION TYPE FIELD EFFECT TRANSISTOR, WHEREIN AN ANNULAR P TYPE GATE REGION HAVING A PROTRUDING PORTION CONNECTED TO A P TYPE SILICON SUBSTRATE ACROSS AN N TYPE SOURCE REGION IS PRELIMINARILY FORMED, AND AFTER MEASURING THE ELECTRICAL CHARACTERISTICS BETWEEN THE SOURCE AND A DRAIN REGION, THE PROTRUDING PORTION IS HEAVILY DOPED WITH AN N TYPE DETERMINING IMPURITY SO AS TO ISOLATE THE ANNULAR P TYPE GATE REGION AND THE SUBSTRATE. D R A W I N G

Differential drain resistance of field-effect transistors beyond pinch-off: A comparison between theory and experiment

Abstract: The theoretical computation of the drain characteristics of junction field-effect transistors reported by Kim and Yang has been compared with the experimental measurements in terms of the differential drain resistance. Good agreement between the theory and experiment has been found.

Ionization fire alarm

Abstract: An ionization fire alarm utilizing at least one transistor with high input resistance, such transistor being a field-effect transistor of the enhancement type having a threshold voltage above 7 volts. Further, the voltage value of the voltage source and the resistance value of a resistor element are selected such that the voltage drop at the ionization chamber without the influence of combustion aerosols is smaller than the threshold voltage of the field-effect transistor so that the field-effect transistor is therefore non-conductive or blocked, and additionally these values are simultaneously chosen such that the field strength, in the chamber regions of the ionization chamber in which at least 85 percent of the ionization current flows, is smaller than 5 V/cm.