Showing papers on "Drain-induced barrier lowering published in 1981"

Semiconductor devices controlled by depletion regions

Abstract: A field effect semiconductor device and method of controlling the device by merged depletion regions are provided. The device includes, in combination, first (22) and second (24) spaced apart PN junctions. Depletion regions (36, 38 and 40, 42) associated with the junctions have boundaries displaced from their respective junctions as a function of the doping concentration on either side of the junctions. The junctions are spaced apart by a distance with allows overlap of the depletion regions (38, 40) positioned therebetween. By applying a reverse bias to one (22) of the PN junctions the conductivity on the side (34) of the second PN junction (24) remote from the first PN junction (22) can be varied through the effect of merged depletion regions.

Self-refreshing memory cell

Abstract: A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

High performance submicron metal-oxide-semiconductor field effect transistor device structure

Abstract: A novel metal-oxide-semiconductor (MOS) field effect transistor having enhanced oxide thickness at the edge of the gate electrode and having metal silicide regions in the gate electrode and source and drain areas. The enhanced oxide thickness improves interconnect-to-interconnect breakdown voltage in multilevel interconnect devices as well as minimizing gate overlap of source and drain. The metal silicide regions reduce series resistance and improve device speed and packing density.

Self-aligned gate method for making MESFET semiconductor

Abstract: A MESFET is fabricated using a self-aligned gate process. This process uses a vertical (anisotropic) etch to self-align the gate and source/drain. The vertical etch, in conjunction with a two-level insulator, creates a barrier between the gate and source/drain, so that when metal is deposited and reacted, and any excess removed, the gate is self-aligned with the source/drain, and contacts to the source/drain and gate are well isolated. The alignment obtained by this process is advantageous in that series channel resistance is reduced, and a more compact structure is attained for improvement in packing density.

An analytical expression for the threshold voltage of a small geometry MOSFET

Abstract: A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.

Voltage current converter circuit

Abstract: A linear voltage-current converter circuit having a simplified circuit structure and operable over a wide voltage range is disclosed. The circuit comprises a first transistor having a drain connected to a power voltage through a first load element, a second and a third transistor having drains connected to the power voltage through a second load element, means for supplying gates of the first and second transistor with voltage signal, means responsive to a voltage difference at drains of the first and second transistors for controlling a gate voltage of the third transistor so as to reduce the voltage difference to zero, an output transistor, and means for supplying a gate of the output transistor with the same voltage as the gate voltage of the third transistor.

Mechanical valve analog

Abstract: A device suitable for use as an electrical analog of a unidirectional mechanical valve includes a three-terminal MOSFET. A sensing comparator has inputs coupled to the drain and source terminals of the FET, and an output coupled to the gate of the FET. A floating power supply allows the analog to operate independently of the circuit in which it is used. The FET will conduct current whenever the voltage from the drain to the source exceeds a threshold value, and will effectively act as an open circuit whenever the drain to source voltage is less than this threshold.

Threshold voltage characteristics of depletion-mode MOSFET's

Abstract: This paper presents the results of a study of the characteristics of the depletion-mode MOSFET. In particular, it is shown that the threshold voltage of this device is a function of its mode of operation (linear or saturated) due to a change in dominant conduction mechanisms caused by the finite depth of donor impurities in the channel. The effect of these impurities on the short channel behavior of the devices also is examined.

A numerical analysis of avalanche breakdown in short-channel MOSFETs

Abstract: Recently, the electrical characteristics for the short channel MOSFETs (Metal-Oxide-Semiconductor field effect transistor) have become important because of the increasing density of LSIs (Large Scale Integrated Circuits). One of the methods to understand the characteristics of the short channel MOSFETs is the two-dimensional analysis of the MOSFETs, and many studies about threshold voltage and other items have been made by using the two-dimensional method. In this paper, the drain breakdown characteristics for the short channel MOSFETs are calculated by the two-dimensional analysis method. Consequently, one of the phenomena for the short channel MOSFETs, that the breakdown voltage decreases with increase in gate voltage, is reduced to the difference of the electric field strength distribution from that of the long channel MOSFETs. This variation of the electric field distribution is caused by the strong influence of the electric field from the drain upon the considerable region in the substrate of the short channel MOSFETs.

Input protection circuit for an mis transistor

Abstract: The input protection circuit protects a MIS transistor Q 0 from high voltages. Resistors R 1 and R 2 are connected in series between an input terminal in and the gate of the transistor Q o . A first protection transistor is connected between a point N1, where R 1 and R 2 are joined, and a ground power supply line V ss . A second protection transistor is connected between a point N2, where the resistor R 2 and the gate of transistor 0 0 are connected, and the high power supply line V cc . The second protection transistor Q 2 has a break-down voltage lower than the breakdown voltage of the MIS transistor Q 0 but has a high impedance when it is turned ON when a high voltage is applied to the input terminal in. The first protection transistor Q 1 has a breakdown voltage higher than that of the transistor Q o but has a low impedance when turned ON when a high voltage is applied to the input terminal in. The combination of protection transistor Q, and Q 2 provides adequate protection for the transistor Q o even when it has only a minute and very thin gate insulating film.

Setting method for threshold voltage of mnos memory cell

Abstract: PURPOSE:To readily obtain an MNOS transistor having different threshold voltages by applying a voltage to the substrate and the gate of an MNOS memory cell, and then applying a voltage between the gate terminal of the cell and a source or drain terminal, thereby deciding the threshold value of the cell. CONSTITUTION:A high voltage is applied to the gate terminal 2 of an MNOS transistor to write, and an electrode is collected to a trap center. Then, a voltage VS or VD to be applied to a source or drain terminal 4 or 3 is varied while maintaining the voltage VG of the terminal 2 constant, the difference¦VG-VD¦ from the gate voltage VG is set to V1, V2, V3, V4, thereby rewriting. In this manner, threshold voltages Vth1-Vth4 of the transistor corresponding to V1- V4 of the voltage difference between the VG and the VD are obtained, thereby selecting the transistor having the prescribed threshold value. In other words, the width of a depletion layer is variably controlled to perform the writing or rewriting, and the transistor having different threshold value is formed.

Negative resistance device

Abstract: A negative resistance device utilizing a substrate bias effect is comprised of two MOS transistors of n-channel type and p-channel type. The two transistors are connected at the sources and the gates. The drain of the n-channel MOS transistor is connected to the substrate of the p-channel MOS transistor. The drain of the p-channel MOS transistor is connected to the substrate of the n-channel MOS transistor.

Input protection circuit for MIS transistor

Abstract: An input protection circuit which protects the gate of a MIS transistor from breakdown due to an excessively high voltage being applied thereto. The input protection circuit includes a first resistor and a second resistor connected in series between a input terminal and a gate of the MIS transistor, a first protection transistor provided between a first connecting point between the first and second resistors and one side of the power supply, and a second protection transistor provided between a second connecting point between the second resistor and the gate of the MIS transistor the other side of the power supply. The first protection transistor has a large mutual conductance gm, while the second protection transistor has a low breakdown voltage. With this input protection circuit, even when the gate breakdown voltage of the transistor to be protected is lower than the breakdown voltage of the first protection transistor, the gate electrode is kept at a voltage lower than the gate breakdown voltage by means of the second protection transistor having a lower breakdown voltage.

Threshold and subthreshold characteristics theory for a very small buried-channel mosfet using a majority-carrier distribution model

Abstract: Simple expressions of threshold and subthreshold characteristics for a very small buried-channel MOSFET is derived from a model of majority-carrier distribution along the channel. The carrier distribution is determined from the Poisson equation for a high-low junction. The basic formula for the subthreshold characteristic is derived from the majority-carrier drift-current equation. The theory is compared with the measured threshold voltages and the measured inverse semilogarithmic slopes of subthreshold current. The theoretical curves are in a reasonable agreement with experimental results. It is shown for a buried-channel MOSFET having a channel length less than 1 μm that the threshold and subthreshold characteristics change abruptly as the channel length is reduced because the majority-carrier concentration increases through the carrier diffusion from the source and drain terminals. The theoretical estimation shows that buried-channel MOSFETs will have the less short-channel effect than surface-channel MOSFETs for a small drain voltage. The theory also predicts that the buried-channel MOSFET can be scaled down in the same way as the surface-channel MOSFET.

Mos transistor circuit with breakdown protection

Abstract: A protected MOS transistor circuit includes an input (or output) MOS transistor (1) and a protective circuit (10) including a depletion mode MOS transistor (TrP) having a drain-source current path connected between ground and the gate of the MOS transistor and arranged to prevent breakdown of the gate oxide of the protected MOS transistor when power is off as a consequence of stray voltages. When power is on, the depletion mode MOS transistor's gate receives a control signal which renders the depletion mode MOS transistor non-conductive but, when power is off, the depletion mode transistor is conductive so as to ground currents caused by the stray voltages.

Logic circuit including at least one resistor or one transistor having a saturable resistor field effect transistor structure

Abstract: A logic circuit including an input stage, wherein a first field-effect transistor is in series with a first saturable resistor interposed on the drain side in the supply of the first transistor, and an output stage including a second transistor which is identical with the first and has a supply on the drain side which is common with the input stage supply. The gate of the second transistor is connected to the drain of the first transistor. The supply circuit of the second transistor is closed across a forward-biased diode, and a second saturable resistor on the ground of the common supply is connected to the source of the first transistor. At least a selected of the field effect transistors or the saturable resistors has a saturable resistor structure formed of a layer of semiconductor material on a semi-insulating substrate. The material is doped to set up a dipolar domain in respect of an electric field which is higher than a so-called critical value. The saturable resistor structure further includes a groove cut in the semiconductor layer between two ohmic contacts so as to define a residual channel in the material. The dimensions of the groove are such that the critical value of the electric field is overstepped in respect of a value of the order of one volt of the voltage between the ohmic contacts.

A charge sheet model for small geometry MOSFET's

Abstract: A charge sheet DC MOSFET model for small geometry devices is derived. It takes into account the drain induced barrier lowering and high field effects at the drain side. This model includes the diffusion component; the current expression is therefore valid in a continuous way for all regions of operation including the subthreshold regime. Two important saturation mechanisms are brought out by the analysis : at low current a diffusion mode and at high current a drift mode. I-V characteristics are predicted, within the limits of process parameter variations, using as inputs only physical and structural constants.

Normally-off field-effect transistor of the depletion type

Abstract: The field-effect transistor has a depletion zone (10) between the source and drain zones (2 and 3) which is of the same conduction type as the latter but more lightly doped. It also has a gate (6) consisting of polycrystalline semiconductor material which is of the same conduction type as the substrate and has a high level of doping. The object is that the turn-on voltage of such a transistor should be independent of the channel length. For this purpose, according to the invention, the source and drain zones (2 and 3) are underlaid by additional semiconductor zones (11 and 12) which are of the same conduction type as the former, have at least approximately the same doping level as the depletion zone (10) and form, together with the latter, a common, flat p-n junction (13) with the substrate. The field of application comprises VLSI circuits.

Planar doped barrier gate field effect transistor

Abstract: Disclosed is an epitaxial layer field effect transistor having a planar dd barrier gate formed on an n-type semiconductor planar channel region between drain and source terminals formed on the surface of the channel region. The semiconductor channel region is fabricated on a semiconductor substrate, preferably GaAs and being separated therefrom by one or more semiconductor planar buffer regions. The planar doped barrier gate comprises an n+ -π-p+ -π structure grown by molecular beam epitaxy over the n-type channel region. Application of an electrical potential to the gate modulates the channel charge depletion in the semiconductor channel region underlying the gate causing a variation in the channel conductance laterally between the source and drain terminals.

Process for making a dual implanted drain extension for bucket brigade device tetrode structure

Abstract: The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

N-Channel JFET device having a buried channel region, and method for making same

Abstract: A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface of the body outside the p-well. A buried channel connects the source and drain. A p-layer above the buried channel forms the top gate. Gate leakage current and noise are very low.

Subsurface junction field effect transistor

Abstract: A novel bipolar compatible junction field effect transistor structure is described in this paper. The device is fabricated using a single boron implant at energies high enough to result in a p-type channel fully embedded in an n-epitaxial background material. The channel is buffered from the Si-SiO 2 interface by a thin n-type region which improves device reproducibility. The structure has been used to make subvolt pinchoff devices especially suitable for micropower low voltage operation.

MOS transistor with bipolar operation in saturation

Abstract: 1. Circuit associating an insulated gate field-effect transistor (30) with a bipolar transistor (31), the drain being connected to the collector and the source to the emitter, a control terminal (G) being connected to the gate, characterized in that the base (B) of the bipolar transistor is connected on the one hand to the gate (G) of the field-effect transistor via a threshold device (32) and on the other hand to the connection between emitter and source (S) via a resistor (33) of high value, as a result of which the circuit functions like a field-effect transistor for low control voltages and like a bipolar transistor for control voltages higher than the threshold value of the threshold device.

Continuous model for gate-induced charge in short-channel MOSFETs

Abstract: The threshold voltage in a short-channel MOS transistor is a sensitive function of the effective channel length, substrate bias and the channel impurity profile. A continuous model is developed in this letter to obtain a simple analytical expression for the above described sensitivities suitable for CAD program implementation. The calculated values for the threshold voltage are compared with the measurements on MOSFETs with effective channel lengths between 9.7 μm and 1.2 μm.

Non-volatile EPROM and EEPROM of increased efficiency

Abstract: The floating gate in an N-channel EPROM cell extends over the drain diffusion region and over a part of the channel to form a "drain" capacitance between the drain and the floating gate and a "channel" capacitance between the channel and the floating gate. A control gate overlaps the floating gate and extends over the remainder of the channel close to the source diffusion region to form a "control" capacitance between the channel and the control gate. These three capacitances form the coupling for driving each cell. The inversion region in the channel directly underneath the control gate is reached directly by a "write or read access" voltage, which is applied to the control gate. The inversion region in the channel directly underneath the floating gate is reached directly through the drain and control capacitances and the channel capacitance by the control gate voltage and by another write access voltage, which is applied to the drain. The drain voltage is namely coupled to the section of the channel next to the drain through the series drive circuit which is formed by the drain capacitance and the channel capacitance. During writing, hot electrons from the write channel current are directed and injected into the floating gate through the transverse electric field between the floating gate and the channel lying thereunder. Stored injection charging on the floating gate increases the conductive state threshold of the programmed cell, the cell remaining non-conducting during reading, when customary or low access voltages are applied to the control gate. An unprogrammed cell conducts in a way dependent on the low read voltages which are applied to its control gate and to the drain drive circuit. The cell is erased either by ultraviolet illumination or by electrons from the floating gate which tunnel through a region of dilute oxide. The asymmetric arrangement of control gate and floating gate with respect to source and drain makes it possible for the arrangement to be very compact.

A model for the drain voltage and gate voltage dependence of the current fluctuation spectrum of unsaturated JFET's

Abstract: From the standpoint of the number fluctuation model of the generation-recombination noise and 1/ f noise, a model for the drain and gate voltage dependences of the current fluctuation spectrum of an unsaturated JFET ot MESFET can be established. The derived formula can explain the various experimental results, especially the square-law dependence of the drain voltage throughout almost all of the unsaturated region, and the increasing characteristic of the current fluctuation spectrum with increasing reverse gate voltage. It can also explain the dependence of drain current fluctuation on the device geometric parameters, and finally, it points out that Hooge's expression for the spectral intensity of the current fluctuation can be valid only in the linear region of the device.

Amplifier stage with IGFET additional equalisation - applies high biassing voltage to pn-junction between drain and/or source and substrate, not causing avalanche effect

Abstract: The operational point of an amplifier stage is subsequently stabilised by a process based on 2842631. The amplifier stage contains an IGFET with source, drain, channel region, an insulator and a controllable gate, and is intended for amplifying AC signals. For subsequent stabilisation of its operational point, the transistor contains a storage gate, load switchable by irradiation, between the channel region and the control gate, this storage gate being insulated on all sides. The pn-junction between the drain (D) and/or source (S) and the substrate has applied to it a high biasing voltage (Upn), however, insufficient to form an avalanche effect. To the biased drain and/or source is supplied a short-wave electromagnetic radiation (UV). This radiation can be alternately fed to an overlapping storage gate (G1) for the purpose of underdiffusion. The radiation may be of differential strength w.r.t. one of the drain and/or source regions.