Showing papers on "Emulation published in 2014"

Virtual Machines: Versatile Platforms for Systems and Processes

Abstract: Virtual Machine technology applies the concept of virtualization to an entire machine, circumventing real machine compatibility constraints and hardware resource constraints to enable a higher degree of software portability and flexibility. Virtual machines are rapidly becoming an essential element in computer system design. They provide system security, flexibility, cross-platform compatibility, reliability, and resource efficiency. Designed to solve problems in combining and using major computer system components, virtual machine technologies play a key role in many disciplines, including operating systems, programming languages, and computer architecture. For example, at the process level, virtualizing technologies support dynamic program translation and platform-independent network computing. At the system level, they support multiple operating system environments on the same hardware platform and in servers. Historically, individual virtual machine techniques have been developed within the specific disciplines that employ them (in some cases they aren’t even referred to as “virtual machines?), making it difficult to see their common underlying relationships in a cohesive way. In this text, Smith and Nair take a new approach by examining virtual machines as a unified discipline. Pulling together cross-cutting technologies allows virtual machine implementations to be studied and engineered in a well-structured manner. Topics include instruction set emulation, dynamic program translation and optimization, high level virtual machines (including Java and CLI), and system virtual machines for both single-user systems and servers. * Examines virtual machine technologies across the disciplines that use them—operating systems, programming languages and computer architecture—defining a new and unified discipline. * Reviewed by principle researchers at Microsoft, HP, and by other industry research groups. * Written by two authors who combine several decades of expertise in computer system research and development, both in academia and industry.

Using Mininet for emulation and prototyping Software-Defined Networks

Abstract: Software-Defined Networks (SDNs) represents an innovative approach in the area of computer networks, since they propose a new model to control forwarding and routing data packets that navigate the World Wide Web. Since research on this topic is still in progress, there are not many devices such as routers and switches that implement SDN functionalities; moreover, the existing ones are very expensive. Thus, in order to make researchers able to do experiments and to test novel features of this new paradigm in practice at a low financial cost, one solution is to use virtual network emulators. As a result, this paper focuses on study and evaluation of SDN emulation tool called Mininet. Initial tests suggested that the capacity of rapid and simplified prototyping, the ensuring applicability, the possibility of sharing results and tools at zero cost are positive factors that help scientists boost their researches despite the limitations of the tool in relation to the performance fidelity between the simulated and the real environment. After presenting some concepts of this paradigm, the purpose of its appearance, its elements and how it works, some net prototypes are created to better understand the Mininet tool and an evaluation is done to demonstrate its advantages and disadvantages.

MaxiNet: Distributed emulation of software-defined networks

Abstract: Network emulations are widely used for testing novel network protocols and routing algorithms in realistic scenarios. Up to now, there is no emulation tool that is able to emulate large software-defined data center networks that consist of several thousand nodes. Mininet is the most common tool to emulate Software-Defined Networks of several hundred nodes. We extend Mininet to span an emulated network over several physical machines, making it possible to emulate networks of several thousand nodes on just a handful of physical machines. This enables us to emulate, e.g., large data center networks. To test this approach, we additionally introduce a traffic generator for data center traffic. Since there are no data center traffic traces publicly available we use the results of two recent traffic studies to create synthetic traffic. We show the design and discuss some challenges we had in building our traffic generator. As a showcase for our work we emulated a data center consisting of 3200 hosts on a cluster of only 12 physical machines. We show the resulting workloads and the trade-offs involved.

Battery Emulation for Power-HIL Using Local Model Networks and Robust Impedance Control

Abstract: Battery emulation with a controllable high-power dc supply enables repeatable hardware-in-the-loop testing of powertrains for hybrid and electric vehicles. For this purpose, not only the power flow but also the nonlinear characteristic and dynamic impedance of batteries need to be emulated. In this paper, nonlinear local model networks are used to obtain dynamic battery models with high fidelity that can be computed in real time. This approach also allows the extraction of local linear impedance models for high-bandwidth impedance emulation, leading to a tighter coupling between the test bed and simulation model with predictable closed-loop dynamics. A model predictive controller that achieves optimal control with adherence to system constraints is extended to impedance control and robustness against constant power loads. This results not only in superior dynamic performance but also in stable dc-bus voltage control even for testing of tightly controlled electric motor inverters with negative differential input resistance. Since the controller design is based on a model of the test bed setup including the virtual battery model, emulator hardware, and input characteristics of the powertrain under test, it is possible to systematically analyze stability.

Defense Against Primary User Emulation Attacks in Cognitive Radio Networks Using Advanced Encryption Standard

Abstract: This paper considers primary user emulation attacks in cognitive radio networks operating in the white spaces of the digital TV (DTV) band. We propose a reliable AES-assisted DTV scheme, in which an AES-encrypted reference signal is generated at the TV transmitter and used as the sync bits of the DTV data frames. By allowing a shared secret between the transmitter and the receiver, the reference signal can be regenerated at the receiver and used to achieve accurate identification of the authorized primary users. In addition, when combined with the analysis on the autocorrelation of the received signal, the presence of the malicious user can be detected accurately whether or not the primary user is present. We analyze the effectiveness of the proposed approach through both theoretical analysis and simulation examples. It is shown that with the AES-assisted DTV scheme, the primary user, as well as malicious user, can be detected with high accuracy under primary user emulation attacks. It should be emphasized that the proposed scheme requires no changes in hardware or system structure except for a plug-in AES chip. Potentially, it can be applied directly to today's DTV system under primary user emulation attacks for more efficient spectrum sharing.

Efficient Coding for Interactive Communication

Abstract: We revisit the problem of reliable interactive communication over a noisy channel and obtain the first fully (randomized) efficient constant-rate emulation procedure for reliable interactive communication. Our protocol works for any discrete memoryless noisy channel with constant capacity and fails with exponentially small probability in the total length of the protocol. Following a work by Schulman (1993), our simulation uses a tree-code, yet as opposed to the nonefficient construction of absolute tree-code used by Schulman, we introduce a relaxation in the notion of goodness for a tree code and define a potent tree code. This relaxation allows us to construct an efficient emulation procedure for any two-party protocol. Our results also extend to the case of interactive multiparty communication. We show that a randomly generated tree code (with suitable constant alphabet size) is an efficiently decodable potent tree code with overwhelming probability. Furthermore, we are able to partially derandomize this result by means of epsilon-biased distributions using only O(N) random bits, where N is the depth of the tree.

Characterization and Compensation of Network-Level Anomalies in Mixed-Signal Neuromorphic Modeling Platforms

Abstract: Advancing the size and complexity of neural network models leads to an ever increasing demand for computational resources for their simulation. Neuromorphic devices offer a number of advantages over conventional computing architectures, such as high emulation speed or low power consumption, but this usually comes at the price of reduced configurability and precision. In this article, we investigate the consequences of several such factors that are common to neuromorphic devices, more specifically limited hardware resources, limited parameter configurability and parameter variations due to fixed-pattern noise and trial-to-trial variability. Our final aim is to provide an array of methods for coping with such inevitable distortion mechanisms. As a platform for testing our proposed strategies, we use an executable system specification (ESS) of the BrainScaleS neuromorphic system, which has been designed as a universal emulation back-end for neuroscientific modeling. We address the most essential limitations of this device in detail and study their effects on three prototypical benchmark network models within a well-defined, systematic workflow. For each network model, we start by defining quantifiable functionality measures by which we then assess the effects of typical hardware-specific distortion mechanisms, both in idealized software simulations and on the ESS. For those effects that cause unacceptable deviations from the original network dynamics, we suggest generic compensation mechanisms and demonstrate their effectiveness. Both the suggested workflow and the investigated compensation mechanisms are largely back-end independent and do not require additional hardware configurability beyond the one required to emulate the benchmark networks in the first place. We hereby provide a generic methodological environment for configurable neuromorphic devices that are targeted at emulating large-scale, functional neural networks.

A Real-Time Nonlinear Hysteretic Power Transformer Transient Model on FPGA

Abstract: A transformer is the most widely used equipment in power systems to transfer energy from one circuit to another. For real-time electromagnetic transient simulation, this paper presents a digital hardware emulation of the power transformer on a field programmable gate array. The linear model of the transformer is based on the admittance matrix approach. Detailed real-time modeling of the transient nonlinearities, including hysteresis phenomena, is carried out based on the Preisach theory. The nonlinear solution in real time is undertaken using a full Newton iteration. All the hardware modules for the transformer emulation were developed in VHDL. The model is fully parallelized and pipelined to achieve the lowest latency and the smallest hardware resource consumption. Real-time results on the oscilloscope are compared with off-line results from the ATP software.

Keyflow: a prototype for evolving SDN toward core network fabrics

Abstract: The large bulk of packets/flows in future core networks will require a highly efficient header processing in the switching elements. Simplifying lookup in core network switching elements is capital to transport data at high rates and with low latency. Flexible network hardware combined with agile network control is also an essential property for future software-defined networking. We argue that only further decoupling between the control and data planes will unlock the flexibility and agility in SDN for the design of new network solutions for core networks. This article proposes a new approach named KeyFlow to build a flexible network-fabricbased model. It replaces the table lookup in the forwarding engine by elementary operations relying on a residue number system. This provides us tools to design a stateless core network by still using OpenFlow centralized control. A proof of concept prototype is validated using the Mininet emulation environment and OpenFlow 1.0. The results indicate RTT reduction above 50 percent, especially for networks with densely populated flow tables. KeyFlow achieves above 30 percent reduction in keeping active flow state in the network.

Massively Parallel Approximate Gaussian Process Regression

Abstract: We explore how the big-three computing paradigms---symmetric multiprocessor, graphical processing units (GPUs), and cluster computing---can together be brought to bear on large-data Gaussian processes (GP) regression problems via a careful implementation of a newly developed local approximation scheme. Our methodological contribution focuses primarily on GPU computation, as this requires the most care and also provides the largest performance boost. However, in our empirical work we study the relative merits of all three paradigms to determine how best to combine them. The paper concludes with two case studies. One is a real data fluid-dynamics computer experiment which benefits from the local nature of our approximation; the second is a synthetic example designed to find the largest data set for which (accurate) GP emulation can be performed on a commensurate predictive set in under an hour.

Static and dynamic power system load emulation in converter-based reconfigurable power grid emulator

Abstract: A hardware test-bed platform emulating multiple-area power system scenario dynamics has been established aiming at multiple time-scale emulations. In order to mimic real power flow situation in the system, the load emulators have to behave like real ones in both its static and dynamic characteristics. A constant-impedance, constant-current, and constant-power (ZIP) model has been used for static load type, while a three-phase induction motor model has been built to represent dynamic load types. In this paper, ways of modeling ZIP and induction motor loads and the performance of each load emulator are discussed. A comparison between simulation and experimental results are shown as well for the validation of the emulator behavior.

Smart key emulation for vehicles

Abstract: Techniques are disclosed for permitting a person to keylessly start a vehicle using a machine-sensible item such as his/her mobile device without requiring the person to possess a smart key.

Development of converter based reconfigurable power grid emulator

Abstract: A Hardware Test-Bed (HTB) is developed to serve as a platform for power grid emulation. For maximum flexibility, power converters, which can accommodate various control algorithms and behave distinctively based on the applied model and control, is adopted. With the developed emulators, such as generator, load, wind turbine, and PV emulators, diverse research and experiments can be performed by using the HTB. This paper introduces the emulating method, hardware, control and communication structure of the HTB. At the same time, experimental results are compared with simulation to verify the emulation. I. INTRODUCTION Nowadays, with the help of fast computers, digital simulation has become an important method for research in various areas, including power systems. Unlike analog computation with physical components, digital simulation is done by solving differential and algebraic equations of the target network composed with mathematical models of each individual component. Therefore, the accuracy of the mathematical models and the robustness of the numerical method in use dictate the validity of the simulated results. Digital simulation sometimes will suffer from problems such as numerical oscillation due to discontinuities and interpolation without proper selection of time step or integration method (1). At the same time, even though mathematical models of diverse devices are well developed, many users of digital simulation tools tend to simplify or ignore critical conditions such as measurement error, time delay, non-linearity, electromagnetic interference, etc. This leads to scenarios with impractical and unrealistic simulation parameters. Currently, there is no comprehensive simulation software that takes every possible aspect in consideration. Furthermore, in spite of a sophisticated designing methodology, the inner defect of an equipment or a system cannot be detected or noticed without field testing.

Team-level programming of drone sensor networks

Abstract: Autonomous drones are a powerful new breed of mobile sensing platform that can greatly extend the capabilities of traditional sensing systems. Unfortunately, it is still non-trivial to coordinate multiple drones to perform a task collaboratively. We present a novel programming model called team-level programming that can express collaborative sensing tasks without exposing the complexity of managing multiple drones, such as concurrent programming, parallel execution, scaling, and failure recovering. We create the Voltron programming system to explore the concept of team-level programming in active sensing applications. Voltron offers programming constructs to create the illusion of a simple sequential execution model while still maximizing opportunities to dynamically re-task the drones as needed. We implement Voltron by targeting a popular aerial drone platform, and evaluate the resulting system using a combination of real deployments, user studies, and emulation. Our results indicate that Voltron enables simpler code and produces marginal overhead in terms of CPU, memory, and network utilization. In addition, it greatly facilitates implementing correct and complete collaborative drone applications, compared to existing drone programming systems.

A Gesture Learning Interface for Simulated Robot Path Shaping With a Human Teacher

Abstract: Recognition of human gestures is an active area of research integral for the development of intuitive human-machine interfaces for ubiquitous computing and assistive robotics. In particular, such systems are key to effective environmental designs that facilitate aging in place. Typically, gesture recognition takes the form of template matching in which the human participant is expected to emulate a choreographed motion as prescribed by the researchers. A corresponding robotic action is then a one-to-one mapping of the template classification to a library of distinct responses. In this paper, we explore a recognition scheme based on the growing neural gas (GNG) algorithm that places no initial constraints on the user to perform gestures in a specific way. Motion descriptors extracted from sequential skeletal depth data are clustered by GNG and mapped directly to a robotic response that is refined through reinforcement learning. A simple good/bad reward signal is provided by the user. This paper presents results that show that the topology-preserving quality of GNG allows generalization between gestured commands. Experimental results using an automated reward are presented that compare learning results involving single nodes versus results involving the influence of node neighborhoods. Although separability of input data influences the speed of learning convergence for a given neighborhood radius, it is shown that learning progresses toward emulation of an associative memory that maps input gesture to desired action.

TimeKeeper: a lightweight virtual time system for linux

Abstract: We present TimeKeeper: a simple lightweight approach to embedding Linux containers (LXC) in virtual time. Each container can be directed to progress in virtual time either more rapidly or more slowly than the physical wall clock time. As a result, interactions between an LXC and physical devices can be artificially scaled, e.g., to make a network appear to be ten times faster with respect to the software within the LXC than it actually is. Our approach also supports synchronized (in virtual time) emulation, by grouping LXCs together into an experiment where the virtual times of containers are kept synchronized, even when they advance at different speeds. This has direct application to the integration of emulation and simulation within a common framework.

Probe Selection in Multiprobe OTA Setups

Abstract: Standardization work for over-the-air (OTA) testing of multiple-input-multiple-output (MIMO) capable terminals is currently ongoing in COST IC1004, 3GPP, and CTIA, where a multiprobe anechoic chamber based method is a promising candidate. Setting up a multiprobe configuration with channel emulators is costly, so finding ways to limit the number of probes while still reproducing the target channels accurately could make the test system both cheaper and simpler to implement. Several probe selection algorithms are presented in this paper to address this issue. The proposed techniques provide a probe selection framework for the channel emulation techniques published in the literature. Simulation results show that good channel emulation accuracy can be achieved with the selected subset of probes for the considered target channel models. The probe selection algorithm is further supported by measurement results in a practical multiprobe setup.

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Abstract: Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.

Detecting Primary User Emulation Attacks in Cognitive Radio Networks via Physical Layer Network Coding.

Abstract: Primary user emulation (PUE) attacks on cognitive radio networks pose a serious threat to the deployment of this technique. Previous approaches usually depend on individual or combined received signal strength (RSS) measurements to detect emulators. In this paper, we propose a new mechanism based on physical layer network coding to detect the emulators. When two signal sequences interfere at the receiver, the starting point of collision is determined by the distances among the receiver and the senders. Using the signal interference results at multiple receivers and the positions of reference senders, we can determine the position of the ‘claimed’ primary user. We can then compare this localization result with the known position of the primary user to detect the PUE attack. We design a PUE detection mechanism for wireless networks with trustworthy reference senders. We analyze the overhead of the proposed approach and study its detection accuracy through simulation. c � 2013 Published by Elsevier Ltd. Selection and/or peer-review under responsibility of Z. Khan and N. Javaid.

Large-Scale, Full-Wave-Based Emulation of Step-Frequency Forward-Looking Radar Imaging in Rough Terrain Environments

Abstract: Large-scale, full-wave modeling of multistatic target imaging in a rough ground environment is described. The emulation methodology employs a parallelized three-dimensional “near-field” finite-difference time-domain algorithm in characterizing the electromagnetic scattering from the ground surface and buried and on-surface targets in the form of landmines and unexploded ordnances; subsequent focusing of the scattered fields into an image is obtained by exploiting the time-reversal technique applied over a spectral band consistent with one used by a step-frequency system under development. Imaging performance is investigated with numerical experiments for both single- and multi-aperture sensing geometries. The emphasis of this study is on examining the responses of discrete ground targets in the presence of distributed variable ground clutter as relevant to performance prediction for ultra-wideband forward-looking radar applications.

FPGA-based real-time simulation of nonlinear permanent magnet synchronous machines for power hardware-in-the-loop emulation systems

Abstract: This paper presents an FPGA-based real-time simulation system of a nonlinear permanent magnet synchronous machine and its qualification for power hardware-in-the-loop emulation systems. The machine model considers the magnetic anisotropy of the rotor, the saturation of the iron as well as dynamic cross-coupling effects between the direct- and quadrature axis of the machine. A specifically designed high performance signal processing system is developed to calculate the machine behavior with a frequency of 1.5 MHz. The developed model calculates the state variables of the machine as well as the counter voltage for an emulation converter in a way that the coupling network of the power hardware-in-the-loop emulation test bench could be equipped with any inductance. Measurements validate the proper function of the machine model and demonstrate the accurate solution of the nonlinear differential equation system of an anisotropie synchronous machine with nonlinear magnetics in real-time.

Airborne network evaluation: challenges and high fidelity emulation solution

Abstract: The future AN is envisioned as an IP-based hierarchical network with heterogeneous nodes and waveforms. Due to its highly dynamic nature and bandwidth constraints, new AN technologies are needed to provide reliable network operations with similar levels of mission support as in terrestrial networks. This article first identifies challenges in designing and evaluating AN technologies and then describes an ongoing effort to develop a realistic wireless testing and performance evaluation platform for ANs. A set of use cases are presented to illustrate how high fidelity emulation can be used to evaluate new architectures and protocols in AN environments.

Emulating full-converter wind turbine by a single converter in a multiple converter based emulation system

Abstract: A real-time reconfigurable hardware test-bed is being constructed to emulate a transmission network of a power system by modular regenerative converters. This test-bed enables flexible research scenarios without the necessities of using the actual power system equipment. This paper presents the emulation of a full-converter wind turbine using a single converter in order to investigate the impact of renewable energy penetration. By integrating physical models and control strategies into the converter controller, the emulator can imitate the behaviors of the wind turbine accurately. Simulation and experiments performed in the test-bed validate the effectiveness of the emulation, and demonstrate the performance of the emulated wind turbine during different power system scenarios.

A fault injection methodology and infrastructure for fast single event upsets emulation on Xilinx SRAM-based FPGAs

Abstract: Modern SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly employed in safety- and mission-critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. Assessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing design exploration of different protection alternatives. This paper presents a Dynamic Partial Reconfiguration-based fault injection methodology implemented by an integrated infrastructure for SEUs emulation in the configuration memory of Xilinx SRAM-based FPGAs. The proposed methodology exploits the Xilinx Essential Bits technology to extremely speed-up fault injection, ensuring correct operations of the fault injection infrastructure during the whole injection process.

A hybrid network IDS for protective digital relays in the power transmission grid

Abstract: In this paper, we propose a novel use of network intrusion detection systems (NIDSs) tailored to detect attacks against networks that support hybrid controllers that implement power grid protection schemes In our approach, we implement specification-based intrusion detection signatures based on the execution of the hybrid automata that specify the communication rules and physical limits that the system should obey To validate our idea, we developed an experimental framework consisting of a simulation of the physical system and an emulation of the master controller, which serves as the digital relay that implements the protection mechanism Our Hybrid Control NIDS (HC-NIDS) continuously monitors and analyzes the network traffic exchanged within the physical system It identifies traffic that deviates from the expected communication pattern or physical limitations, which could place the system in an unsafe mode of operation Our experimental analysis demonstrates that our approach is able to detect a diverse range of attack scenarios aimed at compromising the physical process by leveraging information about the physical part of the power system

Evaluation of a Multihop Airborne IP Backbone with Heterogeneous Radio Technologies

Abstract: In recent years, there has been increasing interest in the US Department of Defense to build an on-demand airborne network for communications relay utilizing high-capacity, long-range military radio systems. While these systems operate well in a network of homogeneous systems, platforms generally employ multiple heterogeneous radio systems making internetworking difficult due to varying radio characteristics and lack of interoperability. Although simulations and emulation tests can provide a baseline for how systems will perform in a controlled environment, field tests are crucial to demonstrate capabilities in real-world operating environments. In this paper, we present measurement results from a field test involving two airborne platforms forming a dynamically routed aerial IP backbone over 200 nautical miles with various radio systems as part of the C4ISR on-the-move 2010 exercise. We present measurement results on per link performance, radio-to-router interface performance, and multihop network performance results with prototype software on open source platforms. Additionally, key lessons learned and recommendations are given.

Primary-User Emulation Detection Using Database-Assisted Frequency-Domain Action Recognition

Abstract: In this paper, we propose an approach for detecting primary-user emulation (PUE) attacks in cognitive radio (CR) networks based on the application of action recognition techniques in the frequency domain. Specifically, we apply this method to analyze the fast Fourier transform (FFT) sequences of wireless transmissions operating across a CR network environment and then use a relational database and an artificial neural network to classify their actions in the frequency domain. Based on the previous approach proposed by the authors, this new approach is initiated via energy detection to locate the potential PU emulators within a specific frequency band. The approach employs a relational database system to record the motion-related feature vectors of PUs on this frequency band. When an intercepted transmission does not have a match record in the database, this transmission is considered from the PUE. Otherwise, a covariance descriptor will be calculated and fed into an artificial neural network for further classification. The proposed approach is validated via computer simulations and by experimental hardware implementations using a software-defined radio (SDR) platform. The computer simulations show that our new approach is more efficient than the authors' previous approach when there are multiple PUs in the network. The hardware experiment shows that the proposed approach can maintain system performance in terms of percentage of correct classification.

Stream monitoring across a distributed platform

Abstract: Some embodiments provide a system for simultaneously monitoring a content stream that is streamed using any of a plurality of streaming protocols from different points-of-presence (PoP) from within a distributed platform in real-time without the need for manual visual verification. The system is implemented with different emulation engines, each providing client-side player emulation for a different streaming protocol. The client-side player emulation involves requesting and downloading content stream chunks from a specified PoP according to the streaming protocol that is used by the distributed platform to stream the content stream under test. As part of the emulation, each instance inspects the downloaded chunks without decoding or rendering in order to track real-time performance and any errors in the server-side transmission of the content stream under test.