Showing papers on "Error detection and correction published in 1991"

Optimal Inference in Cointegrated Systems

Abstract: Properties of maximum likelihood estimates of cointegrated systems are studied. Alternative formulations are considered, including a new triangular system error correction mechanism. We demonstrate that full system maximum likelihood brings the problem of inference within the family covered by the locally asymptotically mixed normal asymptotic theory, provided all unit roots have been eliminated by specification and data transformation. Methodological issues provide a major focus of the paper. Our results favor use of full system estimation in error correction mechanisms or subsystem methods that are asymptotically equivalent. They also point to disadvantages in the use of unrestricted VAR's formulated in levels and of certain single equation approaches to estimation of error correction mechanisms. Copyright 1991 by The Econometric Society.

Robust adaptive control: a unified approach

Abstract: A complete tutorial review of the entire field is presented, beginning with simple instability examples to identify the causes of nonrobust behavior in adaptive control. Some of the mathematical groundwork is presented, and the theory for the design and analysis of adaptive laws is developed. Commonly used adaptive controller structures are discussed, highlighting their particular robustness properties. Particular attention is paid to model reference, pole placement, and linear quadratic controller structures. Designs and analyses of model reference, pole placement, and linear quadratic controllers, based on combining the corresponding controller structures with the various robust adaptive laws, are presented. Suggestions for future research are given. >

Error-correcting codes for list decoding

Abstract: In the list-of-L decoding of a block code the receiver of a noisy sequence lists L possible transmitted messages, and is in error only if the correct message is not on the list. Consideration is given to (n,e,L) codes, which correct all sets of e or fewer errors in a block of n bits under list-of-L decoding. New geometric relations between the number of errors corrected under list-of-1 decoding and the (larger) number corrected under list-of-L decoding of the same code lead to new lower bounds on the maximum rate of (n,e,L) codes. They show that a jammer who can change a fixed fraction p >

Video signal processing circuit

Abstract: PURPOSE:To enable the execution of most satisfactory error correction over a wide range as much as possible by using corrected sample data for the correction processing of error sample data and varying an upper limit value in the number of times for repeating the correction CONSTITUTION:To the sample data and an error flag supplied to an input terminal 1, the error correction is executed concerning a horizontal direction by a one-dimensional error correcting circuit 2 Next, the respective sample data of lines are supplied to a two-dimensional error correcting circuit 3 corresponding to the current line, upper line, lower line and current line before one frame from the circuit 2 and line delay circuit 4-6 Then, the error correction is executed by a control signal, etc, from a ranking control circuit 7 A threshold value in the number of times for repeating the correction to be set to the ranking control circuit 7 can be set from an external part and made variable Thus, since the number of times for repeating a repeated replacement processing using the sample data, to which the error correction is already executed, is controlled, the error correction can be executed corresponding to the kind of a picture, etc

On unordered codes

Abstract: By extending the results obtained by D. E. Knuth (1986), a parallel unordered coding scheme with 2/sup r/ information bits is described. Balanced codes in which each codeword contains equal amounts of zeros and ones, with r check bits and up to 2/sup r+1/-(r+2) information bits, are constructed. Unordered codes with r check bits and up to 2/sup r/+2/sup r-1/-1 information bits are designed. Codes capable of detecting 2/sup r-1/+(2/sup r//2)-1 unidirectional errors using r check bits are also described. A review of previous work is presented. >

Method and apparatus for transferring data between a data bus and a data storage device

Abstract: A bus interface between a data bus and data storage devices provides error protection for multi-byte data packets received from the bus and intended for storage on an associated storage device by checking the data symbols in a packet for errors using check sum and parity symbols included in the packet. The bus interface then (i) encodes a predetermined number of data symbols to generate error detection symbols, (ii) again checks the data symbols for errors using the parity bits, and (iii) stores the data and associated error detection symbols in one of a series of linked buffers. Each buffer holds enough the data and associated error detection symbols to fill one storage unit, or sector, on an associated storage medium. A storage interface later retrieves the buffered data and error detection symbols, combines them with the address of a designated storage sector, and encodes the symbols to generate error correction symbols. It then stores the encoded data, and error detection and correction symbols in the designated sector. When the storage interface later retrieves the symbols from the sector, it corrects errors in the data using the retrieved error correction symbols. It next removes the sector address from the error detection symbols and returns the data and error detection symbols to the bus interface. The bus interface (i) generates parity bits, (ii) checks for errors using the error detection symbols, (iii) generates check sum symbols and (iv) transmits the data, check sum and parity symbols over the bus. If the bus interface at any time detects an error, it stops the data transfer operation.

Dynamic ram with on-chip ecc and optimized bit and word redundancy

Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

Method and apparatus for concealing errors in a digital television

Abstract: A method and apparatus for concealing errors occurring during the transmission and or reception of digital television signals. Blocks of video information are received and if any of the blocks contain errors including missing coefficients and/or motion vectors which are not correctable by the error correction circuitry, they are concealed by deriving replacement coefficients and/or motion vectors from at least one of the other received blocks of video.

Adaptive rate error control through the use of diversity combining and majority-logic decoding in a hybrid-ARQ protocol

Abstract: Diversity combining and majority-logic decoding are combined to create a simple but powerful hybrid automatic repeat request (ARQ) error control scheme. Forward-error-correcting (FEC) majority-logic decoders are modified for use in type-I hybrid-ARQ protocols through the identification of reliability information within the decoding process. Diversity combining is then added to reduce the number of retransmissions and their consequent impact on throughput performance. Packet combining has the added benefit of adapting the effective code rate to channel conditions. Excellent reliability performance coupled with a simple high-speed implementation makes the majority-logic system and ideal choice for high-data-rate error control over both stationary and nonstationary channels. >

Throughput estimation of ARQ protocols for a Rayleigh fading channel using fade- and interfade-duration statistics

Abstract: Error detection combined with automatic repeat request retransmission is used to provide reliable digital data transmission over a communication channel. The throughput for a system using go-back-N or selective-repeat protocols with Rayleigh fading in both directions of transmission is approximated by using fade- and interfade-duration statistics of a multipath channel. Results indicate that for a slow-fading channel (e.g. fading rate=1.34 Hz), the throughput of go-back-N is only slightly inferior to that of selective-repeat, mainly due to the burstiness of the channel bit errors. >

A complete error model for free space polarimetric measurements

Abstract: The authors present a complete 12-term error model for the systematic errors in polarimetric radar and antenna free space measurements for test range and laboratory use. Errors are induced by the frequency response, the channel imbalance, the coupling between the transmit channels, the coupling between the receive channels, the coupling from transmit to receive and by the residual reflections of the environment. The errors are contained in three 2*2 matrices, the isolation matrix, the transmit matrix and the receive matrix. A full polarimetric calibration with the empty room, a sphere, a vertical dihedral corner and a 45 degrees dihedral corner is proposed. The physical understanding is supported by a cubic signal graph for the error terms. >

A hybrid ARQ scheme with adaptive forward error correction for satellite communications

Abstract: A hybrid automatic-repeat-request system combined with adaptive forward error correction (ARQ/AFEC) which adaptively alters the error-correcting capability according to channel state using a nonsystematic Reed-Solomon code is presented. lt is shown that the system can alter the error-correcting capability by varying the number of information symbols fed to the decoder only, and not change the hardware of the encoder. Performance evaluations indicate that the ARQ/AFEC system has much higher frame efficiency than ARQ without AFEC for low-bit error rate and has high frame efficiency in a wide range of bit error rates. >

Integer division using reciprocals

Abstract: By using a reciprocal approximation, integer division can be synthesized from a multiply followed by a shift. Without carefully selecting the reciprocal, however, the quotient obtained often suffers from off-by-one errors, requiring a correction step. The author describes the design decisions made when designing integer division for a new 64-b machine. The result is a fast and economical scheme for computing both unsigned and signed integer quotients which guarantees an exact answer without any correction. The reciprocal computation is fast enough, with one table lookup and five multiplies, so that this scheme is competitive with a dedicated divider, while requiring much less hardware specific to division. The real strength of the proposed method is division by a constant, which takes only a single multiply and shift, one operation on the machine considered. The analysis shows that the computed quotient is always exact: no adjustment or correction is necessary. >

Tape controller with data compression and error correction sharing a common buffer

Abstract: A controller has a data compression unit and error correcting code unit which share a single common random access memory. The controller is connected between a host computer and a peripheral device such as a tape drive. A second order search for strings of data bytes is enabled or disabled to change the compression ratio, data throughput, and memory bandwidth constraints.

Decoding cyclic and BCH codes up to actual minimum distance using nonrecurrent syndrome dependence relations

Abstract: The decoding capabilities of algebraic algorithms, mainly the Berlekamp-Massey algorithm, the Euclidean algorithm, and the authors' (1989) generalizations of these algorithms, are basically constrained by the minimum distance bounds of the codes. The authors introduce a more general procedure which breaks away from this restriction and which can determine the, error locations from nonrecurrent dependence relations among the syndromes. It can decode many cyclic and BCH codes up to their actual minimum distance and is seen to be a generalization of the procedure introduced by W.W. Peterson and E.J. Weldon (1972). >

Programmable systolic BCH decoder

Abstract: A programmable decoder that provides both error and erasure decoding for all Reed-Solomon, primitive BCH, non-primitive BCH, and binary BCH codes of any rate over any field is disclosed. The user can specify decoding parameters including the code block-length, the code-generator polynomial, and the field-generator polynomial. The basic architecture, less the small overhead for programmability, is also recommended for fixed-code applications. The decoding processor of the decoder includes systolic arrays implementing a syndrome calculator, a key equation solver, a Chien search, a recursive extender, and an inverse transform. The number of cells required for each of the five functions is on order of the error correction capability t. The systolic arrays can be fabricated on a single VLSI microchip that is itself systolic. Each of the individual systolic arrays can extended by arraying microchips together, so that any desired error correction capability can be attained by using multiple systolic microchips with a single controller.

Generation of error messages and error recovery for an LL(1) parser

Abstract: The syntactic definition of a grammar for language statements is the basis for a method for automatically generating error messages and error recovery for the language statements. The grammar is used to produce a parser, an error message generator, and error recovery for the language statements. The error message generator is produced automatically along with a parser and provides an indication of alternative valid input symbols. The method also produces the automatic generation of expected symbols lists to achieve error message generation goals. The error recovery routines are also produced automatically along with a parser and provide an indication of where valid parsing continues in the event of error detection in the language statements. The method also uses the dynamic generation of sets of synchronization symbols to achieve error recovery goals.

Robust Stabilization and Robust Performance Using Model Reference Control and Modeling Error Compensation

Abstract: A new robust linear controller design method is considered. The robust controller consists of two parts: (1) A conventional model matching feedback which assures that the reference signal to output signal transfer function is identical to that of a given reference model. (2) A conceptually new linear "modeling error compensator which exploits a modeling error signal (based on the plant input and output signals) to enhance both the stability and performance robustness It is shown that for linear SISO system of known order without right half plane zero and arbitrary variation of transer function coefficients within a given bounded set, a modeling error compensator can be designed which guarantees robust stability and an arbitrary small H ? -norm over a given frequency band. We show by example that modeling error compensation can be used to improve the robustness for systems with right half plane zeros as well. The examples further show that the transient response using model error compensation is much better than that using model reference adaptive control.

Disk allocation methods using error correcting codes

Abstract: The problem of declustering, that is, how to distribute a binary Cartesian product file on multiple disks to maximize the parallelism for partial match queries, is examined. Cartesian product files appear as a result of some secondary key access methods. For the binary case, the problem is reduced to grouping the 2/sup n/ binary strings on n bits in m groups of unsimilar strings. It is proposed that the strings be grouped such that these group forms an error correcting code (ECC). This construction guarantees that the strings of a given group will have large Hamming distances, i.e., they will differ in many bit positions. Intuitively, this should result in good declustering. The authors describe how to build a declustering scheme using an ECC, and prove a theorem that gives a necessary condition for the proposed method to be optimal. Analytical results show that the proposed method is superior to older heuristics, and that it is very close to the theoretical (nontight) bound. >

Enumerative modulation coding with arbitrary constraints and postmodulation error correction coding for data storage systems

Abstract: Modulation constraints of practically any degree of complexity can be described by a state transition table with a finite number (Omega) of states. Examples include all (d,k;c) codes (where (Omega)

A comparison of cryptanalytic principles based on iterative error-correction

Abstract: A cryptanalytic problem of a linear feedback shift register initial state reconstruction using a noisy output sequence is considered. The main underlying principles of three recently proposed cryptanalytic procedures based on the iterative error-correction are pointed out and compared.

Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums

Abstract: In this paper we study the problem of concurrent error detection in analog and switched-capacitor state variable systems. The errors can arise due to failed components (resistors, capacitors, opcrational amplifiers, etc) or simply due to line opens and shorts. A failed component is one whose value has changed due to a harsh environment (heat, etc) or due to drift or one which no longer performs its intended function (such as a shorted capacitor). The error detection is performed by a small amount of additional circuitry whose inputs are tapped directly from the outputs of all the operational amplifiers that compose the circuit on which error detection is to be performed. The sensitivity of the error detection circuitry to errors in the component values can be easily adjusted. The basic idea is to use continuous matrix chechums for error detection. This is possible because the function of an analog or switched-capacitor state variable system can be represented mathematically by a set of matrices to which checksum codes can be applied.

Balancing space and time errors in the method of lines for parabolic equations

Abstract: A new error control strategy for the time integration in the solution of parabolic equations using the method of lines is presented. The strategy aims to approximately balance the spatial discretisation and time integration errors so that they are of the same order of magnitude, but so that the time integration error is less than the spatial discretisation error. This is achieved by making use of the individual contributions of the spatial discretisation error and the time integration error to an existing estimate of the global error in the numerical solution. The new strategy is presented in the light of this global error indicator and a comparison between the new error control strategy and a similar existing strategy is made. Numerical results are used to illustrate the performance of this strategy.

Shift error correcting modulation codes

Abstract: 5A class of codes that perform bit-shift error detection/correction directly on run-length-limited (RLL) binary channel data is described. These highly efficient, variable-rate codes can be used with RLL sequences having d,k constraints of d>0 and (k-d)>or=2, and they are fully compatible with conventional signal processing, e.g., peak detection can be used. The simplest and most efficient of these codes are effective only against bit-shift error, i.e., the predominant type of channel data error caused by intersymbol interference and noise in saturation recording systems that employ RLL modulation coding. >

Combining ECC with modulation: performance comparisons

Abstract: A technique for combining error correcting codes (ECCs) with modulation codes of the block type is described. Its performance is analyzed with respect to the traditional method in magnetic recording, which involves the concatenation of error-correcting code with a convolutional modulation code. Conditions are established under which the new method is superior to the concatenated scheme. For a fixed number of information bits, the total redundancy with the two methods is calculated and conditions are established under which the redundancy of the new method is smaller than the redundancy of the traditional method. In particular, performance with respect to the

Incremental-redundancy transmission for meteor-burst communications

Abstract: The performance of type-II hybrid automatic repeat request (ARQ) is compared to that of fixed-rate type-I hybrid ARQ for meteor-burst communications. Maximum throughput is obtained for meteor-burst communications by using a transmission scheme for which the information rate of the code, varies in response to the fluctuations in the power received from a meteor trail. For type-II hybrid ARQ, a variation in the code rate is inherent in the coding scheme. On the first transmission that is made for a data block, a code of relatively high rate is used, but if an additional transmission is required, only redundant symbols are sent, and this reduces the overall rate of the code. The performance measure is the throughput per trail, which is defined as the expected number of successfully received information bits for a given meteor trail. The authors also develop an approximation for the average value of the throughput, averaged over the parameters of the meteor trail. Numerical results for Reed-Solomon codes are included to illustrate the relative performance of the various schemes. It is shown that the throughput is larger for type-II hybrid ARQ than for either fixed-rate type-I hybrid ARQ or ARQ without forward-error-correction. >

The reliability of semiconductor RAM memories with on-chip error-correction coding

Abstract: The mean lifetimes are studied of semiconductor memories that have been encoded with an on-chip single error-correcting code along each row of memory cells. Specifically, the effects of single-cell soft errors and various hardware failures (single-cell, row, column, row-column, and entire chip) in the presence of soft-error scrubbing are examined. An expression is presented for computing the mean time to failure of such memories in the presence of these types of errors using the Poisson approximation; the expression has been confirmed experimentally to accurately model the mean time to failure of memories protected by single error-correcting codes. These analyses will enable the system designer to accurately assess the improvement in mean time to failure (MTTF) achieved by the use of error-control coding. >

Bit error rate estimation techniques for digital land mobile radios

Abstract: Two methods are shown to provide reliable estimates of the raw channel BER (bit error rate) over channels which are characterized as having Rayleigh fading. In the first method, it is shown that pseudorandom noise sequences when interleaved within the transmitted data can be used to compute an autocorrelation parameter in the receiver from which the channel BER may be estimated. The accuracy of this estimate is shown to be a function of the sequence length for a given channel signal-to-noise ratio. In the second method, it is shown that if symbol interleaving is used in a Reed-Solomon-based system, side information from bounded distance decoders can be used to provide an estimate of the raw channel BER. Further, it is shown that decoder failure and error events do not significantly affect this BER estimate. >

Quasi-perfect tracking control of non-minimal phase systems

Abstract: The authors describe a new digital algorithm for quasi-perfect tracking control (QPTC) of non-minimal phase systems. The algorithm computes a feedforward signal in two steps: (1) a feedforward signal based on the zero phase error tracking control (ZPETC) algorithm of M. Tomizuka (1987); and (2) a compensation of the remaining tracking error with an additional feedforward. First, a closed-form expression is derived for the relation between the z-transform of the desired output signal and the z-transform of the tracking error resulting from the ZPETC algorithm. From this expression, the time and frequency domain properties are derived. These properties give insight into the parameters that influence the tracking error. Second, the QPTC algorithm is discussed and verified by simulation results. It shows a drastic improvement of tracking over the ZPETC algorithm. >

Speech decoder for high quality reproduced speech through interpolation

Abstract: A speech decoder includes a separating circuit, an error correction decoding circuit, an interpolating circuit, and a speech reproducing circuit. The separating circuit separates a code string of a filter parameter, a code string of a parameter associated with a pitch, and a code string of a parameter associated with an index and a gain of a codebook representing an excitation signal of speech from a received code string. The error correction decoding circuit detects a transmission error, which cannot be corrected, in the received code string. When a transmission error which cannot be corrected is detected, the interpolating circuit interpolates between parameters of past and future proper frames, thereby recovering parameters of a current frame. The speech reproducing circuit reproduces a speech signal on the basis of the interpolated parameters and other received codes.