Showing papers on "Etching (microfabrication) published in 1977"

The Loading Effect in Plasma Etching

Abstract: The dependence of etch rate on the quantity of material being etched, often referred to as the loading effect, for plasma etching is analyzed quantitatively with the aid of some simplifying assumptions. The etch rate is related to the quantity of material being etched through three phenomenological parametersβ, τ, and , which are related to the affinity of the etching material for the active species created in the plasma, the lifetime of the active species, and the volume generation rate of the active species, respectively. It is shown analytically that the reciprocal of the etch rate, when identical wafers are etching simultaneously, is directly proportional to . Data are presented for the plasma etching of Si in a plasma which confirm the analytical prediction. The significance of loading with respect to the measurement of etch rate, end‐point detection, and the interpretation of the temperature dependence of etch rate is discussed. A brief discussion of the physical meaning of the phenomenological parameters and their relation to process parameters subject to control such as power, pressure, and temperature is also included.

Ion‐surface interactions in plasma etching

Abstract: The surface chemistry and the etching behavior of silicon and oxidized silicon bombarded with a CF3+ ion beam (50–4000 eV) have been studied using Auger electron spectroscopy, and a quartz‐crystal microbalance. The conclusions of this study are as follows: (a) the etch rate of Si caused by CF3+ ion bombardment can be accounted for by physical sputtering; (b) the deposition and removal of carbon at the etched surface may be one of the most important phenomena affecting the operation of plasma‐etching systems; and (c) there is reason to believe that ion bombardment of the etched surface enhances the reaction rate of the neutral etching species which are most probably fluorine atoms and CF3 radicals.

Microwave Plasma Etching

Abstract: A new plasma etching technique using microwave discharge is presented. Silicon wafers are etched by the discharge in a (CF4+O2) gas mixture. Fine patterns with dimensions of 1 µm are etched up to 1 µm in depth without undercutting at a pressure of 5×10-4 Torr with an Al mask having 0.08 µm thickness. Etching is thought to be carried out by chemical reactions. With this technique, the etching rate becomes maximum (2.6×10-2 µm/min) when the mixing ratio γ is 20%. Symbol γ is the partial pressure of O2 divided by the total pressure. The etched depth is proportional to the etching time. This technique is suitable for etching fine patterns of semiconductor devices.

A study of the optical emission from an rf plasma during semiconductor etching

Abstract: Spectroscopic analysis of optical emission during rf plasma etching of semiconductor materials has been used to gain a better understanding of the plasma chemistry involved in these systems. The emission was studied principally in CF4−O 2 gas mixtures, but other gases were observed as well. It is known that the addition of a relatively small percentage of O2 to CF4 yields a much faster etching rate for silicon and silicon nitride. With the addition of O2 to CF4 discharges we have studied emission from atomic O and molecular CO with a large increase in the emission of atomic F. When the plasma is actively etching silicon or silicon nitride, the emission intensities of both F and O atoms are significantly lower. The etching process can be monitored by observing the intensities of these lines. Analysis of the emission features has also been used to determine abnormal conditions which can adversely affect the etching process.

Breakdown field in vapor‐grown silicon carbide p‐n junctions

Abstract: The electrical breakdown of one‐sided abrupt p‐n junctions in 6H silicon carbide has been investigated. The diodes are produced by vapor growth and mesa etching. Breakdown fields in the range (2–3.7) ×106 V/cm have been observed for p layers with 1017

Chemically Polished Quartz

Abstract: : Etching in a saturated solution of ammonium bifluoride is shown to be capable of producing chemically polished AT-cut quartz surfaces over a broad range of conditions The quality of chemical polish depends primarily on the surface finish prior to etching, the depth of etch and the quality of quartz used The speed of polishing depends primarily on the temperature of the etching bath In an 88 degree C etching bath, starting with 3 micrometers lapped blanks, chemically polished blanks with a surface roughness of 01 micrometer and a roughness angle of 1 degree can be produced in 15 minutes Starting with a finer surface finish can produce a smoother chemically polished surface Chemically polished blanks are shown to be extremely strong Fundamental mode 20 MHz resonators made with chemically polished natural quartz blanks showed no Q degradation with increasing depth of etch

Plasma etching A ’’pseudo‐black‐box’’ approach

Abstract: A framework for understanding plasma etching has been developed (using the CF4 plasma etching of silicon and silicon compounds as an example) which treats the discharge as a ’’pseudo‐black‐box’’ which is characterized by a dissociation rate G of the CF4 molecules and a recombination rate R at which CF4 and other inert molecules are re‐formed by recombination of the active fragments. Expressions based on the conservation of fluorine and carbon in the system have been derived which relate the concentration of the various species in the effluent gas to the etch rate. This approach provides a semiquantitative understanding of several aspects of plasma etching such as the effects of additive gases and the presence of a much larger ’’loading’’ effect for Si than for SiO2.

Chemical etching of silicon. iv. etching technology

Abstract: The etching of silicon in based systems proceeds by a sequential oxidation‐followed‐by‐dissolution process. In those composition regions where the solution is very low in and rich in , the rate‐limiting process is the oxidation step. Consequently, electron concentration, surface orientation, crystal defects, and catalysis by lower oxides of nitrogen play an important role. In those compositions where is in limited supply, dissolution of the formed oxide is the rate‐controlling step and diffusion of the complexing fluoride species is the important factor. Therefore, crystal orientation and conductivity type independence as well as hydrodynamic control are the consequences. In order to meaningfully select an etching composition to solve a specific processing problem, it is necessary to understand this composition‐mechanism interaction. Corollary with the mechanism understanding, sample geometry effects have been followed as a function of solution composition. The solution composition plane has been characterized into various regions where the two basic mechanisms interact and specific procesing utilization is shown. Similar results are shown for the system . In addition, a number of particular etching problems are posed, and solutions offered, that make use of these composition characterizations, and show how one can use their information to solve other practical processing problems.

Total dielectric isolation utilizing a combination of reactive ion etching, anodic etching, and thermal oxidation

Abstract: A process which utilizes an anodized porous silicon technique to form dielectric isolation on one side of a semiconductor device is described. Regions of silicon semiconductor are fully isolated from one another by this technique. The starting wafer typically is predominantly P with a P+ layer thereon. A P or N layer over the P+ layer is formed thereover such as by epitaxial growth. The surface of the silicon is oxidized and a photoresist layer applied thereto. Openings are formed in the photoresist. Openings are formed in the silicon dioxide using the photoresist as a mask and appropriate etching techniques. The openings in the silicon dioxide define the regions to be etched by reactive ion etching. Reactive ion etching is accomplished at least down to the P+ region. The structure is then subjected to the anodic etching technique which preferentially attacks the P+ layer to form porous silicon throughout the P+ layer. The structure is then placed in a thermal oxidation ambient until the porous silicon layer has been fully oxidized to silicon dioxide. The openings through the surface layer are filled up with oxide to fully isolate the P or N surface layer.

Calcium orthovanadate, Ca3(VO4)2-a new high-temperature ferroelectric

Abstract: Ferroelectricity has been discovered in calcium vanadate. Large, transparent crystals have been grown by Czochralski pulling. Electrical 180° domains of millimeter dimensions are observed by etching as-grown crystals. The ferroelectric Curie temperature, Tc = 1383 K, has been determined from dielectric, thermal and pyroelectric studies.

Ion beam texturing

Abstract: Wehner and Hajicek have reported that a microscopic surface texture could be created by sputter etching a surface while simultaneously sputter depositing a lower sputter yield material onto the surface. A xenon ion beam source has been used to perform this texturing process on samples as large as 3 cm diam. Ion‐beam‐textured surface structures have been characterized with SEM photomicrographs for a large number of materials, including Cu, Al, Si, Ti, Ni, Fe, stainless steel, Au, and Ag. Surfaces have been textured using a variety of low sputter yield materials—Ta, Mo, Nb, and Ti. The initial stages of the texture creation have been documented, and the technique of ion beam sputter removal of any remaining deposited material has been studied. A number of other texturing parameters have been studied such as the variation of the texture with ion beam power, surface temperature, and the rate of texture growth with sputter etching time.

Corrosion resistant thin film head assembly and method for making

Abstract: A slider element includes a thin film transducer deposited onto a slider along at least one of the rails forming the flying air bearing surface with a magnetic media. A portion of the end tips of the pole pieces and gap of the thin film inductive transducer and a portion of the slider rail adjacent to the transducer is etched by a sputter etching process. A layer of a passivation material such as chromium is sputter deposited into the etched portion such that the leading portion of the rail protects the passivation material from wear. The passivation material over the pole tips of the transducer prevents the corrosion of the iron-nickel alloy comprising the pole tips.

Reactor apparatus for plasma etching or deposition

Abstract: Plasma reactor apparatus which provides improved uniformity of etching or deposition. A uniform radio frequency (RF) field is established between two closely spaced parallel plates disposed within the reactor. One of the plates functions as a manifold for the reactant gases, mixing the gases and dispensing them through a regular array of orifices into the RF field between the plates. The uniformity results from a combination of the uniform field, the uniform dispersion of reactant gases, and the close proximity of the gas dispersal to the work pieces. The capacity of the apparatus can be increased by repeating the parallel plate structure in a stacked array of alternating grounded and RF energized plates.

Etching apparatus using a plasma

Abstract: An etching device uses a gas activated by a plasma for etching a semiconductor element. The apparatus includes object feeding and etching chambers formed on the opposite sides of an airtight flat chamber and a support plate rotatably mounted in the flat chamber to bring the semiconductor element from the feeding chamber to the etching chamber in which the semiconductor element is etched by the vertically flowing activated gas.

Redeposition—A serious problem in rf sputter etching of structures with micronmeter dimensions

Abstract: In sputter‐etching redeposition of sputtered material due to backscattering from the plasma or direct redeposition can seriously alter the dimensions of patterns with micron dimensions. A simple model which takes into account simultaneous sputter etching and redeposition is presented. Using this model a computer simulation was performed on the evolution of a square‐wave profile. Results from this computer simulation are compared with sputter‐etched square‐wave profiles in SiO2 as examined under the SEM.

Two and three mask process for IGFET fabrication

Abstract: Semiconductor wafer processes employing two and three masks are disclosed for fabricating a plurality of insulated gate field effect transistors (IGFETs) to be used singly as discrete devices or interconnected as integrated circuits on the wafer by means of diffused regions at a first level and a composite of polysilicon and metal silicide layers at a second level. The first mask of the two-mask process is used in opening windows through a thick oxide layer covering the wafer for the gate and diffused regions including the source and drain regions. After forming a thin oxide layer in these windows, the wafer is coated with successive layers of polysilicon and silicon nitride. Then, a second masking operation yields a pattern out of the polysilicon-nitride layer including gate electrodes and a top-lying interconnection level which abuts to openings etched through the thin oxide layer. Doping impurities are diffused therethrough to form source and drain regions and crossunders. After etching the nitride layer a silicide forming metal is deposited and sintered to form a silicide layer on all exposed silicon surfaces lowering the sheet resistance of the polysilicon layer and joining the interconnection pattern with the source and drain regions. The process is completed by removing the remaining unreacted metal using a maskless aqua regia etch.

Method for fabricating ultra-narrow metallic lines

Abstract: A method for fabricating very narrow superconducting metallic lines on a substrate using ion-implantation and etching techniques. The method permits lines to be produced which are much smaller than those fabricated by conventional masking and etching techniques. It makes the fabrication of very small Josephson and other superconducting devices possible. Also since lines are formed in metals, they have high conductivity, so are useful as ordinary conductors at high temperature or when the technique is utilized with non-superconducting materials. The method includes the steps of depositing a selected metal film on a substrate, applying a photoresist or other masking pattern and exposing, etching away the exposed region, ion-implanting the edge of the resulting pattern, removing the photoresist and etching away the unimplanted portion of the metal leaving an ultra-narrow line pattern.

Etching of Polymeric Surfaces: A Review

Abstract: The selective etching of polymeric surfaces has been of considerable interest to many polymer scientists and engineers. Some prime concerns of selective etching have been to increase the roughness of polymeric surfaces, change the surface chemical constitution, degrade or dissolve low molecular weights which migrate to the surface, and relieve residual surface stresses. Every polymeric surface, thermoplastic or thermoset, amorphous or crystalline, has, to some extent, different morphology from the bulk. Etching can considerably change the morphology and chemical properties of polymeric surfaces. An important commercial example is the etching of polymers prior to the subsequent metal plating [35, 74]. The adhesion and durability of the metal plate are greatly influenced by the condition of the polymeric surface. The increased surface area gives rise to a larger density of sites for the subsequent metal deposition. In many cases the chemical reactivity of etched surfaces is also increased upon etch...

Tapered Windows in SiO2: The Effect of NH 4 F : HF Dilution and Etching Temperature

Abstract: Etching of windows in thermally grown silicon dioxide to achieve an approximately 45° taper edge profile has been empirically optimized using compositions and etching bath temperatures Steeper slopes or much shallower tapers are obtainable by suitable adjustments of these two experimental parameters The mechanism by which tapering occurs may best be described as a controlled separation of the photoresist/oxide interface which relates the lateral etch rate to the bulk etch rate Depending on etching conditions, each beveled window edge consists of two or three distinct regions which comprise the final shape of the sloping taper The dissolution reaction in all instances was found to be activation controlled with an apparent activation energy of 99 kcal/mole Curves of etch rates as a function of temperature and molarity are presented and a quantitative relationship for etch rate in terms of these two parameters is given

Investigations on the damage caused by ion etching of SiO2 layers at low energy and high dose

Abstract: The radiation damage caused by argon ion bombardment during ion etching of thermally grown SiO 2 films at an energy below 1 keV and a dose of about 10 18 cm −2 has been studied by evaluating MOS C-V curves, FET characteristics, as well as Rutherford ion backscattering spectra. The bombarded samples revealed that ion beam etching in this energy range causes a damaged layer of 5–10 nm thickness at the single crystal silicon surface. Moreover, traces of metal atoms are found in the damaged layer together with argon atoms (≈ 10 21 cm −3 ).

Enhanced crystallinity of silicon films deposited by CVD on liquid layers (CVDOLL process): Silicon on tin layers in the presence of hydrogen chloride

Abstract: Chemical vapor deposition of silicon on a graphite substrate coated with a 5‐μm‐thick fluid tin layer provides a possibility for the production of large grained polycrystalline silicon layers. Using silane as a source material, crystallites can be produced with a mean grain size of about 20 μm, compared with 5 μm on a substrate without fluid layer. The grain size can be further enhanced by adding HCl as an etching agent to the gas phase. Mean crystallite sizes of 100 μm and larger can be obtained by the use of a fluid layer and a proper combination of SiH4 and HCl.

Dry processing of high resolution and high aspect ratio structures in GaAs-Al(x)Ga(1-x) As for integrated optics.

Abstract: The properties of ion-beam milling, rf-sputter etching, and plasma etching for the fabrication of high resolution integrated optical structures in GaAs and AlxGa1−xAs were investigated. The ion-beam milling rates for a 500-eV Ar beam were measured as a function of the angle of incidence for A2-1350 photoresist, GaAs, Al, Ti, and Ta in vacuum. For Ti and Ta, the ion-beam milling rates were measured for various O2 partial pressures in the target chamber. For the fabrication of high-resolution patterns, a technique was developed in which a very thin resist pattern is transferred by plasma etching into a layer of Ta prior to ion-beam milling. Both ion-beam milling and rf-sputter etching through the Ta metal mask were used for the fabrication of gratings in GaAs. From measurements made in this study, it was found that rf-sputter etching in an Ar atmosphere results in a resolution comparable to ion-beam milling at normal incidence, but the material removal efficiency is somewhat lower. Third-order Bragg diffraction gratings (period = 0.36–0.37 μm) for GaAs-AlxGa1−xAs heterostructure lasers and ridged stripes 10 μm wide and 1.5–2.0 μm deep have been prepared by these techniques. High-aspect ratio or skewed-profile gratings were obtained by selection of the ion-beam milling or rf-sputter etching conditions. As previously reported, these structures have been overgrown by MBE AlxGa1−xAs layers to form distributed feedback lasers.

Polycrystalline silicon etching with tetramethylammonium hydroxide

Abstract: A family of etchants for polycrystalline silicon based upon an aqueous solution of NR4 OH, where R is an alkyl group, has a relatively low etching rate enabling the exercise of better control over the delineation of fine structures

Selective lift-off technique for fabricating gaas fets

Abstract: MBE growth of epitaxial layers on selected areas of a growth surface (e.g., wafer or epi-layer grown thereon) is achieved by masking portions of the surface with an amorphous material and directing molecular beams at the masked surface so that a polycrystalline layer deposits on the mask and an epi-layer grows in the unmasked zones. The mask material is then exposed to a suitable etchant effective to dissolve that material, lift-off the polycrystalline layer and expose the underlying surface. Self-aligned contacts can be fabricated by depositing a metal layer prior to etching. Subsequent lift-off removes both the polycrystalline layer and the overlying metal. This process can be utilized in the fabrication of FETs and opto-electronic devices such as double heterostructure junction lasers.

Mos type semiconductor device and its manufacture

Abstract: PURPOSE: To manufacture the short channel MOS, by providing the source and drain with self alignment, after providing the insulation film with vapor phase growing only on the gate side surface and its vicinity. CONSTITUTION: Field oxide film 2, gate oxide film 3, and poly-Si gate 4' are formed on the p type Si substrate 1, and the CVD oyxide film 6 is uniformly de- posited. Next, when etching gas is vertically incident, the etching speed is slow at the gate side surface 4'b. When the film 3 and the film 6 of the gate upper surface 4'a are removed and etching is stopped, fine insulation film pattern 6' covering only the side surface 4' and the gate film 3 near it is formed and the width W is the thickness of the film 6 on the side surface 4'b. After that, diffusion is made so that the spread 1 to the side of the n type source and drain 7 and 8 is greater than the width w of the film 6', CVD oxide film 9 is deposited and electrodes 10 to 12 are provided by performing selective opening. With this constitution, without lower- ing the ric dielectric strength between the gate and the source and drain, short channel MOS can be formed. COPYRIGHT: (C)1979,JPO&Japio