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Showing papers on "FET amplifier published in 1982"


Journal ArticleDOI
TL;DR: In this paper, a computer-aided design (CAD) procedure is introduced for treating the broadband matching of an arbitrary load to a complex generator, which can be applied to the design of interstage equalizers for microwave amplifiers.
Abstract: A computer-aided design (CAD) procedure, which is a new and simplified "real frequency" technique, is introduced for treating the broad-band matching of an arbitrary load to a complex generator. The method can be applied to the design of interstage equalizers for microwave amplifiers. It utilizes the measured data obtained from the generator and the load networks. Neither an a priori choice of an equalizer topology, nor an analytic form of the system transfer function, is assumed. The optimization process of the design procedure is carried out directly in terms of a physically realizable, unit normalized reflection coefficient which describes the equalizer atone. Based on the load-generator matching technique, a sequential procedure to design multistage microwave amplifiers is presented. An example is given for a three-stage, FET amplifier proceeding directly from the measured scattering parameters of the FET devices. The example is in three parts and illustrates the sequential method; that is, first a single-stage, then a two-stage, and finally the three-stage system is computed.

175 citations


Patent
Eric J. Swanson1
20 Dec 1982
TL;DR: An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means as discussed by the authors.
Abstract: An enhancement mode (104, 204, 404) and a depletion mode (102, 202, 402) pair of N-channel MOS transistors have their drain-source conduction paths connected in series and provided with a bias current means (120, 220, 306, 410) The gates (106, 206, 308, 310) are coupled together as an input node In one embodiment (100) their bulk regions are source-connected and the output (118) is from the source of the enhancement mode device (104) to obtain a source follower configuration amplifier In a second embodiment (200), the output (218) is taken from the drain (208) of the depletion mode device (202) to obtain a common source configuration amplifier Two source follower pairs (302, 304) are disclosed connected in parallel to form a differential input voltage amplifier stage (300) A common source pair (402, 404) is disclosed in combination with an additional enhancement mode transistor (406) to form a current mirror (400)

61 citations


Patent
Lanny S. Smoot1
26 Jul 1982
TL;DR: In this article, an improved transimpedance amplifier allows an optical transmitter and receiver to be in close proximity to each other without fear of overloading the receiver, which increases the dynamic range of the Transformer.
Abstract: An improved transimpedance amplifier allows an optical transmitter and receiver to be in close proximity to each other without fear of overloading the receiver. The improvement increases the dynamic range of the transimpedance amplifier and thereby the operating range of the receiver. A peak detector (22) at the output of an inverting amplifier (11) within the transimpedance amplifier turns on a field effect transistor (FET) circuit (23) when an AC component of an electrical signal becomes so large that the inverting amplifier would otherwise go into saturation. The FET circuit (23) acts as an AC shunt impedance at the input of the inverting amplifier and diverts the excess AC current to ground (30). Also, the FET circuit (23) acts as a DC resistance in concert with sense and sink current mirrors (21) and (24) to effectively divert an excessive DC component of the electrical signal away from the input of the inverting amplifier (11). Although the dynamic range of the transimpedance amplifier is increased, the optical sensitivity and the performance of the receiver remain unchanged.

41 citations


Patent
21 Jun 1982
Abstract: A three terminal bidirectional FET circuit is provided by first and second MOSFETs connected source to source in series relation between first and second main terminals, and by gating circuitry including current source means connected to a gate terminal for driving the FETs into conduction. A resistor is connected between a point common to the FET sources and a point common to the FET gates and the current source, such that the gate to source voltage for each FET is the same regardless of the relative polarity of the main terminals.

40 citations


Patent
23 Sep 1982
TL;DR: In this article, a predistortion circuit for a radio frequency power amplifier which has gain and phase shift characteristics that are non-linear as a function of power level of an RF input signal is presented.
Abstract: A predistortion circuit for a radio frequency power amplifier which has gain and phase shift characteristics that are non-linear as a function of power level of an RF input signal The circuit includes a dual gate FET, with a drain coupled to the power amplifier A modulated RF input signal is applied to an inductive matching network which is coupled to the signal gate of the FET A modulating envelope detected version of the input signal is applied to a video amplifier which is coupled to the FET control gate The signal applied to the control gate varies the gain of the FET as a function of input signal to compensate for the non-linear gain characteristic of the power amplifier and in conjunction with the matching network causes a phase change of the signal through the predistortion circuit to compensate for the non-linear phase characteristic of the power amplifier

32 citations


Patent
29 Jun 1982
TL;DR: In this article, a transformer drive circuit for a high voltage field effect transistor has been proposed, which includes a small transformer coupled to the gate and source with a diode in series at the gate, so that a short on-drive pulse charges the gate capacitance, and the charge is held by the diode.
Abstract: The high voltage field effect transistor has a drive circuit for pulse width modulation, which includes a small transformer coupled to the gate and source with a diode in series at the gate, so that a very short on-drive pulse charges the gate capacitance, and the charge is held by the diode. Another FET has its output connected between the gate and source of the high voltage FET, and its input coupled to another small transformer so that it is turned on for a short time by a very short off-drive pulse to discharge the gate capacitance and thus turn off the high voltage FET. A transformer drive circuit includes two one-shot devices connected to the pulse width modulator as leading and trailing edge detectors respectively, with their outputs connected via FET's to the on-drive and off-drive transformer primaries respectively, to provide pulses of 100-200 nanoseconds.

31 citations


Patent
21 Jun 1982
TL;DR: In this article, a fast turn-off FET circuit is provided by a bipolar transistor in the gate circuit of the FET, which is driven into conduction by residual charge.
Abstract: A fast turn-off FET circuit is provided by a bipolar transistor in the gate circuit of the FET. The bipolar transistor is driven into conduction by residual charge in the gate to source capacitance of the FET upon turn-off of the latter due to removal of gate drive. Conduction of the bipolar transistor provides faster discharge therethrough of the FET gate, whereby to facilitate faster FET turn-off without reverse gating current and its attendant auxiliary power supply.

31 citations


Patent
Robert Reiner1
07 Jul 1982
TL;DR: In this paper, a monolithically integrable MOS-comparator has a capacitor, a signal input and a reference input of the comparator being alternatingly connected to the capacitor via respective first and second clock-controlled transfer transistors.
Abstract: A circuit of a monolithically integrable MOS-comparator has a capacitor, a signal input and a reference input of the comparator being alternatingly connected to the capacitor via respective first and second clock-controlled transfer transistors, a first amplifier stage having a control input and an output, the capacitor being directly connected to the control input and being also connected via a third transfer transistor to the output of the first amplifier stage, a second amplifier stage having a control input and an output, the output of the first amplifier stage being further connected via a fourth transfer transistor to the control input of the second amplifier stage. A third amplifier stage identical with the first and second amplifier stages has a signal input and an output, the output of the second amplifier stage being a first signal output of the comparator and being also connected to the signal input of the third amplifier stage. The output of the third amplifier stage as a second signal output of the comparator and as connected via a fifth transfer transistor to the control input of the second amplifier stage. Means for transmitting two clock signals are connected to the first and second transfer transistors, respectively, for alternatingly switching the signal input and the reference input, respectively, of the comparator to the capacitor, the signal-transmitting means being also connected to the third, fourth and fifth transfer transistors for controlling the same.

27 citations


Book
01 Jan 1982
TL;DR: The history of the Thermionic Valve Operation of the Electron Tube Wiring Tube Circuits CD/Line Amplifier Hi-Fi Amplifier General-Purpose Line Amplifier Pick-Up/line Amplifier with SRPP Output Hi-FI Output Amplifier for CD Players Track Layouts of PCBs.
Abstract: Contents: History of the Thermionic Valve Operation of the Electron Tube Wiring Tube Circuits CD/Line Amplifier Hi-Fi Amplifier General-Purpose Line Amplifier Pick-Up/Line Amplifier with SRPP Output Hi-Fi Output Amplifier with 2xEL34 Class A Stereo Output Amplifier with 2xKT88 Miscellaneous Amplifiers Guitar/Keyboard Amplifiers Guitar Amplifier with Transistor Input Voltage Regulation with Valves Heater-Voltage Supplies SRPP Amplifier for CD Players Track Layouts of PCBs.

26 citations


Patent
21 Jun 1982
TL;DR: In this paper, a three terminal bidirectional FET circuit is provided by first and second MOSFETs connected drain to drain in series relation between the main terminals, and by gating circuitry providing requisite gate drive to a corresponding FET regardless of the polarity of its correspondent main terminal.
Abstract: A three terminal bidirectional FET circuit is provided by first and second MOSFETs connected drain to drain in series relation between first and second main terminals, and by gating circuitry providing requisite gate drive to a corresponding FET regardless of the polarity of its correspondent main terminal. A current source is connected to a common point between the FET gates, which common gate point is referenced through a resistor and a pair of diodes to the most negative of the main terminals.

23 citations


Patent
Stephen George Harman1
21 Jun 1982
TL;DR: In this article, an intermediate frequency preamplifier of a microwave radio receiver includes an amplifier circuit having a negative feedback path (16, 22, 7) including a directional coupler (7) constituted by two transformers (71, 72).
Abstract: @ An intermediate frequency preamplifier of a microwave radio receiver includes an amplifier circuit having a negative feedback path (16, 22, 7) including a directional coupler (7) constituted by two transformers (71, 72). One port (D) of the directional coupler (7) is terminated with a complex impedance (8, 20), producing a controlled mis-match, which is adjustable to optimize the input return loss of the amplifier without changing the noise figure of the preamplifier. The amplifier circuit has a low impedance output (2) constituted by a common-collector transistor (6) so that the signal reflected back into the directional coupler (7) by the mis-match does not significantly affect the output of the amplifier.

Patent
24 May 1982
TL;DR: In this article, the drain electrodes of the transistors are coupled to a current mirror load for converting balanced signals to a single ended output which in turn is applied to a common source amplifier.
Abstract: Imbalances in the potential appearing across the drain electrodes of source coupled FET transistors arranged in a differential amplifier configuration tends to produce input offset voltages. Where the drain electrodes of the transistors are coupled to a current mirror load for converting balanced signals to a single ended output which in turn is applied to a common source amplifier, the input offset may be nulled by differentially adjusting the drain current of the common source amplifier against the source current of the differential stage.

Patent
21 Jun 1982
TL;DR: In this article, a fast turn-off FET circuit is provided by regeneratively coupled bipolar transistors in the gate circuit of the FET which are driven into latched conduction by residual charge in a gate to source capacitance of the latter due to removal of gate drive.
Abstract: A fast turn-off FET circuit is provided by regeneratively coupled bipolar transistors in the gate circuit of the FET which are driven into latched conduction by residual charge in the gate to source capacitance of the FET upon turn-off of the latter due to removal of gate drive. The regeneratively coupled bipolar transistors remain in latched conduction until the FET gate charge is depleted. Conduction of the bipolar transistors provides faster discharge therethrough of the FET gate, whereby to facilitate faster FET turn-off without reverse gating current and its attendant auxiliary power supply.

Proceedings ArticleDOI
15 Jun 1982
TL;DR: In this article, the design, construction, and performance of an X-band multi-chip GaAs monolithic transmit/receive module is described, which consists of a four-bit FET phase shifter, two-stage low-noise amplifier, four-stage power amplifier, and associated FET switches.
Abstract: The design, construction, and performance of an X-band multi-chip GaAs monolithic transmit /receive module is described. The module consists of a four-bit FET phase -shifter, two-stage low-noise amplifier, four-stage power amplifier, and associated FET switches.

Patent
06 Jul 1982
TL;DR: In this article, a non-volatile memory cell contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) for storing a data bit and a variable-threshold insulated-gate FET (Q3) that serves as a nonvolatile storage location.
Abstract: A non-volatile memory cell (20) contains a pair of cross-coupled like-polarity FET's (Q1 and Q2) that serve as a volatile location (21) for storing a data bit and a like-polarity variable-threshold insulated-gate FET (Q3) that serves as a non-volatile storage location (22). The variable-threshold FET has its source coupled to the drain of one of the cross-coupled FET's, its insulated-gate electrode coupled to the drain of the other of the cross-coupled FET's, and its drain coupled to a power supply. A pair of impedance elements (R1 and R2) are coupled between the drains of the cross-coupled FET's, respectively, on one hand and the power supply on the other hand. Just before a power shutdown which causes the data bit to evaporate, the power supply is pulsed to a suitable level to cause the bit to be transferred to the non-volatile location. When power is restored to the normal level, the original data bit automatically returns to the volatile location.

Patent
10 Sep 1982
TL;DR: In this article, a transistor mixer and amplifier input stage which includes a mixer and a differential amplifier whose gain is controlled by a voltage generated by an AGC circuit is described, where two transistors, each having a resistor connected in series with its emitter, are connected between the inputs of the differential amplifier and the mixer.
Abstract: A transistor mixer and amplifier input stage which includes a mixer and a differential amplifier whose gain is controlled by a voltage generated by an AGC circuit. Two transistors, each having a resistor connected in series with its emitter, are connected between the inputs of the differential amplifier and the mixer. When the level of the input signal increases beyond a given level, the two transistors begin to conduct, thereby shunting the differential amplifier.

Patent
21 Jun 1982
TL;DR: In this article, a fast turn-on FET circuit is provided by a constant current source and fast turnon capacitor combination in the gate circuit of the FET, where a bypass capacitor momentarily short-circuits a control resistor in the current source such that a momentarily higher current is supplied by the current-source to FET gate until the capacitor is charged, whereafter constant current as controlled by the resistor is supplid to the gate circuitry to maintain conduction.
Abstract: A fast turn-on FET circuit is provided by a constant current source and fast turn-on capacitor combination in the gate circuit of the FET. At turn-on, a bypass capacitor momentarily short-circuits a control resistor in the current source such that a momentarily higher current is supplied by the current source to the FET gate until the capacitor is charged, whereafter constant current as controlled by the resistor is supplid to the FET gate circuitry to maintain conduction.

Patent
Trung Le1
13 May 1982
TL;DR: In this paper, a closed loop bias adjustment circuit samples the lower of the output levels of the differential amplifier output stages to control a variable current source, which draws current from the amplifier to bias the output transistors thereof to provide optimum speed, maximum voltage swing and minimum power dissipation.
Abstract: In a differential amplifier circuit a closed loop bias adjustment circuit samples the lower of the output levels of the differential amplifier output stages to control a variable current source. This variable current source draws current from the amplifier to bias the output transistors thereof to provide optimum speed, maximum voltage swing, and minimum power dissipation.

Journal ArticleDOI
TL;DR: In this paper, the space charge injection FET (SICFET) was used to achieve low values of gate capacitance associated to high values of trans-conductance leading to gain-band with product close to the submillimetric wavelength range.
Abstract: Results of Monte Carlo simulation of a new type of transistor: the space charge injection FET, are reported. Due to the use of submicronic undoped active regions, it seems possible to achieve low values of gate capacitance associated to high values of trans- conductance leading to gain-bandwith product close to the submillimetric wavelength range.

Patent
10 Dec 1982
TL;DR: In this article, an FET is fixed to one face with its source connected directly to the ground plane through a wire and the gate and drain are similarly connected by wires (21, 22) to metallised areas (23, 24) isolated from the ground planes.
Abstract: An alumina plate (12) has several passive microstrip components (14) on one face (13) while the opposing face (15) has metallised areas to form a ground plane (16). An FET (11) is fixed to this face with its source connected directly to the ground plane through a wire (20). The gate and drain are similarly connected by wires (21,22) to metallised areas (23, 24) isolated from the ground plane. The FET is positioned over a housing area (32) in a metallic support (30) to provide protection and to which it is fastened by flexible clips (31). Connections from the FET to the components is through metallised holes (25,26) which are hermetically sealed during an encapsulation process.

Patent
Merle V. Hoover1
20 May 1982
TL;DR: In this paper, a programmable unijunction transistor (PU transistor) is substituted for programmable CMOS-FET integrated circuits, where the FET circuitry is arranged between first and second terminals defining a conduction path exhibiting a negative resistance characteristic and a control terminal for establishing the peak voltage of such characteristic.
Abstract: FET circuitry is described which may be substituted for a programmable unijunction transistor particularly on CMOS-FET integrated circuits. The FET circuitry is arranged between first and second terminals defining a conduction path exhibiting a negative resistance characteristic and a control terminal for establishing the peak voltage of such characteristic. A P-type MOS transistor has its source and gate electrodes respectively connected to the first and control terminals. A current mirror amplifier comprising N-type MOS transistors has its input terminal connected to the drain electrode of the P-type transistor, its output terminal connected to the control terminal and its common terminal connected to the second terminal of the circuitry.

Patent
16 Sep 1982
TL;DR: In this article, an improved voltage controlled amplifier employing an operational transconductance amplifier which is temperature independent and offering an improved dynamic range for the input signal is disclosed, where an operational amplifier configured in the inverting mode is used as an input device having a first operational transconductor amplifier in the feedback path as a gain control element.
Abstract: An improved voltage controlled amplifier employing an operational transconductance amplifier which is temperature independent and offering an improved dynamic range for the input signal is disclosed. An operational amplifier configured in the inverting mode is used as an input device having a first operational transconductance amplifier in the feedback path as a gain control element. The output of the operational amplifier provides a control voltage to effectively drive a second operational transconductance amplifier.

Patent
01 Nov 1982
TL;DR: In this paper, a digital phase bit is provided for microwave operation, comprising a pair of FET switches and at least three transmission lines, each of two of the transmission lines exhibits a series inductive impedance over the operating frequency band and shunts a FET switch, two shunt combinations being interconnected by the third transmission line.
Abstract: A digital phase bit is provided for microwave operation, comprising a pair of FET switches and at least three transmission lines. The FETs when operated in a digital switching mode, present a small impedance when on and a high impedance when off. Each of two of the transmission lines exhibits a series inductive impedance over the operating frequency band and shunts a FET switch, two shunt combinations being interconnected by the third transmission line. When the switches are on, the signal path is effectively through the FET switch alone (and not branched) and a reference phase shift is produced. When the FET switches are off, a signal applied to the phase bit branches at each shunt combination. The inductive reactance of the transmission line and the capacitive reactance of the FET switch of each shunt combination then jointly produce a resonantly enhanced reactance over the band, causing a reflection and a maximum differential phase shift. The reflections are cancelled at the input port by a suitable choice of length and impedance for the third transmission line. The phase bit is suitable for monolithic fabrication on a common semiconductor substrate and is bidirectional when symmetrical FET switches are used.

Patent
06 May 1982
TL;DR: In this paper, a changeover switch is used to select either an electret capacitive microphone (M) or a tele-induction coil (T) for receiving l.f. signals via a magnetic field.
Abstract: The hearing and amplifier input circuit has a change-over switch (S) to select either an electret capacitive microphone (M) or a tele-induction coil (T)(for receiving l.f. signals via a magnetic field). The change-over switch short circuits whichever device has not been selected and thereby reduces cross-talk from the unselected device. The circuit can be attached directly to a telephone loop and used in theatres, lecture-halls, cinemas, churches etc., for the hard-of-hearing. The microphone is coupled via a resistor and capacitor to the input (base) of an amplifier (Q) whose output passes to the hearing aid's main amplifier. The induction coil is connected to the amplifier's emitter. The change-over switch effectively alters the configuration of the amplifying transistor from an earthed emitter (with high negative feedback and low output impedance) to earthed base (with high output impedance).

Patent
18 Mar 1982
TL;DR: In this paper, a linear, class A FET amplifier circuit with a time-varying envelope function was proposed, where the gate bias voltage is dynamically controlled by the envelope of the input signal.
Abstract: The present invention relates to a linear, class A FET amplifier circuit capable of providing linear amplifier of input signals with a time-varying envelope function. An envelope detector (12) is responsive to an input signal (vi (t)) for extracting the envelope signal (Vi (t)) therefrom. A gate controller (16) subsequently adds the envelope signal to a predetermined gate bias voltage (EG) and applies the sum (EG (t)) as the "d-c" gate input to the FET amplifier (14). Therefore, the gate bias voltage is dynamically controlled by the envelope of the input signal, resulting in a significant improvement in the power-added efficiency (ηadded) over prior art class A FET amplifiers.

Proceedings ArticleDOI
15 Jun 1982
TL;DR: Sub-half-micron gate GaAs FET's have been used to fabricate a MIC balanced amplifier module with 4.2 dB of minimum gain over 26.5-40.0 GHz and data is presented for gain, VSWR, noise figure, and power on the module.
Abstract: Sub-half-micron gate GaAs FET's have been used to fabricate a MIC balanced amplifier module with 4.2 dB of minimum gain over 26.5-40.0 GHz. The module and devices are described and data is presented for gain, VSWR, noise figure, and power on the module.

Patent
17 May 1982
TL;DR: In this paper, a feedback loop to a regulator transistor within the drain circuit of the input field effect transistor (FET) serves to maintain the voltage across the drain-gate junction at a constant value consistent with FET operation as a source follower, thereby mitigating junction to junction capacitances within the FET.
Abstract: A first feedback loop to a regulator transistor within the drain circuit of the input field effect transistor (FET) serves to maintain the voltage across the drain-gate junction of the input FET at a constant value consistent with FET operation as a source follower, thereby mitigating junction to junction capacitances within the FET. A second feedback loop created guard circuits on the cases of the input FET and the drain circuit regulator transistor, thereby mitigating junction to external circuitry capacitances. A third feedback loop modifies essentially constant current flow in the source circuit of the input FET in order to compensate for capacitance within that circuit. When utilized in compact form for microprobing of low voltage nanosecond rise time signals, the amplifier demonstrates an effective input capacitance of less than 0.5 picofarads.

Patent
08 Apr 1982
TL;DR: In this article, a reduction in noise figure is obtained by using a single gate gallium arsenide field effect transistor (GaAs FET) as the RF preamplifier and providing an AGC control signal.
Abstract: RF preamplification with AGC is employed because of the wide range of signal levels to which the RF input section of a radio is subjected. A reduction in noise figure is obtained by using a single gate gallium arsenide field effect transistor (GaAs FET) as the RF preamplifier and providing an AGC control signal to vary the gain of the RF preamplifier so that the subsequent circuits are not overloaded when high RF signal levels appear at the input.

Patent
19 Nov 1982
TL;DR: In this paper, a feedback circuit is provided between the output and the input of a lower transistor amplifier of a push-pull amplifier driver output stage to inhibit power supply transients as the amplifier output stage transitions rapidly from a low to high output state.
Abstract: A feedback circuit is provided between the output and the input of a lower transistor amplifier of a push-pull amplifier driver output stage to inhibit power supply transients as the amplifier output stage transitions rapidly from a low to high output state. Additionally, if the push-pull output stage is incorporated within a three state gate or the like, which gate shares a common bus with other like three state gates, the feedback circuit inhibits loading of the bus whenever the three state gate is operated in a three state mode or is powered down as the other gates are active and are rapidly transitioned between low and high output states. The feedback circuit provides a low impedance path at the input of the lower transistor amplifier of the push-pull driver output stage to shunt transient currents harmlessly away from the base thereof to prevent the transient currents from turning on the lower transistor amplifier.

Patent
Takeshi Sato1
07 Jan 1982
TL;DR: In this article, a TV tuner circuit having a dual-gate MES FET in a UHF RF amplifier and a dualgate MOS FET, which are both controlled by a single AGC voltage source, is presented.
Abstract: A TV tuner circuit having a dual-gate MES FET in a UHF RF amplifier and a dual-gate MOS FET in a VHF RF amplifier which are both controlled by a single AGC voltage source. The source of the MES FET is always connected to a DC source voltage input through a resistor so as to ensure that no DC current flows from an AG voltage source to the second gate of the dual-gate MPES FET in receiving VHF signals. Accordingly, there is no drop in the AGC voltage applied to the second gate of the dual-gate MOS FET in the VHF RF amplifier, thereby enabling both the UHF RF amplifier and the VHF RF amplifier to have the same gain reduction characteristics.