Showing papers on "Field-effect transistor published in 1972"

Development, Operation, and Application of the Ion-Sensitive Field-Effect Transistor as a Tool for Electrophysiology

Abstract: A new solid-state device has been developed for the measurement of ion activities in electrochemical and biological environments. One can recognize in the device the properties of both a glass electrode and a field-effect transistor. This justifies the name ion-sensitive field-effect transistor. The device makes it possible to measure ion activities without using a reference electrode. For its application, a special electronic circuit is described. Results of measured Na + and H + ion activities are given in detail. As an example for electrophysiological application, results are shown of recorded extracellular ion pulses measured with a guinea pig taenia coli.

Ion-implanted complementary MOS transistors in low-voltage circuits

Abstract: Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.

Electron dynamics in short channel field-effect transistors

Abstract: The dynamics of electrons between the source and drain of a microwave field-effect transistor (FET) have been studied using a Monte Carlo method. The spatial dependence as well as the time dependence of the average electron velocity is presented. It is shown that in silicon the relaxation time is short enough not to influence the figure of merit of the transistor. However, in direct gap polar semiconductors (e.g., GaAs), the electrons can have a velocity well above their saturation value for an appreciable length of time and, consequently, over a distance nonnegligible compared to the length of the active region of a high frequency FET. This could improve the figure of merit of the FET.

Low level currents in insulated gate field effect transistors

Abstract: A theory for low-level current operation in Insulated Gate Field Effect Transistors is developed. Using the depletion approximation for the semiconductor surface potential, an analytical expression is obtained which is accurate for gate voltages corresponding to surface operation from depletion to the onset of strong inversion. Numerical calculations that avoid the limitations on gate voltage have shown the theory to hold as well for surface potentials corresponding to strong inversion.

Schottky barrier type field effect transistor

Abstract: A Schottky barrier gate field effect transistor is capable of operating in the enhancement mode. The transistor includes a gallium arsenide layer formed on a substrate. The relationship between the thickness W and impurity concentration N of the gallium arsenide layer is given by the expression: 2 X 103CM 1/2 < W . square root N < 3 X 103 cm 1/2.

A two-dimensional analysis of gallium arsenide junction field effect transistors with long and short channels

Abstract: A two-dimensional analysis of indium phosphide junction field effect transistors with long and short gates is presented. The two devices are shown to have properties similar to those of gallium arsenide JFETs. The short gate device has a negative resistance region at low drain voltages which is absent in the long gate device. The negative resistance region is determined by the distribution of the drift velocity along the conducting channel, and the resulting distribution of the electron charge. A field dependent mobility is used, and its effect on current saturation is discussed. The electrostatic charge distribution and electric field distribution are calculated for both devices, and are shown in graphic form.

Input transient protection for complementary insulated gate field effect transistor integrated circuit device

Abstract: A COS/MOS INTERGRATED CIRCUIT DERIVE OF THE TYPE HAVING A DIFFUSED WELL REGION AND COMPLEMENTARY INSULATED GATE FIELD EFFECT TRANSISTORS INSIDE AND OUTSIDE THE WELL REGIONS, RESPECTIVELY, HAS AN INTEGRAL CIRCUIT FOR PROTECTING THE GATE INSULATORS OF THE INSULATED GATE FIELD EFFECT TRANSISTORS FROM DESTRUCTIVE TRANSIENTS. THE PROTECTION CIRCUIT INCLUDES A DIFFUSED RESISTOR MADE AT THE SAME TIME AS THE SOURCE AND DRAIN REGIONS OF THE TRANSISTOR WHICH IS WITHIN THE WELL REGION. THE DIFFUSED RESISTOR IS DISPOSED WITHIN A REGION MADE AT THE SAME TIME AS THE WELL REGION.

Burglar alarm actuated by cut telephone wire

Abstract: A burglar alarm which is actuateable by the cutting of a telephone set wire such as located outside of a residence home, the alarm relay switch-actuating circuit being connected to either battery or DC-rectified AC-power source, the detector and actuating circuitry of a preferred embodiment including positive and negative leads connectable to telephone wire contacts of corresponding polarity, each lead including adjacent to the respective contacts, in series, a resistor, the respective resistors being connected to different terminals of each of a third resistor, a capacitor, a zener diode, and a field effect transistor (FET), the negative lead being connected to the FET gate terminal and to the diode such that electrons are flowable solely from said negative lead to said positive lead, and said postive lead being connected to each of the FET source and to a base of typically an NPN transistor, the FET drain being connected in series through a fourth resistor and a relay switch coil to the NPN collector, the relay switch being actuateably closeable of an alarm power circuit, the NPN emitter being connected to one terminal of a second capacitor and to a DC power source terminal of the relay alarm switch-actuating circuit, and the remaining relay switch being connected to each of the remaining terminal of the second capacitor and the remaining coil lead to the relay switch, the relay alarm switch-actuating circuit preferably including, in series, the relay actuating coil, the NPN transistor, a step-down transformer coil, and a rectifier diode permitting DC current to flow toward each of said collector and said drain.

Drain Feedback - A Novel Feedback Technique for Low-Noise Cryogenic Preamplifiers

Abstract: This paper describes a novel technique of charge restoration - the drain feedback, based on the characteristics of the gate-to-drain junction of the input FET. The restoration charge required at the input of the preamplifier is generated by impact ionization in high-field regions of the FET. Actually the feedback is obtained by regulating the drain voltage according to the input energy count-rate product and consequently adjusting the electric field for the necessary charge generation. In the first part of the paper the principles of impact ionization in semiconductors at cryogenic temperatures are outlined and applied to junction FET's (JFET's) under saturation conditions. Then, the properties of FET gate leakage current generated by impact ionization are analyzed. Finally, the continuous mode of operation of the new feedback method is presented, and results from its application in x-ray spectroscopy with silicon and germanium detectors are given. Superior noise and count-rate performance coupled with simplicity and reliability are the outstanding features of the drain feedback method. It is the first feedback method in which the cryogenic input stage comprises the detector and the FET without the parasitic increases of stray capacitance or light-induced leakage currents characteristic of the other resistorless configurations.

Method of making a semi planar insulated gate field-effect transistor device with implanted field

Abstract: A semi-planar insulated gate field effect transistor integrated circuit device having an ion implanted field region to achieve high field inversion voltage. The field effect transistor is fabricated on an elevated region of P-type silicon surrounded by and aligned to an implanted P-type field region. A thick field oxide layer on the implanted P-type field region surrounds and extends somewhat above the elevated region of P-type silicon in which the field effect transistor is fabricated. The field effect transistor includes N+ source and drain regions, a gate oxide insulator, a gate electrode and an interconnect metal layer provided in the elevated active region of P-type silicon. The method of manufacturing includes thermally growing a high integrity oxide layer on the P-type substrate, depositing a layer of nitride thereon, and removing the nitride over the field region, thereby leaving nitride over the active region of the silicon. The surface of the device is bombarded with boron ions to produce an implanted layer in the field region, with the nitride serving as an implant mask. The boron ions are then redistributed by application of a heat cycle. A thermal oxidation step increases the thickness of the oxide over the field, causing a deeper implanted P-type field region to be formed. The surface concentration of the implanted field region is increased by a subsequent heat cycle to compensate for boron ions depleted at the oxide-silicon interface during the oxidation cycle. The oxide formed on the nitride is removed and the field effect transistor is provided in the active region in a conventional manner.

Characteristics of p-channel MOS field effect transistors with ion-implanted channels

Abstract: Ion implantation technology was employed in the fabrication of MOS devices. Boron doses in the range of 0·4 × 10 12 to 1·72 × 10 12 ions/cm 2 were implanted into the channels of MOSFETs at 42 keV. Both low threshold enhancement-mode and depletion-mode devices were obtained. The variation of threshold voltage of enhancement-mode devices, and drain to source current of depletion-mode devices as a function of boron doses was reported. It was found that boron implantation under these conditions has no significant effect on the current gain constant k ′, P − N junction leakage current, or threshold stability of MOS devices. Boron implanted MOS capacitors were also studied. The C − V plots on capacitors implanted with moderate doses exhibit parallel shifts to the positive voltage direction, due to the presence of the very shallow non-uniformly doped layer on the silicon surface.

Methods of manufacturing semiconductor devices

Abstract: A method of manufacturing a semiconductor device, in which in a semiconductor body comprising a boundary between a higher doped region and a lower doped region radiation enhanced diffusion of impurity is effected across the boundary from the higher doped region into the lower doped region to form in the lower doped region a further region the lateral extent of which is substantially constant, said radiation enhanced diffusion being effected by directing a beam of energetic particles towards the boundary from the side thereof at which the lower doped region is present and to produce damage of the crystal structure in the lower doped region at least in the vicinity of the boundary, the orientation of the semiconductor body with respect to the incident beam and the energy of the particles being selected so as to produce channelling of the semiconductor body crystal lattice by the particles with a channelling range in the lower doped region which extends at least to the boundary The method may be carried out with proton bombardment and particularly some novel junction field effect transistor structures are formed having channel portions of precisely controlled dimensions The method may be used in the manufacture of a buried channel junction FET having a uniform pinch-off voltage for all parts of the channel Also the method may be used to yield junction FET structures in which the output characteristics can be predetermined according to the cross-sectional shape of the channel region portions determined by the bombardment induced radiation enhanced diffusion with controlled channelling

Field effect transistor structures and methods

Abstract: A field effect transistor is made in a mesa configuration with the top portion of the mesa being the source region and with the limits of the gate electrode being defined by a shadow mask that overhangs part of the mesa. A drift region layer of moderately high resistivity is included between the transistor channel region and the drain region and constitutes the upper wafer substrate surface from which the mesa extends. A thin implanted layer in the upper surface of the drift region layer limits the extent of the channel in the mesa, and a thick oxide over the drift layer reduces the coupling from the gate electrode to the drift region.

Epitaxial outdiffusion technique for integrated bipolar and field effect transistors

Abstract: An NPN transistor, a P channel and an N channel field effect transistor are formed in the same epitaxial layer on a monolithic semiconductor substrate. Subcollector-like areas of one conductivity type are diffused into selected regions of a semiconductor substrate of the opposite conductivity type. Each subcollector-like area comprises two impurities of the same conductivity type but different concentrations and diffusion rates. An epitaxial layer of the same conductivity type as the substrate is grown over the substrate. One of each pair of subcollector impurities outdiffuses completely through the epitaxial layer during the growth of the epitaxial layer and during subsequent heat treatments to define a plurality of isolated pockets of a conductivity type opposite the conductivity type of the surrounding epitaxial layer and substrate. An NPN bipolar transistor and a P channel field effect transistor subsequently are formed in respective isolated pockets. An N channel field effect transistor is formed in the epitaxial layer between the isolated pockets.

Vertical channel junction field-effect transistors and method of manufacture

Abstract: The disclosed junction field-effect transistor (FET) has a precisely controlled gate configuration which enables either high power operation or high frequency operation or both. The FET is manufactured by steps including the growing of a first epitaxial layer having a predetermined crystallographic orientation on a substrate to form a drain. Next, a first anisotropic etch of the epitaxial layer provides "U"-shaped grooves with flat bottoms, therein through which a gate is diffused having internal side walls of uniform depth that define the source-to-drain channel. A second epitaxial layer is then grown on the surface of the first epitaxial layer and of the gate to provide a source. A second anisotropic etch exposes a portion of the gate, which also forms an etch stop, to facilitate electrical contact thereto. Current flowing through the channel is controlled in response to an input signal applied between the gate and source which adjusts the thickness of a depletion region extending into the channel.

Gyrator employing field effect transistors

Abstract: A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180* phase reversal. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central, voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

Subthreshold drain leakage currents in MOS field-effect transistors

Abstract: There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (V tx ) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage V i , the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between V i and V tx the surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below V tx . The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.

Field effect transistor detector amplifier cell and circuit for low level light signals

Abstract: A light sensitive element, typically a phototransistor, diode or the like, is suitably coupled to a load element, typically an FET device suitably biased as a linear load. An output circuit including a high input impedance element, typically an FET inverter, is coupled between the linear load and the diode. Little or no current flows in the input circuit in the absence of light applied to the light sensitive element. When light is applied current flows through the light sensitive element and modulates current flow through the inverter. The output circuit has high sensitivity to low level light signals by reason of the linear load and the absence of "Johnson" or thermal noise. A suitable connection between the light sensitive element and the load element sets the output circuit in a threshold state for immediate response to light signals. Connecting the inverter output to suitable circuitry, i.e., amplifiers, differential amplifiers, level shifters and the like, provides an analog or digital output sensitive to extremely low light levels.

Field effect semiconductor device having an unsaturated triode vacuum tube characteristi

Abstract: A field effect transistor comprises a semiconductor channel, a source and a drain electrode formed at the opposite ends of the channel and a gate electrode provided on the side of the channel. The channel has a small impurity density and therefore the depletion layer extending from the gate goes deep into the channel to substantially close the conductive portion of the channel even in the absence of a gate voltage. The drain current will not flow where the drain voltage is below a certain threshold voltage, and will flow where the drain volage is above the threshold voltage exhibiting a linear resistance characteristic. This drain-current to drain-voltage characteristic simulates the anode-current to anode-voltage characteristic of the triode vacuum tube very closely.

Integrated circuit balanced mixer apparatus

Abstract: Balanced mixer circuit apparatus using two matched integrated circuit field effect transistors as active elements wherein one input signal is applied to the gates of the transistors in pushpull relationship and a second input signal is applied to the substrates of the transistors in a common mode push-push manner. Both input signals thus look into capacitive loads which for practical purposes can be considered to be open circuits, thereby averting any harmonic distortion which might otherwise be produced by loading of the input drive circuits.

Insulated-gate field effect semiconductor device having low and stable gate threshold voltage

Abstract: An insulated-gate field effect transistor includes a gate electrode composed of a tantalum layer and an aluminum layer. An insulating film composed of a tantalum oxide layer and an aluminum oxide layer is disposed about the gate electrode and insulates the gate electrode from the source and drain electrodes. In the fabrication of the device, the aluminum oxide and tantalum oxide layers are formed by anodic oxidation.

Method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors

Abstract: The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the bit lines. In one embodiment, the FET is a load device of the memory cell and has its source electrode connected to one of the bit lines and also to the drain electrode of another FET, which has its gate electrode connected to the other of the bit lines and functions as an active device of the cell. A substantially constant voltage is applied to the gate electrode through one of the bit lines to inactivate the FET which has its drain electrode connected to the source electrode of the FET having its electrical characteristics determined. The other of the bit lines is discharged for a predetermined period of time and then allowed to charge for another predetermined period of time. The measurement of this charged voltage will indicate whether the FET, which is the load device, is connected to the bit line and has the desired gain and whether the leakage current through the bit line is too high. In the other embodiment, a substantially constant voltage is applied to an FET which is the active device and has its drain electrode connected to one of the bit lines to have a substantially constant voltage applied thereto while its gate electrode is connected to the other of the bit lines to have two different voltages applied thereto. The difference in current flow through the active FET having the two different voltages applied to its gate electrode is employed to determine the threshold voltage of the FET.

Method of making insulated gate field effect transistor

Abstract: The present invention relates to an insulated gate field effect transistor and method of making same. An aluminum film is evaporated on a silicon wafer. Portions of the aluminum film are masked. The unmasked portions are anodized. The unanodized portions are removed leaving the anodized insulative portions thereon. Dopant atoms are diffused into areas of the silicon wafer which are not covered by the anodized insulative layer. The anodized insulative layer acts as a diffusion mask, to form source and drain regions in the silicon wafer, and to thus delineate a gate insulator layer between the source and drain regions by the act of diffusion. A second aluminum film is evaporated over the silicon wafer. The portions of the areas of the second aluminum film over the source and drain regions, and the area of the second aluminum film over the aligned gate insulator layer are masked. The unmasked portions of the second aluminum film are anodized to delineate an aligned gate electrode over the aligned gate insulator layer and to delineate source and drain electrodes in contact with the source and drain regions. An insulated gate field effect transistor is thus formed.

A semi-insulated gate gallium-arsenide field-effect transistor

Abstract: Proton bombardment has been used to make a semi-insulated gate gallium-arsenide field-effect transistor. This technique combines the simplicity of the metal semiconductor FET technique, the advantage of operating the device using positive as well as negative bias on the gate, and the possible use of higher conductivity material for the channel, which may result in a higher transconductance and a higher saturated current density.

Substrate bias circuit

Abstract: A semiconductor substrate including a field effect charge pump for injecting charge into the substrate and a field effect transistor circuit, connected between the substrate and a reference voltage source, responsive to the level of substrate charge for clamping the substrate bias voltage at a desired level. By controlling the gate voltage applied to the field effect transistor circuit and the number and arrangement of transistors in the circuit, the substrate bias voltage can be clamped at a value greater than, equal to, or less than the transistor threshold voltage.

Shielded silicon gate complementary MOS integrated circuit

Abstract: An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift in C-V curve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.

Complementary field effect transistors having p doped silicon gates

Abstract: AN INSULATING GATE COMPLEMENTARY FIELD EFFECT TRANSISTOR INTEGRATED CIRCUIT USES SILICON AS THE GATE ELECTRODE. THE GATES OF BOTH N- AND P- CHANNEL TRANSISTORS ARE DOPED WITH P TYPE IMPURITIES, THEREBY BALANCING THE VOLTAGE THRESHOLD CHARACTERISTICS OF THE TRANSISTORS. THE GATE INSULATOR IS DUAL NITRIDE-OXIDE TYPE, WHICH, IN COMBINATION WITH THE P-TYPE GATES, RESULTS IN A HIGH SURFACE-STATE CHARGE DENSITY, AND REQUIRES PARTICULAR DOPING VALUES FOR THE CHANNELS OF THE COMPLEMENTARY TRANSISTORS.

Peripheral circuitry for dynamic mos rams

Abstract: Improved circuits for a dynamic MOS RAM having a storage array of inverting storage cells, including an improved input buffer, an improved write circuit, and a sense circuit. The input buffer circuit includes a dynamic latch circuit clocked by the first clock complement signal and is compatible with TTL logic levels. The cross coupled gate nodes of the dynamic latch are conditionally discharged by circuitry which includes a ratio type first address inverter, and a second ratio type address inverter followed by a third ratioless inverter, whose output conditionally discharges one of the cross coupled gate nodes of the dynamic latch. A separate write circuit drives each digitsense column bus line, and includes a push-pull driver clocked by the third clock input signal. The pull-up and pull-down field effect transistors of the push-pull driver each have an exclusive OR type circuit for conditionally discharging the prepcharged gate electrodes of the pull-up and pull-down field effect transistors, depending on the voltages on the data input signal and the data control signal. The ratioless data control inverter and the data input inverter provide the complement signals required by the two exclusive OR type circuits.

Nonvolatile capacitive memory cell

Abstract: The present invention relates to a nonvolatile capacitive memory cell, which has a capacitive means and a nonvolatile alterable threshold field effect transistor therein. The nonvolatile alterable threshold field effect transistor is used to capacitively store information in said capacitive means while power is applied to the nonvolatile capacitive memory cell. The nonvolatile alterable threshold field effect transistor is also used to nonvolatilely store a binary bit of information which is capacitively stored within the capacitive means, when power is lost to the nonvolatile capacitive memory cell. A pulse from a storage driver connected to the gate electrode of the nonvolatile alterable threshold field effect transistor causes the nonvolatile storage of said binary bit of information. When a binary one bit of information is capacitively stored in the volatile capacitive means, and power is lost, the threshold voltage of the nonvolatile alterable threshold field effect transistor will not be changed, representing the nonvolatile storage of a one bit by said transistor. When a binary zero bit of information is capacitively stored in the volatile capacitive means and power is lost, the threshold voltage of the nonvolatile alterable threshold field effect transistor will be changed, representing the nonvolatile storage of a zero bit by said transistor. A write data circuit is connected to the source electrode of the nonvolatile alterable threshold field effect transistor to capacitively store a binary bit of information into the capacitive means. A preset circuit and a storage circuit are used in nonvolatilely storing the one or zero bit of binary information of the capacitive means into the nonvolatile alterable threshold field effect transistor as power is lost to the nonvolatile capacitive memory cell.

Low power fet driver circuit

Abstract: Disclosed is an FET (field effect transistor) driver circuit capable of driving large capacitive loads, while dissipating relatively little power. A delay circuit forms a parallel path between the circuit input and output providing a delayed signal at the output of the circuit after the gate to source feedback capacitor of the output FET has been charged. The particular delay circuit disclosed herein accurately tracks the driver circuit providing a precise time delay for limiting transient power dissipation in high frequency operation.