Showing papers on "Flip-flop published in 1995"

Method for creating a high speed scan-interconnected set of flip-flop elements in an integrated circuit to enable faster scan-based testing

Abstract: The present invention relates to a method (150) of construction of a scannable integrated circuit. The method includes forming a plurality of flip-flops on an integrated circuit where each flip-flop includes a system data transfer gate and a scan data transfer gate, the gates receiving control signals from a controller (152). A clock signal is routed to the flip-flops (154). Preferably, the flip-flops are placed in a manner to optimize the operation of the integrated circuit when in a system mode. The flip-flops are then coupled into scan chains such that the integrated circuit may operate at a scan mode frequency that is equal to or greater than a system mode frequency (156, 158, 160). An alternative method includes forming a plurality of input lines, a plurality of output lines, and a plurality of scan data paths such that each input line starts a balanced scan chain.

Sample and hold flip-flop for CMOS logic

Abstract: A sample and hold flip-flop that includes a clock buffer circuit responsive to a first clock signal for producing a second clock signal and a third clock signal, wherein the second clock is delayed inverted replica of the first clock and wherein the third clock is a delayed inverted replica of the second clock signal; a CMOS inverter having an input and an output, wherein the output of said CMOS inverter forms the output of the sample and hold flip-flop; a first MOS transistor of a first type having a gate terminal connected to the first clock signal and a drain terminal connected to the input of the CMOS inverter; a second MOS transistor of the first type having a gate terminal connected to the second clock signal and a drain terminal being connected to the source terminal of the first MOS transistor of the first type; a first MOS transistor of a second type having a gate terminal connected to the second clock signal and a drain terminal connected to the input of the CMOS inverter; a second MOS transistor of the second type having a gate terminal connected to the third clock signal and a drain terminal connected to the source terminal of the first MOS transistor of the second type; and wherein the source terminal of the second MOS transistor of the first type and the source terminal of the second MOS transistor of the second type are connected together to form an input of the sample and hold flip-flop.

A novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19-Gb/s decision circuit using a 0.2-/spl mu/m GaAs MESFET

Abstract: This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs Low-power Source-Coupled FET Logic (LSCFL). We reveal the high-speed operation mechanism of the HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series-gated master slave flip-flops and HLO-FF's based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision IC's confirm the accuracy of our analytical method and the high-speed operation of a HLO-FF decision circuit at 19 Gb/s. >

Low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths. Furthermore, a single clock signal is used to enable both master and slave sections. The ability to use a single clock signal without local regeneration coupled with minimizing the number of required components facilitates higher integrated circuit density and reduces power consumption.

Scan flip-flop that holds state during shifting

Abstract: A scan flip-fop is designed to hold the state of the slave latch during scan shifting. This allows an ATPG tool to develop robust delay path tests using combinational scan flip-flop models. Combinational scan flip-flop models suffice because the launch can be done in the cycle before test enable goes active and capture can be performed during the cycle in which test enable is active. Thus, multiple clocks during the capture cycle are not necessary and, therefore, sequential delay path ATPG is not necessary. It is only necessary for the ATPG tool to store the last parallel vector in a buffer. The dynamic latch used for the scan slave latch is made small and slow, thereby increasing the delay along the data path during shifting, making the cell immune to hold time violation for any reasonable amount of clock skew.

High performance energy efficient push pull D flip flop circuits

Abstract: An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ P-type MOSFETs in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.

Static/dynamic flip-flop

Abstract: A storage element responsive to static and dynamic input signals which generates complementary static and dynamic output signals and incorporates scan test logic. The invention includes a first circuit for receiving dynamic and static input signals and providing static output signals in response thereto and a second circuit connected to the first circuit for providing dynamic output signals. In the illustrative embodiment, the first circuit includes a static flip-flop constructed with a multiplexer, a static input (master) latch and a static output (slave) latch. The static input latch provides first and second intermediate complementary outputs on first and second intermediate output terminals respectively. In the illustrative embodiment, the second circuit is an arrangement which includes a first switching element with a first terminal connected to a first node, a control terminal responsive to the first intermediate complementary output signal and a third terminal for providing a third intermediate complementary output signal. The second circuit includes a second switching element having a first terminal connected to the first node, a control terminal responsive to a second complementary input signal and a third terminal for providing a fourth intermediate complementary output signal. The second circuit further includes a third switching element having a first terminal connected to the first node, a second terminal connected to a source of supply and a control terminal connected to a source of a clock signal.

A 40-GHz D-type flip-flop using AlGaAs/GaAs HBT's

Abstract: We report master-slave D-type flip-flop (D-FF) circuit implemented with AlGaAs/GaAs HBT's. The fabricated HBT's had an f/sub T/ of 107 GHz and an f/sub max/ of 110 GHz. To maximize the speed, the logic swing and transistor size in the IC were optimized. In the D-FF, to facilitate the high-speed testing, a selector circuit was integrated on the same chip. As a result, the operation of this IC was confirmed up to 40 GHz, which is the highest speed in D-FF. >

Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuits

Abstract: This paper addresses the problem of testing for delay faults in sequential circuits which incorporate standard scan path design. The technique presented here aims at the reduction or elimination of enhanced-scan flip-flops and their associated overhead. Flip-flop sharing modifies the order of the flip-flops in the scan path such that adjacent flip-flops along the path are from different sequential machines. This allows the application of arbitrary two-vector test sets necessary for delay fault testing. This arrangement is feasible for practical circuits because today's complex ICs consist, in general, of many sequential machines that may need to be delay testable.

Multiplexed by-passable memory devices with increased speed and improved flip-flop utilization

Abstract: A memory device, with increased storage speed and enhanced memory utilization, can be implemented by using multiplex clocking and efficient device design and enhanced flip-flop utilization. Transit time through the circuit, and hence circuit speed, can be controlled through multiplexed clock signals, and is increased by using fewer transistors in the signal path and allowing data to be transmitted directly to the flip-flop output by bypassing the flip-flop's master latch input.

Storage circuit and flip-flop circuit

Abstract: PURPOSE: To provide the storage circuit for which the number of transistors is decreased and power consumption is reduced. CONSTITUTION: At the storage circuit using two inverters, the inverter on the side of a feedback path is composed of plural MOS transistors 2-5 serially connected between a power source and a ground. The MOS transistors 2 and 5 excepting for the MOS transistors to be functioned as inverters in the MOS transistor group are always set in the ON state and functioned, and the load driving ability of those inverters is reduced. COPYRIGHT: (C)1996,JPO

Low power flip-flop

Abstract: A flip-flop circuit which includes a master section (1) having a pair of back to back connected inverters (5, 7) to form a latch circuit with their ground terminals connected together. The clock signal is coupled to the ground terminal of the inverters (5,7) to provide a negative gate to source voltage rather than an essentially zero gate to source voltage as used in prior art inverters to insure full turn off of the inverter transistors (40, 45) during their off periods and conserving power thereby. When the first phase of the clock signal goes high, the signal on the data line is fed to one side of the latch and the other side of the latch is coupled to ground or reference voltage. When the first phase of the clock then goes low, the signal from the data line is latched into the latch of the master section (1) and the other side of that latch is decoupled from ground. Also, when the first phase of the clock signal goes low and the second phase of the clock signal concurrently goes high, the signal latched in the latch of the master section (1) is fed to the slave section (3). The slave section (3) is identical to the master section (1) except that the clock signals received are of opposite phase or state to the clock signals received by the master section (1) and the input to the slave section (3) is the signal latched into the latch of the master section (1). The signal stored in the latch of the slave section (3) is the output of the flip-flop.

Fast-transient susceptibility of a D-type flip-flop

Abstract: Human electrostatic discharge (ESD) produces a transient current pulse with a very fast risetime, which can be a source of electromagnetic interference in digital devices. The focus of this paper is the radiated susceptibility of D-type flip-flops implemented in various CMOS and TTL logic technologies. A transient impulse was used to simulate the radiated field produced during an ESD event. A synchronized-disturbance testing methodology is developed that allows accurate control of the instant at which the disturbing signal is applied to the data input lines during an operational cycle of the circuit. The study reveals that these devices are susceptible only during certain time intervals during an operational cycle. The particular interval during which a flip-flop is susceptible is dependent on the logic state of the data input line, the implementation technology of the flip-flop, and the amplitude of the disturbing signal. The total width of the susceptibility intervals is a device parameter that can be used to determine the probability that the flip-flop will fail in the presence of random transient interference pulses. >

Method and structure for providing a flip flop circuit with a configurable data input path

Abstract: A method and structure for a configurable flip flop circuit. The configurable flip flop circuit includes a flip flop, a first signal line for receiving a first signal, a second signal line for receiving a second signal, a first enable line for receiving a first enable signal, a second enable line for receiving a second enable signal, a programmable logic circuit and a multiplexer circuit. The programmable logic circuit receives the first and second enable signals from the first and second enable lines. In response, the programmable logic circuit generates multiplexer control signals which are provided to the multiplexer circuit. The multiplexer circuit selectably couples the first signal line, the second signal line, and the output terminal of the flip flop to the flip flop input terminal in response to the multiplexer control signals. The programmable logic circuit can be programmed to provide different multiplexer control signals in response to the same first and second enable signals, thereby advantageously allowing the priority of the first and second enable signals to be selected.

D flip-flop having asynchronous data loading

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

Edge triggered set-reset flip-flop (SRFF)

Abstract: A timer comprised of first and second gated SR (set-reset) latches each including two pair (S1, S2 and R1, R2) of inputs and a pair of outputs (Q, QN), the Q output of the first latch being connected to the R2 input of the second latch, and the QN output of the first latch being connected to the S2 input of the second latch, the Q output of the second latch being connected to the S2 input of the first latch, and the QN output of the second latch being connected to the R2 input of the first latch, apparatus for applying a delayed representation of a first pulse signal to the S1 input of the first latch and apparatus for applying a delayed representation of a second pulse signal to the R1 input of the first latch, apparatus for applying an inverted representation of the pulse signal to the S1 input of the second latch and apparatus for applying an inverted representation of the second pulse signal to the R1 input of the second latch, whereby timed output signals representing a differential between leading edges of the first and second pulse signals are provided at the outputs Q, QN of the second latch.

Non-contact ic card and non-contact ic card system

Abstract: PROBLEM TO BE SOLVED: To stably execute the operation of the internal circuits by providing a reset generation circuit in the non-contact IC card operate various internal circuits only when power voltage for an operation in a non-contact card is more than a prescirbed value. SOLUTION: Since the input of a flip flop 45 is almost equal to VDD until time when VDD reaches 5V from the reception start time of a radio wave, a reset being the output is almost equal to VDD and the internal circuits are reset during that period. At time when VDD reaches 5V of the operation voltage of the internal circuits, a regulation circuit 33 operates, the output signal is dropped from 'H' to 'L' and the output of a NAND gate 47 goes to 'H'. The voltage VDD point B is impressed on one input of a NAND gate 46, and the 'H'-level of the output of the NAND gate 47 is impressed on the other input. Thus, the output of the NAND gate 46 becomes 'L', and a reset state is released.

Flip-flop circuit

Abstract: A flip-flop circuit able to commute in correspondence with any logic transition of the input signal (IN) using a flip-flop (N1, N2, N3, N4, INV) and a logic gate (E) of the EXNOR type receiving at its input a signal (IN) and the inverted output of the flip-flop (N1, N2, N3, N4, INV). To the output of the EXNOR gate (E) is connected a set-reset flip-flop (FFSR) which allows a reset to be effected after each commutation of the circuit in order to prepare it for the next transition.

Non volatile programmable flip-flop with predefined initial state, especially for memory redundancy circuit

Abstract: Current can pass from the voltage rail down two parallel paths (T1,T3,TGF1; T2,T4,TGF2). The second path has an extra transistor (T8) in series. in the non- programmed state, the extra transistor pushes the voltage in its path higher. This is reinforced by connections from the transistor grids to the opposite paths. the output logic state output (OUT) thus remains at 1. If the path through the extra transistor is blocked, the transistor connected to the output logic conducts, allowing an upper connection (INV) to the parallel paths to be set to zero. A transistor in the opposite path (TGF1) is then set to non-conducting and the imbalance to the opposite parallel path is reinforced. Thus a two state output is produced, with no permanent current flow in the stable states.

P-type flip-flop

Abstract: A P-type flip-flop, which selectively functions in a D-type flip-flop mode or latch mode depending on its clock signal input The P-type flip-flop has an output changing states to follow its data input at a leading edge of its clock input, the output then does not change states for a period e, and then the output changing states to match its data input after the period e if a signal is received at its clock input having a period greater than e With a pulse applied at the clock input having a width less than e, the P-type flip-flop is edge sensitive functioning similar to a D-type flip-flop With a pulse with longer than e applied to the clock input, the P-type flip-flop appears transparent similar to a latch

Flip-flop circuit

Abstract: PURPOSE: To provide an FF circuit of low power consumption, in which the output timing of output data depends on only the edge of an external input clock, usable under the same timing condition as that of a D-FF circuit and free from influence of hazard. CONSTITUTION: This circuit comprises a short clock generation circuit 105 which generates a short pulse setting the change point of the external input clock as a start point, a delay circuit 104 which delays the output signal of a state monitoring circuit 103 to monitor the coincidence/noncoincidence of input data D and the output data Q, and a clock control circuit 105 which stops/outputs the short clock by a signal delayed by the delay circuit 104. COPYRIGHT: (C)1996,JPO

Scan flip flop circuit

Abstract: PURPOSE:To enable a scan flip flop circuit which can perform tests by a scan testing system to perform scan tests including the delay of functional circuits which are sequential circuits when the flip flop circuit is positioned on the input side of the functional circuits. CONSTITUTION:When scan tests are performed, set scan-in data are outputted by operating a system clock SYS-CLK at an actual operating frequency as a control signal CLK 1 after preventing the output of the scan-in data by cutting off a latch circuit 71 constituting a master-stage cell and another latch circuit 72 constituting a slave-stage cell at the point of time when the scan-in data are set.

Microcomputer with built in serial IO interface for connection to LAN

Abstract: The microcomputer SIO has a counter (1) that receives the clock frequency divided (51a) by a quarter. The counter has a coupled switch module (2) that allows a frequency fixing the data transmission rate to be selected. Coupled to the counter are D type flip flops (3,4,5) and a serial input/output register (7) that responds to a clock signal from a logic gate (6). The register provides the bidirectional conversion of data between parallel and serial forms for transmission via the network. The flip flop stages provide signals to start the cycle and to reset the counter.

Flip-flop circuits for testing LSI gate arrays

Abstract: A flip-flop circuit comprising serially connected flip-flops is associated with a combination circuit and configures a scanning circuit for performing a scanning operation in order to test the combination circuit in a test mode. In performing the scanning operation, the flip-flop circuit is preset or cleared and the preset or cleared data is scanned out through the scanning circuit so that the failure of an asynchronous system input circuit connected to a preset or clear terminal of the flip-flop circuit is detected.

Flip flop circuit and shift register circuit using the circuit

Abstract: PURPOSE:To reduce the number of elements constituting a flip flop (FF) circuit and to reduce its area by constituting the FF circuit only of a slave part of a master-slave type circuit and generating a complementary pulse synchronized with transition timing to a prescribed level of a clock signal to drive the FF circuit CONSTITUTION:An input clock signal CLK is inputted to a 2-input NAND gate 31 in a pulse driver circuit and inputted also to an inverter 32 having a delay function A delay inverse signal Va outputted from an inverter 32 is inputted to the other input of the NAND gate 31, which generates a reverse phase clock pulse phi2 The pulse 2 is inverted by an inverter 33 and outputted as a positive phase clock pulse phi1 The ON/OFF control of transfer gates 21, 24 in the FF circuit is executed by the pulses phi1, phi2 and after latching input data IN by the gate 21, the data are uutputted from the gate 24 Thereby the same function as the master-slave type can be obtained only by the slave part

Input buffer circuit

Abstract: PURPOSE:To provide an input buffer circuit making possible the output of a stable output signal also when noise is incorporated into an input signal. CONSTITUTION:An input buffer circuit is composed of an inversion circuit 6 outputting the signal which has an opposite phase to an input signal Ain based on the input of the input signal Ain and a noninverted circuit 7 outputting the signal in-phase with the input signal Ain. The threshold Vth H of the input circuit 8 of the inversion circuit 6 is made the level which is higher than the threshold Vth L of the input circuit 9 of the noninverted circuit 7, an output signal is outputted from the inversion circuit 6 via a switch circuit 10 to be closed when the input signal Ain becomes the level which is higher than the threshold Vth H, the output signal is outputted from the noninverted circuit 7 via a switch circuit 11 to be closed when the input signal Ain becomes the level which is lower than the threshold Vth H, and the output signals of the inversion circuit 6 and the noninverted circuit 7 are outputted as complementary output signals OUT 1 and OUT 2 via a flip flop circuit 3.

D type flip-flop circuit with hold function

Abstract: PURPOSE:To reduce layout area and power consumption by forcibly interrupting the connection between a 1st D latch circuit and a 2nd latch circuit of the D type flip-flop and using the 2nd D latch circuit to form a holding state. CONSTITUTION:When a low level signal being a signal H is given to a hold control terminal 3, a signal D received from a data input terminal 1 is received by the 1st D latch circuit 10 with a low level signal being a clock signal C received from a clock input terminal 2, transferred to a 2nd D latch circuit 29 by the rising of the signal C and outputted from a data output terminal 4 as an output signal Q. When a high level signal being the signal H is given to the terminal 3, since a dual direction bus gate 6 is conductive independently of the signal C, a feedback loop is produced in the inside of the circuit 20 and reaches a holding state. Since the dual direction bus gate 5 is nonconductive, the circuits 10, 20 are interrupted and data of the circuit 20 are not destructed in the circuit 10.

High performance superconducting digital analogue converter using duplex joining solid flip-flop

Abstract: PURPOSE: To provide asynchronous high speed and low power digital to analog(D /A) conversion by a high performance, supeconducting D/A converter. CONSTITUTION: A D/A converter is provided with a voltage divider 10 made of a double junction superconducting quantum interference device(SQUID) for generating a series of individual binary voltage levels and a voltage selection circuit 12 made of a double junction SQUID for selecting binary voltages in accordance with a digital input. Currents generated by selected binary voltage levels are mutually added to generate an analog output current representing a digital input.

Clock switching circuit

Abstract: PURPOSE:To eliminate a short periodic clock and to eliminate the malfunctions of various kinds of equipments operating by the clock by outputting the clock in a mask state which is held in an H level state over the period which is longer than a clock half period from a selector at the time of the switching operation of the selector. CONSTITUTION:When a mask command signal MSK becomes an H level, the input data of a data input terminal D or a mask command signal MASK is made to be outputted, and the mask control signals M1 and M2 from data and an output terminal Q are made to rise and are made an H level state by the rise timing of the first clocks CLK 1 and CLK 2 after the mask command signal MASK becomes the H level state by D flip flops 17A and 17B, in a control circuit 15. Thus, OR gates 10A and 10B are made a mask operation states and the clock outputs CLK 1M and CLK 2M from these are held in the H level. Namely, the switching completion signal EXCHG of an AND gate 18 is made to rise and a control signal S is made to be outputted from a D flip flop 16 to a selector 3.

D type flip-flop circuit

Abstract: PURPOSE:To attain speeding up by shortening setup time, by constituting an FF by a clocked inverter and eliminating a feedback loop including a transfer gate CONSTITUTION:First and second transfer gates 2 and 3 are opened and closed oppositely with each other according to the 'L' and 'H' of a clock signal CLK, fetches an input data signal D in an FF 10 and transfers the data latched to the FF 10 as an output data signal Q The power supply of the FF 10 is supplied via MOSFET 15 and 16 simultaneously opening and closing according to the clock signal CLK Namely, because the FF 10 operates as a clocked inverter, setup time is short as compared with a feedback loop form including a transfer gate While power supply is turned off, an MOSFET 17 becomes conducting, holds the potential of a node A 10 to VDD/2, for instance, and makes the FF 10 a balanced state Thus, the rising of a circuit in the next operating period is speeded up