Showing papers on "Flip-flop published in 1997"

Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism

Abstract: A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal and a clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-/spl mu/m GaAs MESFETs

Abstract: This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wideband clock buffer is introduced to cover the FF operation range. An 8- to 24-Gb/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed utilizing production-level 0.2-/spl mu/m GaAs MESFET technology.

Edge-triggered staticized dynamic flip-flop with scan circuitry

Abstract: A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is coupled to receive a data signal, a scan input signal, a scan enable signal, a data enable signal and a single-phase clock signal. During the precharge phase, the dynamic input stage provides an output signal that is the complement of the data or the scan signal. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage outputs the complement of the scan input signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

VLSI test circuit apparatus and method

Abstract: An LSSD MUX D flip flop includes a multiplexer, a master latch L1 and a slave latch L2. The inputs to the multiplexer are functional data D, scan data I, and the control is scan enable SE. The L1 master latch receives its input from the output of the multiplexer and is clocked by the NAND of a -FLUSH (-A CLOCK) with an +EdgeClock (-C CLOCK.) The L2 slave latch receives its data input from the output of the L1 master latch and is clocked with the AND of -FREEZE (B CLOCK) and +EdgeClock. The output of the flip flop is the output of the L2 slave latch. This flip flop structure supports edge sensitive, level sensitive, functional, scan, freeze, flush, and test operations.

Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits

Abstract: Several hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic are described. Each circuit configuration includes two registers that surround the Domino logic to allow that logic to be tested. One of the registers receives an input test vector that can either be loaded directly through a primary set of inputs or by a serial scan chain if the inputs to the register are not directly accessible. The second register is used to latch the results of the test vector application. The contents of this register can then either be read directly through a primary set of outputs if there is no static CMOS logic between the outputs of the register and a primary set of outputs of the circuit, or scanned out of the second register using a serial scan chain. A Domino scan flip-flop is also described that produces significant transistor count reduction over conventional static scan flip-flops. These Domino scan flip-flops can be used in the Domino logic as sequential elements to allow a multiplicity of logic functions to be implemented using Domino logic. These scan flip-flops can then be serially connected either as part of a separate scan chain or integrated into a single scan chain with the registers and any other static scan flip-flops in the circuit. These Domino scan flip flops allow all of the nominal logic to be tested in conjunction with the two registers. A relationship between a Domino clock that is used to drive the Domino logic in a system clock that is used to drive the static CMOS logic is described which ensures that a correct test data is applied and read out from the hybrid circuit.

Monolithic CMOS digital integrated circuits in 6H-SiC using an implanted p-well process

Abstract: We report the first p-well Complementary Metal Oxide Semiconductor (CMOS) digital integrated circuits in 6H-SiC. Enhancement mode NMOSFET's and PMOSFET's are fabricated on implanted p-wells and n-type epilayers, respectively. CMOS logic circuits such as inverters, NAND, NOR, XOR, flip-flops, half adders, and 11-stage ring oscillators are implemented using these devices and operated at room temperature, The inverters show stable operation at room temperature and 300/spl deg/C with V/sub dd/=10 and 15 V.

Method of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flop

Abstract: A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the precharge phase in which a dynamic input stage is precharged and a static output stage maintains the output signal from the previous evaluation phase. During the evaluation phase in the normal mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the data signal. During the evaluation phase in the scan mode, the dynamic input stage generates an output signal that either remains at a logic high level or else transitions from high-to-low, complementing the logic level of the scan input signal. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

Flip-flop circuit

Abstract: A clock control circuit is provided in a flip-flop circuit, since a first clock signal supplied to a master latch circuit is generated by an OR logic between a reference clock signal and a skew adjustment clock signal, a second clock signal supplied to a slave latch circuit is generated in accordance with the reference clock signal, the first clock signal has a phase advanced from the second clock signal by exactly an amount of a skew margin. An input signal is fetched into the flip-flop circuit at the rising edge of the first clock signal, then is output at the rising edge of the second clock signal. By this, malfunction due to the clock skew is prevented. The flip-flop circuit can operate as in the normal mode by holding the skew adjustment clock at a logic "0".

Flip-flop with logic function incorporated therein with minimal time penalty

Abstract: A flip-flop circuit for use with logic gates includes a dynamic input stage and a static output stage. The flip-flop receives a single phase which defines a precharge phase and an evaluation phase. The dynamic input stage has a NMOS logic block coupled to receive one or more data signals. The dynamic input stage output signal is precharged to a logic high level during the precharge phase. During the evaluation phase, the NMOS logic block of the dynamic input stage causes the dynamic input stage to generate an output signal that either remains at a logic high level or else transitions from high-to-low by performing a logic operation of the data signals. The static output stage receives the output signal from the dynamic input stage and the clock signal. During the precharge phase, the static output stage maintains the flip-flop output signal logic at the logic level of the previous evaluation phase independently of the signal received from the dynamic input stage. During the evaluation phase, the static output stage outputs the complement of the output signal received from the dynamic input stage.

ATPG for scan chain latches and flip-flops

Abstract: A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. The algorithm is implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at patterns. This shows that this approach is practical for large circuits.

Flip-flop circuit, parallel-serial converting circuit, and latch circuit

Abstract: It is an object to enlarge the logical amplitude of an output signal of a flip-flop circuit with a suppressed, low power-supply voltage to reduce the possibility of occurrence of malfunction. A signal outputted from a differential amplification portion is converted in an internal level converting circuit and fed back to bases of transistors of a slave latch. With input signals having a high level at 0.5 V, the internal level converting circuit performs conversion to provide output signals having a high level at 0.25 V to prevent a current flowing between a collector and a base of the transistors.

A new true-single-phase-clocked double-edge-triggered flip-flop for low-power VLSI designs

Abstract: A new CMOS double-edge-triggered flip-flop (DETFF) utilizing true single phase clocking is proposed as a promising storage element in low-power VLSI designs. Compared to the previously reported DETFF's, both the total transistor count and the number of clocked transistors per flip-flop are reduced to save the power consumption. A clock system is defined in this paper to include a clock generator, clock distribution networks, and clocked flip-flops. Different amounts of power consumption of the different clocking system with different edge-triggered flip-flops are analyzed and compared. It is found that this newly proposed DETFF requires less power in every respect. For example, using the proposed DETFF can save up to 36% of power consumption in the clocking system for a pipelined FIR macro.

High-speed operation of resonant tunnelling flip-flop circuit employing MOBILE (monostable-bistable transition logic element)

Abstract: A new flip-flop circuit employing a monostable-bistable transition logic element is proposed which was fabricated with resonant tunnelling diodes/HEMT integration technology on an InP substrate. Error free operations up to 18 Gbit/s were demonstrated at room temperature.

Method for implementing a single phase edge-triggered dual-rail dynamic flip-flop

Abstract: A method of implementing a single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes receiving a data-input signal and a clock signal. During the precharge phase, an input stage provides an output signal that is the complement of the data input signal. When the data input signal is provided by a dynamic logic gate, the input stage output signal is precharged to a logic high level. During the evaluation phase, an output signal that either remains at a logic high level or else transitions from high-to-low is generated by the input stage. The output signal and the clock signal are received by the precharge stage from the input stage. During the precharge phase, a logic high level output signal is generated the precharge stage independently of the signal received from the input stage. However, the logic high level signal from the input stage turns on hard an n-channel transistor in the precharge stage, which minimizes the delay through the precharge stage during the evaluation phase. During the evaluation phase, the precharge stage outputs the complement of the output signal received from the input stage. The buffer is coupled to receive the output signal from the precharge stage. During both the precharge and evaluation phases, the buffer outputs the complement of the output signal received from the precharge stage.

TRIAC/SCR proportional control circuit

Abstract: A power controller device which uses a voltage-to-frequency converter in conjunction with a zero crossing detector to linearly and proportionally control AC power being supplied to a load. The output of the voltage-to frequency converter controls the "reset" input of a R-S flip flop, while an "0" crossing detector controls the "set" input. The output of the flip flop triggers a monostable multivibrator controlling the SCR or TRIAC firing circuit connected to the load. Logic gates prevent the direct triggering of the multivibrator in the rare instance where the "reset" and "set" inputs of the flip flop are in coincidence. The control circuit can be supplemented with a control loop, providing compensation for line voltage variations.

CMOS flip-flop having non-volatile storage

Abstract: A flip-flop includes non-volatile storage of a bit for encryption purposes or other applications The non-volatile bit remains in the flip-flop, substantially unaltered, irrespective of normal flip-flop operation, and is available to be recalled whenever it is needed The flip-flop is implemented using a pair of CMOS cells Each cell includes a floating gate formed by connecting the gates of an n-mos transistor and a p-mos transistor One of the two floating gates is selectively charged by hot electron injection, thereby raising the threshold of that cell Depending upon which of the two cells is programmed by this process, the flip-flop outputs a logic one or a logic zero during a recall mode

Split-slave dual-path D flip flop

Abstract: A D flip-flop circuit has two current paths supply the output signal of this flip-flop. A push-pull circuit including an inverter and a transmission gate clocked in a first phase supplies the output of the D flip-flop in a first output path. A slave latch connected to the transmission gate having an output clocked in a second phase opposite to the first phase serves as the second path to the output. In one alternative embodiment the master latch includes a transmission gate clocked in the second phase serving as input and a pair of cross coupled inverters serving as latch. The master latch may include a feedback P-type MOSFET. The slave latch may includes two slave latch inverters and a transmission gate clocked in the second phase connected to the output of the D flip-flop output. In a second alternative, an appropriately clocked tri-state inverter replaces the second slave latch inverter and the transmission gate. The master latch and the push-pull circuit may be combined and include two inverters, two transmission gates and a feedback P-type MOSFET. In a third embodiment the push-pull circuit consists of an appropriately clocked tri-state inverter.

Enhanced flip-flop for dynamic circuits

Abstract: A flip-flop with enhanced support for dynamic circuits. The flip-flop comprises at least one data input node along with at least one inverting and at least one non-inverting output node. A clock input node receives an external clock signal and transmits it to a clocking unit which, in turn, generates a clock signal therefrom for gating an input signal received at the data input node. A storage unit holds the input signal value upon assertion of the clock signal and simultaneously transmits that value in appropriate logic level to inverting and non-inverting outputs. It is understood that the inverting and non-inverting outputs represent complementary signal values as is normally known in the art. The flip-flop further comprises a clear input node which is coupled to an edge-sensitive quiescent state control unit. A predetermined logic state transition, i.e. high to low or low to high, of a control signal applied to the clear input node triggers the edge-sensitive quiescent state control unit which, in turn, drives the inverting and non-inverting nodes to an identical logic level, i.e. either quiescent high or quiescent low depending on the design considerations. A non-inverted output signal and/or an inverted output signal at the inverting and non-inverting nodes, respectively, may be used to control the discharge of a node in a dynamic circuit. Since each of the output signals is cleared to a quiescent state after the signal is applied as an input to the dynamic circuit, the output of the flip-flop will not erroneously cause discharge of the node of the dynamic circuit when the next edge of the clock signal occurs.

High speed analog flip-flop with embedded logic and phase-locked-loop circuit employing the same

Abstract: A phase-locked-loop circuit including a prescaler which divides the frequency of an output signal to thereby generate a frequency-divided signal which is provided as a feedback signal to a phase detector of the phase-locked-loop circuit. The prescaler includes a plurality of analog flip-flop circuits serially connected in a chain, with one or more outputs of latter analog flip-flop stages in the chain being fed back to one or more inputs of the first analog flip-flop. Embedded logic is integrated with the differential input pair of the first analog flip-flop to conditionally control the output of the first analog flip-flop based upon the feedback signals from the latter flip-flop stages. The analog flip-flop with embedded logic includes a master section for setting a state of a differential set up signal in response to an occurrence of a first phase of a clock signal. The master section includes a differential pair of transistors coupled to differentially control a flow current through a first and a second load during a second phase of the clock signal. First and second logic circuits are provided in the place of an input differential pair of transistors which control the flow of current through the first and second loads during the first phase of the clock signal. The first logic circuit includes a first transistor and a second transistor each connected to conduct current which flows through the first load. A second logic circuit may be similarly configured with third and fourth transistors which conduct a current which flows through the second load.

Flip-Flop Circuit

Abstract: A master-slave type flip-flop circuit includes a master latch circuit and a slave latch circuit The master latch circuit includes transfer gates (54, 55) for switching between on and off states in response to a clock signal (CK), transfer gates (56, 57) individually connected in series to the transfer gates (54, 55) for switching between on and off states in response to a data signal (D), and a latch section (50) formed from invertors (58, 59) connected to the latter transfer gates (56, 57) The slave latch circuit includes transfer gates (61, 62) for switching between on and off states in response to the clock signal (CK), transfer gates (63, 64) individually connected in series to the transfer gates (61, 62) for switching between on and off states in response to an output and an inverted output of the latch section (50), and a latch section (60) formed from invertors (65, 66) connected to the latter transfer gates (63, 64)

Synthesizable flip-flop based phase-frequency comparator for phase-locked loops

Abstract: A method of performing phase-frequency comparison comprising the steps of receiving first and second clock signals; comparing the signals by triggering flip-flop circuits controlled by AND gates, and providing a first output when first signal is in advance of the second signal, and a second output when second signal is advance of the first signal.

Timed one-shot active termination device

Abstract: A circuit for driving GTL-type buses actively drives a bus trace towards a first reference voltage when a signal in a first voltage state is detected at its input and actively drives the bus trace towards a second reference voltage for a selected period when the signal at its input transitions from the first voltage state to a second voltage state. The circuit includes a flip-flop for storing the sequential voltage states of the signal, logic for comparing the current voltage state of the signal with a replica of the preceding voltage state of the signal, and first and second transistors of complementary conductivity types, for driving the bus trace to first or second reference voltages, respectively, when activated. The first transistor is turned on when the signal is in the first voltage state. The second transistor is turned on for a period determined by the clock signal driving the flip flop, the type of flip-flop, and, optionally, additional logic gates, when the signal transitions from the first voltage state to the second voltage state.

High-speed operation of a resonant tunneling flip-flop circuit employing a MOBILE (monostable-bistable transition logic element)

Abstract: Resonant tunneling (RT) devices attract much attention because of their potential for high-speed operation as well as their high functionality, which leads to lower power dissipation. We have developed a highly functional logic gate, called MOBILE (monostable-bistable transition logic element), which exploits the negative differential resistance (NDR) of the RT phenomenon. In this paper, we demonstrate the high-speed operation-up to 18 Gb/s-of the MOBILE flip-flop (FF) circuit at room temperature. The present result indicates the promise of MOBILE-based FF circuits for high-speed digital applications.

Inspection facilitation design method for route delay fault and inspection system generation method

Abstract: PROBLEM TO BE SOLVED: To provide an inspection facilitation design method for a route delay fault, which can obtain a high fault detection rate without considerably increasing area overhead. SOLUTION: The unprocessed route delay fault which is given in an integrated circuit is selected (S11). An initial pattern is generated for the selected route delay fault (S12), and logic values which are set in respective scan flip flops are stored (S13). A transition pattern is generated for the selected route delay fault (S14). It is judged whether the scan flip flop where the logic value is contradicted between the initial pattern and the transition pattern exists or not (S15). A D latch is inserted into the output signal line of the scan flip flop whose logic value is contradicted (S16). The contradiction of the logic value is dissolved by the D latch and the inspection of the route delay fault becomes easy.

Low voltage ECL latch and flip-flop

Abstract: An ECL latch circuit eliminates a transistor in a latch driver, thereby reducing the operating voltage required for the latch. The latch includes an input circuit having a differential pair of transistors which is coupled directly to a current source. A data latch is coupled to the input circuit, and a latch driver is coupled between the data latch and the current source. The latch circuit is driven with a single-ended clock signal which has a bias level that is higher than the bias level of a pair of complimentary data input signals. This causes the differential pair of transistors in the input circuit to turn off when the latch driver activates the data latch circuit. The data latch includes a differential pair of transistors coupled to latch a pair of complimentary data output signals. The latch driver includes a single transistor coupled to activate the data latch responsive to a single-ended clock signal. An ECL flip-flop circuit utilizes a pair of ECL latches, each of which has a differential pair of transistors which is coupled directly to a current source. The latches are connected in a master-slave configuration with a signal generator disposed between the two latches for generating the data input and clock signals for the slave latch responsive to the data output signals from the master latch.

Clock multiplication circuit and semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To generate a highly precise clock waveform by generating a pulse waveform by using either a rise waveform or the fall waveform in two clock signals outputted from a delay line circuit. SOLUTION: Signals D1-D3 with an equal delay time difference are taken out from an external clock inputted to the delay line circuit 10. The external clock and the signal D1 are inputted to an R S flip flop 21 and the pulse waveform E1 whose period is set to be an 'L' level is generated with the difference of delay time from the rise of the external clock to the rise of the signal D1. The signals D2 and D3 are inputted to an R S flip flop 22 and a pulse waveform E2 is similarly generated. The signals of the pulses E1 and E2 are synthesized in a HAND circuit 30 and a two-fold clock is obtained. Since the waveforms E1 and E2 in the part of the difference of delay time are generated by using only the rise of the waveforms of the external clock signal and the signals D1-D3, the difference does not occur in the pulse width of the waveforms E1 and E2. COPYRIGHT: (C)1998,JPO

Function clock generating circuit, and d flip-flop with enable function and storage circuit using the same

Abstract: PROBLEM TO BE SOLVED: To realize the function clock generating circuit in which a wiring area, a cell area and power consumption are reduced and design of timing is facilitated. SOLUTION: An input terminal D of a through-latch circuit LTC11 is connected to an input line of an enable signal EN, an inverted clock input terminal G is connected to an input line of a clock signal CK and one input terminal of a NAND gate NAND11 connects to an output terminal Q of the through-latch circuit LTC11, the other input terminal is connected to an input terminal of the clock signal CK and the output terminal is connected to an input terminal of an inverter INV11. Then the enable signal EN is sampled in the through-latch circuit LTC11 at a rising point of time of the clock signal CK and a logic gate LGT consisting of the NAND gate NAND11 and the inverter INV11 passes or blocks a clock pulse just after sampling depending on the sampled enable signal EN.

Asynchronous phase detector having a variable dead zone

Abstract: An asynchronous digital phase detector. The digital phase detector includes an asynchronous state machine which simulates an edge triggered J-K flip flop. Additionally, the digital phase detector includes a reset line. The asynchronous state machine is implemented with logic which provides for optimal phase detector sensitivity and minimal dead zone. The logic within the digital phase detector is implemented with pass-transistors. The channel widths of the pass-transistors are selectively widened or narrowed to further increase the sensitivity of the phase detector.

An IDDQ sensor for concurrent timing error detection

Abstract: Error control is a major concern in many computer systems, particularly those deployed in critical applications. Experience shows that most malfunctions are caused by transient faults which often manifest themselves as signal delays or other timing violations. We present a novel CMOS based concurrent error detection circuit that allows a flip flop (or other timing sensitive circuit element) to signal when its data has been potentially corrupted by a timing violation. Our circuit employs on-chip IDDQ evaluation to determine when the input changes in relation to a clock edge. If the input changes too close to clock time, the resulting switching transient current exceeds a reference threshold, and an error is flagged. We have designed, fabricated and evaluated a test chip that shows that such an approach can be used to effectively detect setup and hold time violations in clocked circuit elements.

Flip-flop circuit

Abstract: PROBLEM TO BE SOLVED: To provide various kinds of flip-flop circuits by combining the toggle function of negative differentiation resistor element serial connection circuit to be biased by a constant voltage with the switching function of the same circuit to be biased by an oscillating voltage. SOLUTION: Converning a 1st serial connection circuit 9 for which negative differentiation resistor elements (resonant tunnel transistors, for example), 10 and 12 having almost the same characteristics are serially connected, this circuit defines its serial connection point as an output point and has one element current control terminal 11 at least. Besides, a 2nd serial connection circuit 13 in the same configuration is provided. When the constant voltage higher than the double peak voltage of resonant tunnel transistor is impressed as a bias voltage, a pulse signal is impressed to a terminal 11 or 15, one terminal in bitable state is selected and held and it can be used as a toggle circuit. further, when the oscillating voltage (clock signal) having a waveheight value higher than the double peak voltage is impressed as the bias voltage, the output state can be switched according to the clock signal.