Showing papers on "Flip-flop published in 2022"

Design and simulation of a compact graphene-based plasmonic D flip-flop

Abstract: In this paper, a compact graphene-based plasmonic D flip-flop is presented where the graphene waveguides are sandwiched between two SnO2 layers. The structure includes two input ports CLK and D, and two output ports Q and Q'. The input signals transmit through the waveguides and interfere with other signals. A portion of input signal D appears at port Q, and another portion interferes with the incoming signal from port CLK then is guided toward port Q'. The commercial Lumerical software is used to solve Maxwell’s equations and simulate the propagation of terahertz waves. The finite difference time domain method is used to calculate the electric and magnetic components of waves throughout the structure. The structure is studied at the transverse magnetic mode, and the perfectly matched layer is assumed at boundaries. The wavelength is assumed from 12.7 µm to 13.1 µm, and the area of the structure is 0.83 µm2. The small area of the designed flip-flop is an essential feature for use in optical integrated circuits. The contrast ratio of outputs Q and Q' is about 7.3 dB and 13 dB, respectively which is more than the previous work. In comparison to the last work which had one port for signal Q, two output ports for signals Q and Q' are designed in this work. This feature is needed for employing the flip-flop at sequential circuits.

Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture

Abstract: Phase frequency detector is one of the basic building blocks for Phase Locked Loop (PLL) architecture. The power efficient Delay flip-flop based Phase frequency detector topology is proposed with two parallel clocked latches by following twin latch parallel paradigm method. To construct the latching sections of the circuit, the power reduction techniques such as reducing the numbers of transistors and spilt path technique are incorporated, which leads to reduction of dynamic power and short circuit power consumption respectively. The twin latch paradigm method improves the performance of the system interms of speed due to the sampling of input data at both positive and negative edge arrival of the clock signal. The proposed topology is implemented in MICROWIND EDA tool and evaluated by simulating the circuit under 0.12µm CMOS process technology. The simulation infers that the proposed design achieves power saving from 28.57% to 33.82%, improvement of power energy product ( PEP) from 0.6% to 2.5% and Power area product (PAP) from 10.66% to 12.6% compared to conventional phase frequency detectors.

A Partially Static High Frequency 18T Hybrid Topological Flip-Flop Design for Low Power Application

Abstract: In this brief, an extremely low power true $1-\phi $ clocking flip-flop is proposed using eighteen transistors only. The flip-flop is a synchronous bistable element that stores single-bit information. To design this Master Slave (MS) type architecture, topological, logical, and adaptive coupling techniques are employed. The minimum number of transistors are maintained by using above techniques, which comprises of complementary pass transistor logic and static complementary MOS logic. It also offers low power, a low delay that speeds up the flip-flops, and low complexity by reducing the transistor count. The proposed circuit is implemented using Cadence Virtuoso and compared with the five other reported logic structures of flip-flops. The proposed hybrid logic architecture has showed the highest percentage, i.e., 49.73% improvement in terms of power as compared to LRFF. It also improved the delay and energy efficiency (EDP). The Monte Carlo simulation has been performed for C to Q Delay for 20K samples. By reducing the number of PMOS transistors, the total area of the proposed flip-flop reduces by a minimum of 9.49% in comparison to state of the art work. The proposed circuit can work properly within a frequency range upto 1 GHz. It is also compared with reported 18T TSPC flip-flop.

Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips

Abstract: In this paper, a flip-flop (FF) that minimizes the transition of internal nodes by using a dual change-sensing scheme is discussed. Further, in order to reduce power consumption, a new technique to eliminate short-circuit currents is described. The proposed dual change-sensing FF (DCSFF) composed of 24T (T: number of transistors) has the lowest dynamic power consumption among conventional FFs, independent of the data activity ratio. According to the measured results with a 65 nm CMOS process, the power consumption of DCSFF is reduced by 98% and 32%, when the data activity is close to 0% and 100%, respectively, compared to that of conventional transmission gate FF. Further, compared to that of change-sensing FF, the power consumption of DCSFF is reduced by 26% when the data activity is close to 100%.

QCA-Based PIPO and SIPO Shift Registers Using Cost-Optimized and Energy-Efficient D Flip Flop

Abstract: With the growing use of quantum-dot cellular automata (QCA) nanotechnology, digital circuits designed at the Nanoscale have a number of advantages over CMOS devices, including the lower utilization of power, increased processing speed of the circuit, and higher density. There are several flip flop designs proposed in the literature with their realization in the QCA technology. However, the majority of these designs suffer from large cell counts, large area utilization, and latency, which leads to the high cost of the circuits. To address this, this work performed a literature survey of the D flip flop (DFF) designs and complex sequential circuits that can be designed from it. A new design of D flip flop was proposed in this work and to assess the performance of the proposed QCA design, an in-depth comparison with existing designs was performed. Further, sequential circuits such as parallel-in-parallel-out (PIPO) and serial-in-parallel-out (SIPO) shift registers were designed using the flip flop design that was put forward. A comprehensive evaluation of the energy dissipation of all presented fundamental flip-flop circuits and other sequential circuits was also performed using the QCAPro tool, and their energy dissipation maps were also obtained. The suggested designs showed lower power dissipation and were cost-efficient, making them suitable for designing higher-power circuits.

Simulation of Low-Power Shift Registers Using the MTCMOS Method with a Wide Selection of Transistors

Abstract: The method of huge integrating involves implementing a significant transistor count in an extremely condensed space. Combinatorial logic has shown to be particularly effective in quantum computing as well as other designing applications. In VLSI design, the primary goal is to cut down on power consumption as well as latency. For the purpose of establishing technology and supporting the increased use of electrical machines, it is vital to decrease sub-threshold current flowing for large strains. This research explores the feasibility of implementing a shift register and without the Multi-threshold CMOS (MTCMOS) approach. At the process technology of 0.18 µm, 0.12 µm, and 90 nm, an investigation into the power loss and transmission delay characteristics of a variety of flip-flops is carried out. As technology gets shrunk, the amount of power lost through leakage rises. Using the greatest technique among all run time strategies, namely MTCMOS, helps to limit the amount of power lost due to leakage. The purpose of this article is to give a comparison between various traditional flip-flops and the TSPC flip-flop with regard to power usage, diffusion delays, product of delay-power (PDP), area, and power flow using the findings obtained from the Microwind simulator.

An Efficient Design of D Flip Flop in Quantum-Dot Cellular Automata (QCA) for Sequential Circuits

Abstract: Quantum cellular automata (QCA) is the most recent creating innovation for rapid, low power computation architectural technique in the field of new-age nanoelectronics that restructures the logical information as charge structures of as a Quantum cell which was firstly suggested by Lent et al. [1]. The Quantum-Dot cellular automata are an alternative for conventional CMOS technology to implement classic cellular automata with quantum dots. The use of quantum cell automata is an innovation as an option to CMOS technology on the nanoscale has a promising future as its integration with various digital circuits in a precisely low powered device. This chapter analyzes the QCA based flip-flops and proposed novel layouts of shift register and ring counter with less QCA cells and better performance parameters. The SISO shift register and ring counter is structured using a D flip flop which is redesigned using 38 cells, show 42% less complexity than previous structures.

A Soft Error Detection and Recovery Flip-Flop for Aggressive Designs With High-Performance

Abstract: Soft errors induced by Single Event Transient (SET) or Single Event Upset (SEU) are a great threat to integrated circuits. To reduce the error rate and improve the reliability of the circuits, we proposed a radiation hardened flip-flop in this paper, namely, Soft Error Detection and Recovery flip-flop (SEDR-FF). Error detection is based on delayed sampling and redundant storage by a redundant latch. A pulsed clock is adopted to control the redundant latch to reduce the hold time constraint of the latch. To generate the pulsed clock, two efficient delay elements are presented in this paper. Error recovery is accomplished by reloading the previous data stored in a history latch. Transistor-level simulations and timing-annotated gate-level simulations under 65 nm technology show that the proposed flip-flop can efficiently detect and correct the soft errors caused by SET or SEU. It has low overhead of setup time, and is suitable for high-performance designs. In addition, compared with other radiation hardened cells, the proposed flip-flop has moderate power and area overhead, and has lower area cost for fixing hold time violations in circuits designs.

Competing Ferroelectric Polarization: Hydroxyl Flip-Flop versus Proton-Transfer Mechanisms

Abstract: Ferroelectricity above room temperature and a theoretical simulation of the spontaneous polarization are reported for a polar polymorph of 2,5-dihydroxybenzoic acid. The planar zigzag hydrogen-bonded chain of hydroxy groups geometrically...

Design and Analysis of Low-Power High Performance 4-Bit Parallel Shift Register using Retentive True Single Phase Clocked D-Flip Flop

Abstract: With increase in internet enabled smart systems, circuit miniaturization and low-operating power levels are given much priority in designing next-generation integrated circuits. Shift registers are commonly used electronic devices for data storage and transmission. The performance of a shift register depends on its internal circuitry that include type of technological node, design architecture and operating power levels. The present study focuses on the design and development of 4-bit parallel in parallel out (PIPO) shift register using retentive true single phase clocked (TSPC) D flip-flop. The manuscript initially demonstrates the performance of retentive true single phase clocked D flip-flop, that makes up the proposed 4-bit PIPO shift register using 16nm technological node yielding a minimum power consumption level 0.75μW at an operational voltage of 0.8V. The power consumption of the individual TSPC D flip-flop is analyzed by varying operating voltages from 0.7V to 1.2V and its results are presented. Lastly, the 4-bit PIPO shift register is designed using TSPC flip-flop and its operation and performance is discussed. The designed 4-bit PIPO shift register can be operated below 1V operating voltage to yield minimal power consumption of around 2μW. The proposed 4-bit PIPO shift register can be possibly implemented in low power energy-efficient data handling electronic devices, which has the true potential to match current industry needs.

Design of Light-Weight Timing Error Detection and Correction Circuits for Energy-Efficient Near-Threshold Voltage Operation

Abstract: Near-threshold voltage (NTV) operation has the potential to improve the energy efficiency of digital integrated circuits. However, the use of a conservative timing guard band to avoid the timing errors introduces excessive timing margins, thus causing larger energy dissipation in the NTV region. An error-tolerant design based on timing error detection and correction circuits has been shown to be a promising solution to mitigate these issues. This paper presents a light-weight timing error-tolerant flip-flop (ETFF) design. This design detects timing errors using a node transition signal detector with only nine transistors and corrects these errors during the same clock cycle. Moreover, transistor sizing is explored to optimize the trade-off between performance and area overhead. The proposed ETFFs are inserted into a monitored circuit by replacing original flip-flops at timing-monitored points. To further reduce the overhead, we develop a mean-time-to-failure-aware method to select the monitored points by simultaneously considering the critical path coverage and activation rates of flip-flops. The simulation results show that a CNN accelerator using the proposed timing error-tolerant design implemented in the SMIC CMOS 40 nm process can robustly work at 1.1–0.3 V with only 3.5% area overhead. Furthermore, this design reduces the area overhead by 54.68% and improves the energy efficiency by 53.69% at 0.6 V, compared with the Razor flip-flop design. The advantage of the proposed design lies in that it requires smaller circuit overheads and can work reliably in a wider range of supply voltages.

Simulation-Based Recommendations for Digital Circuits Design Using Schottky-Barrier-Type GNRFET

Abstract: The use of graphene nano-ribbon field-effect transistors (GNRFETs) in the nanoscale circuits design is challenging because there are several adjustable parameters that need to be selected carefully. In this paper, we evaluate the impact of changes in different GNRFETs’ parameters including channel length (Lch), oxide thickness (Tox), line-edge roughness (Pr), number of dimer lines (N), supply voltage, and temperature on the performance of inverter, Flip-Flop, and SRAM circuits. Performance analysis in terms of noise margin (NM), delay, average power, and energy-delay-product (EDP) show that those adjustable parameters of the GNRFETs are of a significant role in attaining low-power or high-performance requirements. To achieve low-power designs, GNRFETs with perfectly smooth edges and higher Tox should be used. For low-power designs with a smaller oxide thickness, it is suggested to select 9 for N with very low Pr. Otherwise, the priority would be choosing 13 for N. To attain high-performance designs with low delay, it is recommended to use the GNRFETs without Pr. If the edges of graphene nano-ribbons are not smooth, choosing (3p+1, p ∈ ℕ ) periodic for N provides a potential improvement in circuit delay. Moreover, selecting 18 for N and smaller Tox provides a potential improvement in circuit delay.

Performance Optimization of LG = 16 nm Pulse Triggered Low Power High Speed Data Flip-Flops At Higher Temperatures With a VDD of 0.7 V

Abstract: In this work, we optimized the Delay & power performance of pulse-triggered (PT) Data (D)-flip-flops (ep-DCO, MHLFF, static CDFF, PFF & CDFF) using SPICE simulations. The flip-flops were optimized for an ultra low VDD of 0.7 V in 16 nm CMOS. The temperature effects on the Data to Q propagation delay & consumption of power of pulse triggered flip-flops have also been investigated by sweeping the temperature from 303K to 383 K with a step increment of 10K. The SPICE simulations results obtained using a VDD of 0.7 V & 16 nm CMOS process points out that PFF with a propagation delay (Data to Q delay) of 11.09 pS (13.22 pS) at 303K (383K) respectively that outperforms other PT-data flip-flops like ep-DCO, MHLFF, static CDFF, & CDFF flip-flops have been considered as key circuits in micro processors, registers & other synchronous VLSI chips.

Implementation of Fundamental Modules Using Quantum Dot Cellular Automata

Abstract: This paper aims to design logic gates and flip flops using QCA. This paper demonstrates the implementation of logic gates. (AND GATE, OR GATE, NOR GATE, NOT GATE, EXORGATE, X-NOR GATE, NAND GATE) and flip flops (SR flip flop, JK flip flop, D flip flop and T flip flop) using QCA designer tool software. Using QCA, we can reduce power dissipation, increase the speed of operation, and decrease area size. QCA is known as Quantum Dot Cellular Automata, and it is a transistor less model. We don’t need transistors, resistors& capacitors to build or design any logic gates and flip flops. QCA is a square shape nano-structure that can perform computations. Instead of transferring information through current and voltage, it transfers the information in the form of polarization. The QCA cell basic structure consists of four quantum dots and two electrons. These two electrons can occupy any of the four quantum dots and tunnel between them but can’t come out due to high barrier potential

Designing a D-Flipflop Using Novel Sleep Transistor Technique

Abstract: D-Flipflops are widely used in designing various analogue, digital and mixed signals. Different shift registers, counters and other circuits are designed using D-Flipflop. To increase the battery life time and reduce the power consumption, the voltage given to the circuit have to be decreased in the Standby mode of operation. In this paper different D Flipflops are designed using techniques like 5 transistor D-Flip Flop, Self-voltage level D-Flipflop and modified SVL (Self Voltage Level) D-Flipflop and Novel sleep transistor technique. Comparisons are made between all the designs in terms of power, delay and leakage power. All the designs are designed and simulated with the help of Cadence Virtuoso in 90nm technology. The leakage power observed in Novel Sleep Transistor technique is 93.5% less than that observed in Modified SVL Technique.

Asynchronous Counter in QCA Technology Using Novel D Flip-Flop

Abstract: Abstract A strong need for high-speed and low-power consumption devices seems inevitable due to the high speed of technological advancement in the field of microelectronics. Designers are highly interested in designing and making nanoscale devices. The Quantum Cellular Automaton (QCA) is known as one of these technologies, which makes it feasible to implement digital circuits with a high operating speed. In this paper a 4-bits counter, a 3-bits bidirectional counter, a 4-bits counter with a reset terminal, and a 4-bit counter with both set and reset terminals are designed using the proposed D-latch to demonstrate that these circuits function accurately in more complex circuits. According to the results, the area was respectively reduced by 8.33% and 15.38% with a 4.76% reduction in the delay rate in the proposed 4-bits counter and 3-bits bidirectional counter compared to the best previous designs. All the designs and simulation results is being done in the QCAPro and QCADesigner software.

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace Applications

Abstract: In space, the impact of radiative particles, such as neutrons and heavy ions, can change the node states of a flip-flop, thus resulting in loss of data. In this paper, a Highly reliable and Low power Radiation-hardened-by-design (RHBD) Flip-Flop cell, namely HLRFF, completely hardened against double-node-upsets (DNUs), is proposed for aerospace applications. The HLRFF is a master-slave structure. The master latch is mainly constructed from two 2-input C-elements (CEs) and one 2-input clock-gating based CE, while the slave latch has an additional keeper at the output stage. The verification results demonstrate that the proposed HLRFF is completely DNU-tolerant. Furthermore, compared to the state-of-the-art radiation-hardened FF cells, the proposed HLRFF can reduce power consumption by approximately 69%. However, only the proposed HLRFF is not only completely DNU-tolerant but also insensitive to high-impedance-state.

A Bypassable Scan Flip-flop for Low Power Testing with Data Retention Capability

Abstract: The power consumption of modern highly complex chips during scan test is significantly higher than the power consumed during functional mode. This leads to substantial heat dissipation, excessive IR drop, and unrealistic timing failures of the integrated circuits (ICs) under test. In this brief, a ByPassable Scan Data Retention Flip-Flop (BPS-DRFF) is proposed for low-power IC test. The proposed flip-flop contains two secondary latches. The output of the “function” secondary latch goes to the following combinational circuits, while the other “shadow” secondary latch is used to shift test vectors during scan test. By gating the output of the function secondary latch, the redundant switching activity in the combinational circuits is eliminated during scan shift, thereby reducing the test power consumption significantly. The suppressed switching activity also leads to lower IR drop across the chip, increasing the chip manufacturing yield. Furthermore, the shadow latch is reused for data retention in the sleep mode while performing power gating, thereby alleviating the area cost of the shadow latch. The proposed BPS-DRFF also eases the hold time sign-off in the test mode due to the elongated clock-to-Q contamination delay that is brought in by the shadow latch. The proposed design is applied to an AES-128 crypto core in a UMC 55-nm low power CMOS technology. Experiment results show that 68.5% power is saved during scan test with the proposed BPS-DRFF, compared to the standard scan retention flip-flop.

Design and Analysis of New Ultra Low Power CMOS Based Flip-Flop Approaches

Abstract: The flip flops are essential part of the clocking circuits in complementary metal oxide semiconductor circuit based designs. The adiabatic flip flops are more useful in digital systems for clock switching applications. The clock switching approach with energy restoration is most popular and prominent for reducing power dissipation in ultra-low power based digital system designs. These flip flops playing key role in the design of energy efficient adiabatic clock switching methods and these flip flops works on the basis of adiabatic principle. In this research paper, we have simulated and analyzed the behavior of energy restoration flip flops. These are observed as one end condition capture and differential condition capture flip flops. Both the flip- flops are more useful in energy recovery methods. For better enhance results, we can use clock gate switching method together with energy restoration method. These are verified using cadence 180, 90 nm library technologies. Finally, we obtained desired results after simulation.

Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations

Abstract: Recently, Internet of Things (IoT) are spread out in many fields. Some applications for an IoT request intermittent operations to extend their battery life. In this paper, we present a nonvolatile flip-flop (NV-FF) using FiCC (Fishbone-in-Cage Capacitor) suitable for IoT processors with intermittent operations. The NV-FF was fabricated in a 180 nm CMOS process technology. The area overhead caused by nonvolatility of the flip-flop is 29%. We confirmed that NV-FF is fully working at 65 MHz. The data retention time was approximately 155 minutes when the write time to the nonvolatile memory was 0.1 sec. and the reading voltage was set to 1.4 V. The simulation results indicate that the nonvolatile register file composed of the NV-FFs can reduce the energy consumption by 80.31% compared with a conventional register file when it operates 35 sec. per hour and hybernates in the remaining time.

Analysis of the Effect of Red LED and Infrared Flip Flop Frequency on SpO2 Measurement Accuracy

Abstract: Oxygen saturation is a vital parameter for the early detection of advanced oxygen deficiency. Spo2 is a tool that measures the amount of oxygen in the blood non-invasively. This equipment consists of ophotodiodeiode as a sensor as well as red and infrared LEDs with a flip flop driver circuit that has a certain frequency. In this case, several research projects and equipment on the market have various flip flop frequencies. This research aims to find the best frequency setting value for red and infrared led drivers on SpO2 devices. In this research, a SpO2 that can be adjusted with a flip flop frequency of 400 Hz to 1400 Hz was designed. The SPO2 reading from the sensor is presented on the OLED LCD panel using Arduino Mega as a data processor from the driver frequency output controller. Frequency adjustment for sensor drivers is also at 400 Hz to 1400 Hz. This tool was further used to measure the frequency variation of the flip flop. The measurement results on the subject's finger were then compared with the results of the standard SpO2 tool to see the effect of the frequency value on the level of accuracy of the tool. The results of the comparison data processing showed that the largest error of 0.35% occurred in the SPO2 measurement using the 600 Hz sensor frequency driver, and the smallest error value of 0.07%, occurred in the use of the driver frequency at 1400Hz. These results can be used in the initial design of the production of SpO2 equipment, the higher the frequency, the more accurate it will be. This study only discusses the frequency, whereas the intensity parameters of the red and infrared LEDs also vary. In future research, it would be better to involve the LED light intensity parameter to determine its effect on the accuracy of the tool.

High performance d flip flop based on gnrfet

Abstract: In Digital Electronic, As we know the most widely used flip flop is D flip flop which is an edgetriggered device that allows the transfers input data from Q on clock rising or falling edge. Its widely used for storage and circuits registers. For making it effectively use we always make some improvements in a better performance like Power characteristics and energy dissipation, gate leakage. Researchers have developed various types of models of static and dynamic D flip flops with various changes in their efficiency and powersaving but still, we have various ways to implement it and making it effectively useful. So I try to implement it by using Graphene Nano Ribbon Field Effect Transistor (GNRFET) in 22nm technology length of the channel with a concept of power getting for saving energy from being dissipated unnecessarily. The proposed circuit according to the simulation results in HPSICE software is proved to be better in terms of Average power, propagation time delay, Energy Dissipation. Also, voltage source power dissipation is nearly the same in GNRFETs configuration and much better in case of comparison with the bulk CMOS MOSFET counterpart. That is shown by Graphical representation in this paper. GNRFET with power gating proved as the promising substitute under the 22nm category of channel length technology.

Design of Low-power Quad-edge-triggered Flip-flop at Switch Level

Abstract: This paper presents a novel approach to design quad-edge-triggered flip-flop (QETFF) based on ternary clock. At first, the previous QETFF consisting of 3-to-1 multiplexers is reviewed and analyzed; the property of ternary clock is pointed out. By using it, a novel multiplexer is proposed, following which a novel design of QETFF named after uQETFF is proposed, of which the circuit is simpler than the previous one, saving 8 transistors. Then, HSPICE simulations with TSMC 180 nm CMOS technology are carried out on the proposed uQETFFs, their ideal logic functionality being shown. At last, performance comparisons between the proposed uQETFFs and its equivalent flip-flops are made. From the comparisons, it can be seen that the proposed binary uQETFF consumes 13.6% less energy than the equivalent double-edge-triggered flip-flop (DETFF) based on binary clock; the proposed ternary uQETFF optimizes the overall circuit performance with a reduction of 43.5% in PDP (power-delay product) compared to the previous ternary QETFF. Therefore, the proposed uQETFFs are simpler and their characteristics are more desirable, which are more close to the requirements of the practical applications.

Implementation of Low-Power Frequency Divider Circuit using GDI Technique

Abstract: Downsizing breakthroughs and improved VLSI circuit operating rates in the electronic sector is the need of the time. Dynamic power consumption in the micro-scale range is an important issue. In this paper, a sophisticated method based on the single edge triggered flip flop approach is developed and assessed. A frequency divider circuit is designed using positive edge triggered D flip flop where master slave approach is induced. Implementation is executed on 90nm technology with the help of CADENCE virtuoso 16.1 gpdk library. After simulation, the performance parameters like power consumption, propagation delay, rise time, and fall time are 1.972 μW, 375.5 ps, 106.3 ps, and 106.3 ps, respectively. Comparative analysis of power consumption reduction is also done and it has been found that the proposed circuit achieves a handsome amount of power reduction in comparison to the already reported circuits.