Showing papers on "Hardware Trojan published in 2023"

Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study

Abstract: With the exponential increase in the popularity of the RISC-V ecosystem, the security of this platform must be re-evaluated especially for mission-critical and IoT devices. Besides, the insertion of a Hardware Trojan (HT) into a chip after the in-house mask design is outsourced to a chip manufacturer abroad for fabrication is a significant source of concern. Though abundant HT detection methods have been in-vestigated based on side-channel analysis, physical measurements, and functional testing to overcome this problem, there exists stealthy HTs that can hide from detection. This is due to the small overhead of such HTs compared to the whole circuit. In this work, we propose several novel HTs that can be placed into a RISC-V core's post-layout in an untrusted manufacturing environment. Next, we propose a non-invasive analytical method based on contactless optical probing to detect any stealthy HTs. Finally, we propose an open-source library of HTs that can be used to be placed into a processor unit in the post-layout phase. All the designs in this work are done using a commercial 28nm technology.

Circuit Topology-aware Vaccination-based Hardware Trojan Detection

Abstract: Hardware Trojans pose a critical security threat to modern integrated circuits (ICs) through malicious activities, including leaking critical information, executing unauthorized commands, and reducing IC lifetime. Traditional functional and structural verification approaches are inefficient in detecting stealthy Trojans effectively due to corner conditions and rare triggers. Furthermore, the existing approaches are limited to specific circuit designs and require formulating new models for other IC designs. In order to overcome such shortcomings, we introduce an IC topology and behavior-aware hardware Trojan (HT) detection approach, where we extract different structural features of the underlying IC along with the behavioral information for HT detection. Structural features include node (gate) types and their respective counts and connectivity information extracted through an automated process using graph learning. These features are complemented with the behavioral information such as operating frequency and bit-flip patterns under anomalous operating conditions (analogous to vaccination) and analyzed for Trojan detection. We propose a Graph Neural Network (GNN) architecture where we utilize a Graph Convolution Network (GCN) for detecting Hardware Trojans. The proposed technique does not require the golden IC reference design for HT detection. Our model shows an average of around 93.15% accuracy while tested on an utterly unseen Trojan benchmark during the training phase. This shows that the proposed technique can learn the structural feature distribution of the ICs and their behavioral information to distinguish Trojan-free and Trojan-inserted circuits irrespective of the IC topology used in the training phase.

Hardware Trojan Detection Using Machine Learning: A Tutorial

Abstract: With the growth and globalization of IC design and development, there is an increase in the number of Designers and Design houses. As setting up a fabrication facility may easily cost upwards of $20 billion, costs for advanced nodes may be even greater. IC design houses that cannot produce their chips in-house have no option but to use external foundries that are often in other countries. Establishing trust with these external foundries can be a challenge, and these foundries are assumed to be untrusted. The use of these untrusted foundries in the global semiconductor supply chain has raised concerns about the security of the fabricated ICs targeted for sensitive applications. One of these security threats is the adversarial infestation of fabricated ICs with a Hardware Trojan (HT). An HT can be broadly described as a malicious modification to a circuit to control, modify, disable, or monitor its logic. Conventional VLSI manufacturing tests and verification methods fail to detect HT due to the different and un-modeled nature of these malicious modifications. Current state-of-the-art HT detection methods utilize statistical analysis of various side-channel information collected from ICs, such as power analysis, power supply transient analysis, regional supply current analysis, temperature analysis, wireless transmission power analysis, and delay analysis. To detect HTs, most methods require a Trojan-free reference golden IC. A signature from these golden ICs is extracted and used to detect ICs with HTs. However, access to a golden IC is not always feasible. Thus, a mechanism for HT detection is sought that does not require the golden IC. Machine Learning (ML) approaches have emerged to be extremely useful in helping eliminate the need for a golden IC. Recent works on utilizing ML for HT detection have been shown to be promising in achieving this goal. Thus, in this tutorial, we will explain utilizing ML as a solution to the challenge of HT detection. Additionally, we will describe the Electronic Design Automation (EDA) tool flow for automating ML-assisted HT detection. Moreover, to further discuss the benefits of ML-assisted HT detection solutions, we will demonstrate a Neural Network (NN)-assisted timing profiling method for HT detection. Finally, we will discuss the shortcomings and open challenges of ML-assisted HT detection methods.

Importance of Logic Locking Attacks in Hardware Security

Abstract: A rise in the number and devastating capability of hardware-based assaults has brought attention to the necessity of protecting the hardware root of trust alongside improvements in power, cost, performance, and reliability. The whole design of an integrated circuit can be concealed from a suspect foundry or end- user via a key-based circuit obfuscation or logic-locking approach. The method is based on introducing "key" input bits into the circuit to introduce ambiguity within the original circuit, rendering the circuit unreadable without the proper secret key. The present level of knowledge in this developing area is reviewed in this study, which also includes a threat model classification such as hardware Trojans, re verse engineering (RE) and side channel analysis. Moreover, the traditional and strong logic locking techniques and its efficiency in terms of area, power, delay is reviewed in hardware-based attacks.

Static Probability Analysis Guided RTL Hardware Trojan Test Generation

Abstract: Directed test generation is an effective method to detect potential hardware Trojan (HT) in RTL. While the existing works are able to activate hard-to-cover Trojans by covering security targets, the effectiveness and efficiency of identifying the targets to cover are ignored. We propose a static probability analysis method for identifying the hard-to-active data channel targets and generating the corresponding assertions for the HT test generation. Our method could generate test vectors to trigger Trojans from Trust-hub, DeTrust, and OpenCores in 1 minute and get 104.33X time improvement on average compared with the existing method.

Hardware Trojan Detection Method Based on Dual Discriminator Assisted Conditional Generation Adversarial Network

Abstract: Abstract Hardware Trojans are usually implanted by making malicious changes to a chip circuit, which can destroy chip functions or expose sensitive information once activated. The hardware Trojan detection method based on side channel information has now become one of the most widely used detection methods. However, due to the influence of the deviation of the acquisition equipment and the noise of the actual chip working environment, insufficient acquisition of useful information of the collected side channel information occurs, affecting the final results. To address the problem, this paper proposes a detection method based on a dual discriminator assisted conditional generation adversarial network (D2ACGAN), which combines the benefits of CGAN, ACGAN, and D2GAN models and can learn a variety of valid information of the tested chip. It can distinguish between side channel data with and without hardware Trojan and classify hardware Trojan using the extended data. Furthermore, to compare the performance of the proposed model, we use the existing CGAN and ACGAN models equally for side channel information expansion and hardware Trojan detection. Finally, the designed hardware Trojan is implanted in an encryption chip for generating data quality evaluation experiments and model method performance experiments. The results show that the average detection accuracy of the D2ACGAN-based hardware Trojan classification model can reach 97.08%, which is better than the detection models based on CNN, SVM, etc. The D2ACGAN model also outperforms the CGAN and ACGAN models in terms of generated data and hardware Trojan classification.

A Framework for Automated Exploration of Trojan Attack Space in FPGA Netlists

Abstract: Field Programmable Gate Arrays (FPGAs) provide a flexible compute platform for quick prototyping or hardware acceleration in diverse application domains. However, similar to the global semiconductor life-cycle in the modern supply chain, FPGA-based product development includes processes and interactions with potentially untrusted parties outside the traditional scrutiny of a completely in-house development cycle. An untrusted party or software can maliciously alter a hardware intellectual property (IP) block mapped to an FPGA device during various stages of the FPGA life-cycle. Such malicious alterations, also known as hardware Trojan attacks, have garnered significant research into their detection and prevention in the context of application-specific integrated circuit (ASIC) design flow. However, Trojan attacks in FPGAs have not enjoyed this same attention. Designers often rely on mapping ASIC-specific solutions and evaluation benchmarks to the FPGA domain, which leaves much of the FPGA-specific Trojan space uncovered. We note that the distinctive business model as well as the architectural configurations of FPGAs present unique opportunities for Trojan attacks to an adversary. To this end, we introduce a framework to automatically explore the hardware Trojan attack space in FPGA netlists. It is capable of inserting different types of FPGA-specific Trojans in a netlist enabling rapid exploration of potential Trojan attacks in an FPGA design: soft-template, monolithic, and distributed dark silicon. Soft template Trojans use behavioral templates with random synthesis constraints to increase Trojan structural diversity. Monolithic and distributed dark silicon Trojans use the under-utilized input space (FPGA dark silicon) in FPGA primitives to realize Trojans with effectively zero area and power footprint. Further optimizations are also presented to remove any potential delay impact. We then generate over 1300 Trojan-inserted benchmarks using each of the introduced FPGA Trojan classes, and compare their impact on utilization, delay, and power. Finally, we evaluate our Trojans against a machine learning-based Trojan detection to highlight their evasiveness.

Hardware Trojans in Power Conversion Circuits

Abstract: This report investigates the potential impact of a Trojan attack on power conversion circuits, specifically a switching signal attack designed to trigger a locking of the pulse width modulation (PWM) signal that goes to a power field-effect transistor (FET). The first simulation shows that this type of attack can cause severe overvoltage, potentially leading to functional failure. The report proposes a solution using a large bypass capacitor to force signal parity, effectively negating the Trojan circuit. The simulation results demonstrate that the proposed solution can effectively thwart the Trojan attack. However, several caveats must be considered, such as the size of the capacitor, possible current leakage, and the possibility that the solution can be circumvented by an adversary with knowledge of the protection strategy. Overall, the findings suggest that proper protection mechanisms, such as the proposed signal-parity solution, must be considered when designing power conversion circuits to mitigate the risk of Trojan attacks.

A Unioned Graph Neural Network Based Hardware Trojan Node Detection

Abstract: The globalization of the integrated circuit (IC) industry has raised concerns about hardware Trojans (HT), and there is an urgent need for efficient HT-detection methods of gate-level netlists. In this work, we propose an approach to detect Trojan-nodes at the gate level, based on graph learning. The proposed method does not require any golden model and can be easily integrated into the integrated circuits design flow. In addition, we further design a unioned GNN network to combine information from the input side, output side, and neighbor side of the directed graph to generate representative node embeddings. The experimental results show that it could achieve 93.4% in recall, 91.4% in F-measure, and 90.7% in precision on average across different designs, which outperforms the state-of-the-art HT detection methods.

Hardware Trojan Detection and High-Precision Localization in NoC-based MPSoC using Machine learning

Abstract: Networks-on-Chips (NoC) based Multi-Processor System-on-Chip (MPSoC) are increasingly employed in industrial and consumer elec-tronics. Outsourcing third-party IPs (3PIPs) and tools in NoC-based MPSoC is a prevalent development way in most fabless companies. However, Hardware Trojan (HT) injected during its design stage can maliciously tamper with the functionality of this communication scheme, which undermines the security of the system and may cause a failure. Detecting and localizing HT with high pre-cision is a challenge for current techniques. This work proposes for the first time a novel approach that allows detection and high-precision localization of HT, which is based on the use of packet information and machine learning algorithms. It is equipped with a novel Dynamic Confidence Interval (DCI) algorithm to detect ma-licious packets, and a novel Dynamic Security Credit Table (DSCT) algorithm to localize HT. We evaluated the proposed framework on the mesh NoC running real workloads. The average detection precision of 96.3% and the average localization precision of 100% were obtained from the experiment results, and the minimum HT localization time is around 5.8 ~ 12.9us at 2GHz depending on the different HT-infected nodes and workloads.

Hardware Trojans in eNVM Neuromorphic Devices

Abstract: Fast and energy-efficient execution of a DNN on traditional CPU- and GPU-based architectures is challenging due to excessive data movement and inefficient computation. Emerging non-volatile memory (eNVM)-based accelerators that mimic biological neuron computations in the analog domain have shown significant performance improvements. However, the potential security threats in the supply chain of such systems have been largely understudied. This work describes a hardware supply chain attack against analog eNVM neural accelerators by identifying potential Trojan insertion points and proposes a hardware Trojan design that stealthily leaks model parameters while evading detection. Our evaluation shows that such a hardware Trojan can recover over 90% of the synaptic weights.

Trojan Playground: A Reinforcement Learning Framework for Hardware Trojan Insertion and Detection

Abstract: Current Hardware Trojan (HT) detection techniques are mostly developed based on a limited set of HT benchmarks. Existing HT benchmarks circuits are generated with multiple shortcomings, i.e., i) they are heavily biased by the designers' mindset when they are created, and ii) they are created through a one-dimensional lens, mainly the signal activity of nets. To address these shortcomings, we introduce the first automated reinforcement learning (RL) HT insertion and detection framework. In the insertion phase, an RL agent explores the circuits and finds different locations that are best for keeping inserted HTs hidden. On the defense side, we introduce a multi-criteria RL-based detector that generates test vectors to discover the existence of HTs. Using the proposed framework, one can explore the HT insertion and detection design spaces to break the human mindset limitations as well as the benchmark issues, ultimately leading toward the next-generation of innovative detectors. Our HT toolset is open-source to accelerate research in this field and reduce the initial setup time for newcomers. We demonstrate the efficacy of our framework on ISCAS-85 benchmarks and provide the attack and detection success rates and define a methodology for comparing our techniques.

Evil from Within: Machine Learning Backdoors through Hardware Trojans

Abstract: Backdoors pose a serious threat to machine learning, as they can compromise the integrity of security-critical systems, such as self-driving cars. While different defenses have been proposed to address this threat, they all rely on the assumption that the hardware on which the learning models are executed during inference is trusted. In this paper, we challenge this assumption and introduce a backdoor attack that completely resides within a common hardware accelerator for machine learning. Outside of the accelerator, neither the learning model nor the software is manipulated, so that current defenses fail. To make this attack practical, we overcome two challenges: First, as memory on a hardware accelerator is severely limited, we introduce the concept of a minimal backdoor that deviates as little as possible from the original model and is activated by replacing a few model parameters only. Second, we develop a configurable hardware trojan that can be provisioned with the backdoor and performs a replacement only when the specific target model is processed. We demonstrate the practical feasibility of our attack by implanting our hardware trojan into the Xilinx Vitis AI DPU, a commercial machine-learning accelerator. We configure the trojan with a minimal backdoor for a traffic-sign recognition system. The backdoor replaces only 30 (0.069%) model parameters, yet it reliably manipulates the recognition once the input contains a backdoor trigger. Our attack expands the hardware circuit of the accelerator by 0.24% and induces no run-time overhead, rendering a detection hardly possible. Given the complex and highly distributed manufacturing process of current hardware, our work points to a new threat in machine learning that is inaccessible to current security mechanisms and calls for hardware to be manufactured only in fully trusted environments.

Focusing on the Key Suspicious Trojan Nets with a Collaborative Approach

Abstract: While most gate-level hardware Trojan detection techniques strive to detect as many as possible suspicious nets, this paper suggests another direction: identifying only a few suspicious nets, in order to reduce the subsequent manual investigation effort, since there is no need to trace multiple suspicious nets that lead to the same Trojan module. To accomplish this goal, we adopt a collaborative approach by a combination of structural-based analysis, testability-based analysis, and behavioral-based analysis to minimize the number of suspicious Trojan nets. Extensive experiments are conducted with Trust-HUB benchmark and an industrial processor. The results are very significant: (1) high precision 95.39%, most of identified nets being actual Trojan nets; (2) high true negative rate 99.99%, most normal nets being correctly identified as non-suspicious; (3) 44% less suspicious nets to greatly reduce the subsequent manual investigation effort; while (4) leading to detect 100% of the Trojan modules.

Hardware Trojan Mitigation Technique in Network-on-Chip (NoC)

Abstract: Due to globalization in the semiconductor industry, malevolent modifications made in the hardware circuitry, known as hardware Trojans (HTs), have rendered the security of the chip very critical. Over the years, many methods have been proposed to detect and mitigate these HTs in general integrated circuits. However, insufficient effort has been made for hardware Trojans (HTs) in the network-on-chip. In this study, we implement a countermeasure to congeal the network-on-chip hardware design in order to prevent changes from being made to the network-on-chip design. We propose a collaborative method which uses flit integrity and dynamic flit permutation to eliminate the hardware Trojan inserted into the router of the NoC by a disloyal employee or a third-party vendor corporation. The proposed method increases the number of received packets by up to 10% more compared to existing techniques, which contain HTs in the destination address of the flit. Compared to the runtime HT mitigation method, the proposed scheme also decreases the average latency for the hardware Trojan inserted in the flit’s header, tail, and destination field up to 14.7%, 8%, and 3%, respectively.

PUF-based Hardware Trojan: Design and Novel Attack on Encryption Circuit

Abstract: The threat of Hardware Trojans (HT) has gradually increased in recent years. Our study proposes a novel attack with a new class of HT based on physical unclonable function (PUF) to leak information. This study aims to analyze and evaluate the performance of our PUF -based HT and raise awareness about the advanced version of HT. We employed a full-custom design flow, which translated the HT's layout into a compact footprint. This lightweight implementation requires only 749 FETs and an area of 10.6437 mm ² , indicating a high barrier to detection by conventional methods of testing and inspection. Moreover, the signature of the recommended PUF-based HT is physically encrypted so that even if anyone successfully detected the trojan, it would not allow unwarranted activation of the HT. To assess the feasibility of our PUF -based HT, we performed simulation on Tanner EDA and physical test on FPGA; we were also able to leak information successfully.

Hardware Trojan Modelling on a FPGA Based Deep Neural Network Accelerator

Abstract: AbstractNeural networks have started proliferating in various different applications including ones where security can’t be compromised. Training of high performance neural network models involves high hardware requirement and is also very time consuming. This forces users to rely on third party companies for training the neural networks, exposing the trained model to unscrupulous hands and reducing the trustworthiness of the model. It has been reported in literature about mixing of samples of malicious Trojans with training data, the trained network being embedded with hidden functionalities, which can be triggered by specific patterns of the Trojan. Hence it is essential to understand the possibilities of Trojan attacks on local systems. This work is aimed towards proposing a Trojan model for a deep neural network (DNN) targeting FPGA platforms. Insertion of a simple Trojan in the activation module of a neuron resulted in a decrease of 26% in the efficiency of the DNN. This work brings out the need for more efficient defense mechanisms against such Trojans.KeywordsNeural networkHardware trojanVLSIHardware implementationPattern recognition

Scalable Detection of Hardware Trojans using ATPG-based Activation of Rare Events

Abstract: Semiconductor supply chain vulnerability is a major concern in designing trustworthy systems. Malicious implants, popularly known as hardware Trojans, can get introduced at different stages in the System-on-Chip (SoC) design cycle. While there are promising test generation techniques for hardware Trojan detection, they have two practical limitations: (i) these approaches are designed to activate rare states while ignoring rare transitions, and (ii) these approaches are not scalable for large designs. In this paper, we propose a scalable test generation framework to address the above challenges. Our threat model assumes that an adversary may exploit rare events consisting of rare signals (states) as well as rare branches (transitions). We show that the rare branch coverage problem can be mapped to the rare signal coverage problem. We propose a scalable framework for detecting hardware Trojans using Automated Test Pattern Generation (ATPG) based activation of rare events. Specifically, we utilize the complementary abilities of N-detection and maximal clique activation of rare events to generate efficient test patterns. Experimental evaluation shows that our ATPG-based framework is scalable and significantly outperforms the state-of-the-art test generation based Trojan detection techniques.

Enhancing EU Cyber Defense Through Hardware Trojans Detection Capabilities

Abstract: Software Trojans and cybersecurity are a concern worldwide. Hardware Trojans are likely to be an issue faced by the Defence Industry of all countries. Information on how defense industry stakeholders deal with HT in Defense Products is by nature scarce or even inaccessible. It is however fair to assume that they adapt and use IC RE methodologies, notably some developed for IP infringement, to search for HTs. With these RE methodologies, checking a chip after its fabrication implies to deconstruct and analyze the whole surface and all the layers of a chip. It is thus hard to know for sure which states has acquired Hardware Trojan detection capabilities. There are however indications that some States could be in the process of acquiring such capabilities.

Securing Hardware Accelerator Against Reverse Engineering Attack

Abstract: Hardware Accelerators (HAs) have a significant contribution to the fast and uninterrupted functioning of a System-On-Chip (SoC). HAs are mostly used as reusable Intellectual Property (IP) in the SoCs to speed up the design process. This makes HAs susceptible to several hardware attacks like IP counterfeiting, IP cloning, inserting hardware Trojan etc. Reverse Engineering (RE) the HA design is one of the primary steps while launching those attacks. Hardware obfuscation hardens the RE process without changing its functionality, thus hindering the attacker's effort. However, none of the existing hardware obfuscation techniques protect HAs. This paper proposes a robust hardware obfuscation technique for HAs to enhance the RE complexity. It is an in-synthesis process where obfuscation is performed by inserting key-controlled blocks during architectural synthesis. The proposed obfuscation is achieved in three different ways, i.e., by obscuring the primary inputs, inserting the dummy operations, and obscuring the intermediate sub-functions. Unlike state-of-the-art methodologies, the obfuscation points are decided through a novel algorithm. We have analyzed the feasibility of the proposed approach on six different HAs for three different key sizes. Moreover, it achieves enhanced security (~12 times) with lesser design cost (~10.8%) compared to one closely related approach.

Game and Prospect Theoretic Hardware Trojan Testing

Abstract: In this paper, we address the problem of hardware Trojan testing with the buyer of an Integrated Circuit (IC), who is referred to as the defender, and the malicious manufacturer of the IC, who is referred to as the attacker, strategically acting against each other. Our developed model accounts for both imperfections in the testing process as well as costs incurred for performing testing. First, we analytically characterize Nash Equilibrium (NE) strategies for Trojan insertion and testing from the attacker's and the defender's perspectives, respectively, considering them to be fully rational in nature. Further, we also characterize NE-based Trojan insertion-testing strategies considering the attacker and the defender to have cognitive biases which make them exhibit irrationalities in their behaviors. Numerous simulation results are presented throughout the paper to provide important insights.

Graph Neural Networks for Hardware Vulnerability Analysis— Can you Trust your GNN?

Abstract: The participation of third-party entities in the globalized semiconductor supply chain introduces potential security vulnerabilities, such as intellectual property piracy and hardware Trojan (HT) insertion. Graph neural networks (GNNs) have been employed to address various hardware security threats, owing to their superior performance on graph-structured data, such as circuits. However, GNNs are also susceptible to attacks.This work examines the use of GNNs for detecting hardware threats like HTs and their vulnerability to attacks. We present BadGNN, a backdoor attack on GNNs that can hide HTs and evade detection with a 100% success rate through minor circuit perturbations. Our findings highlight the need for further investigation into the security and robustness of GNNs before they can be safely used in security-critical applications.

Exploiting Logic Locking for a Neural Trojan Attack on Machine Learning Accelerators

Abstract: Logic locking has been proposed to safeguard intellectual property (IP) during chip fabrication. Logic locking techniques protect hardware IP by making a subset of combinational modules in a design dependent on a secret key that is withheld from untrusted parties. If an incorrect secret key is used, a set of deterministic errors is produced in locked modules, restricting unauthorized use. A common target for logic locking is neural accelerators, especially as machine-learning-as-a-service becomes more prevalent. In this work, we explore how logic locking can be used to compromise the security of a neural accelerator it protects. Specifically, we show how the deterministic errors caused by incorrect keys can be harnessed to produce neural-trojan-style backdoors. To do so, we first outline a motivational attack scenario where a carefully chosen incorrect key, which we call a trojan key, produces misclassifications for an attacker-specified input class in a locked accelerator. We then develop a theoretically-robust attack methodology to automatically identify trojan keys. To evaluate this attack, we launch it on several locked accelerators. In our largest benchmark accelerator, our attack identified a trojan key that caused a 74\% decrease in classification accuracy for attacker-specified trigger inputs, while degrading accuracy by only 1.7\% for other inputs on average.

A New Optimal Method for the Secure Design of Combinational Circuits against Hardware Trojans Using Interference Logic Locking

Abstract: Effective resistance to intellectual property theft, reverse engineering, and hardware Trojan insertion in integrated circuit supply chains is increasingly essential, for which many solutions have been proposed. Accordingly, strong attacks are also designed in this field. One way to achieve the above goal is obfuscation. The hardware obfuscation method hides the primary function of the circuit and the normal Netlist from the attacker by adding several key gates in the original Netlist. The functionality circuit is correct only if the correct key is applied; otherwise, the circuit is obfuscated. In recent years, various obfuscation methods have been proposed. One is logic locking, the most prominent hardware protection technique since it can protect against untrusted items. Logic locking induces functional and structural changes to a design even before the layout generation. We secured the circuit against hardware Trojan insertion with a secure logic locking method based on the insertion of key gates in interference mode. We call our proposed method Secure Interference Logic Locking, SILL. SILL is based on minimum controllability in paths with maximum fan-out. In this method, we have reduced the number of key gates required for circuit obfuscation and created the maximum Hamming distance between normal and obscure outputs. In addition, the key gates are added to the circuit’s complete interference, and the AES algorithm is used to generate the key. Our proposed method, SILL, was simulated in the Vivado simulation environment; the algorithms used in this method were prepared in VHDL language and designed to allow parallel execution, then applied on the original Netlist of the ISCAS85 benchmark circuits. By analyzing and comparing the results of this simulation to recent works, the amount of hardware consumption has decreased (about 5% space consumption and about a 0.15-nanosecond time delay). Then, the SAT attack algorithm was tested on ISCAS85 benchmark circuits that were obfuscated with SILL. The execution time of the attack in the second attempt was 0.24 nanoseconds longer compared to similar recent works, and it timed out in the fourth attempt. The resistance of our proposed method, having less hardware overhead and higher speed is more effective against SAT attacks than the existing conventional methods.