Showing papers on "Logarithmic number system published in 2005"
01 Nov 2005
TL;DR: A 32-bit fixed-point logarithmic arithmetic unit is proposed for the possible application to mobile three-dimensional (3-D) graphics system and can program its number range for accurate computation flexibility of 3-D graphics pipeline.
Abstract: A 32-bit fixed-point logarithmic arithmetic unit is proposed for the possible application to mobile three-dimensional (3-D) graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in two clock cycles and powering operation in four clock cycles. It can program its number range for accurate computation flexibility of 3-D graphics pipeline and eight -region piecewise linear approximation model for logarithmic and antilogarithmic conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18-mum CMOS technology with 9-k gates. It operates at the maximum frequency of 231 MHz and consumes 2.18 mW at 1.8-V supply
92 citations
18 Apr 2005
TL;DR: This work created a parameterized LNS library of computational units and compared them to an existing floating point library, considered multiplication, division, addition, subtraction, and format conversion to determine when one format should be used over the other and when it is advantageous to change formats during a calculation.
Abstract: There have been many papers proposing the use of logarithmic numbers (LNS) as an alternative to floating point because of simpler multiplication, division and exponentiation computations. However, this advantage comes at the cost of complicated, inexact addition and subtraction, as well as the need to convert between the formats. In this work, we created a parameterized LNS library of computational units and compared them to an existing floating point library. Specifically, we considered multiplication, division, addition, subtraction, and format conversion to determine when one format should be used over the other and when it is advantageous to change formats during a calculation.
65 citations
TL;DR: This work proposes a novel range-addressable technique for using look-up tables that allows efficient conversion from binary-to-single or multidigit MDLNS with varying accuracies, depending on the selected implementation.
Abstract: The multidimensional logarithmic number system (MDLNS), which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and has the ability to use multiple MDLNS components, or digits. Unlike the LNS, there is no monotonic relationship between standard binary representations and MDLNS representations. Using look-up tables (LUTs) to perform the mapping function can be unrealistic for hardware implementations when large binary ranges or multiple digits are used. This work proposes a novel range-addressable technique for using look-up tables that allows efficient conversion from binary-to-single or multidigit MDLNS with varying accuracies, depending on the selected implementation.
47 citations
02 Nov 2005
TL;DR: A high-level synthesis methodology under constraints is presented based on a fixed-point operator library which characterizes the operators cost according to their wordlength, which drastically reduces the optimization time.
Abstract: Field programmable gate arrays (FPGAs) are now considered as a real alternative for digital signal processing (DSP) applications. But, new methodologies are still needed to automatically map a DSP application into an FPGA with respect to design constraints such as area, power consumption, execution time and time-to-market. Moreover DSP applications are frequently specified using floating-point arithmetic whereas fixed-point arithmetic should be used on FPGA. In this paper, a high-level synthesis methodology under constraints is presented. The originality is to consider a computation accuracy constraint. The methodology is based on a fixed-point operator library which characterizes the operators cost according to their wordlength. An error noise propagation model is used to compute an analytical expression of the accuracy in function of the signals wordlength. To obtain an efficient hardware implementation, the data wordlength optimization process is coupled with the high-level synthesis. In addition, the accuracy evaluation is done through an analytical method, which drastically reduces the optimization time.
33 citations
27 Jun 2005
TL;DR: A novel way comparisons can be performed in parallel to the lookup from a small table, making RLNS viable in practical applications that can benefit from shorter multiply and divide times.
Abstract: The residue logarithmic number system (RLNS) represents real values as quantized logarithms which, in turn, are represented using the residue number system (RNS). Compared to the conventional logarithmic number system (LNS) in which quantized logarithms are represented as binary integers, RLNS offers faster multiplication and division times. RLNS and LNS use a table lookup involving all bits for addition. The width, dynamic range, precision and naive table size of RLNS (with careful moduli selection) is as good as those for conventional LNS. Conventional LNS can be more efficient than naive addition lookup. First, commutativity allows interchanging arguments. Second, the addition function is often essentially zero, and does not have to be tabulated. In binary, comparisons are easy. In residue, comparisons are slow. Although RLNS inherently demands comparison, this paper shows a novel way comparisons can be performed in parallel to the lookup from a small table. This paper also describes a novel tool that generates synthesizable Verilog, making RLNS viable in practical applications that can benefit from shorter multiply and divide times.
25 citations
TL;DR: An improved design for a two-digit 2D MDLNS filterbank implementation which reduces power and area by over two times compared to the original design is discussed.
Abstract: This paper addresses the implementation of a filterbank for digital hearing aids using a multi-dimensional logarithmic number system (MDLNS). The MDLNS, which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and the ability to use multiple MDLNS components or digits. The logarithmic properties of the MDLNS also allow for reduced complexity multiplication and large dynamic range, and a multiple-digit MDLNS provides a considerable reduction in hardware complexity compared to a conventional LNS approach. We discuss an improved design for a two-digit 2D MDLNS filterbank implementation which reduces power and area by over two times compared to the original design.
19 citations
Patent•
02 Jun 2005TL;DR: In this paper, a method and apparatus for performing logarithmic arithmetic with real and/or complex numbers represented in a log-polar format is described, where memory in the ALU stores a look-up table used to determine log-arithms of complex numbers.
Abstract: The present invention describes a method and apparatus for performing logarithmic arithmetic with real and/or complex numbers represented in a logarithmic format. In one exemplary embodiment, an ALU implements logarithmic arithmetic on complex numbers represented in a logpolar format. According to this embodiment, memory in the ALU stores a look-up table used to determine logarithms of complex numbers, while a processor in the ALU generates an output logarithm based on complex input operands represented in logpolar format using the stored look-up table. In another exemplary embodiment, the ALU performs logarithmic arithmetic on real and complex numbers represented in logarithmic format. In this embodiment, the memory stores two look-up tables, one for determining logarithms of real numbers and one for determining logarithms of complex numbers, while the processor generates an output logarithm based on real or complex input operands represented in logarithmic format using the real or complex look-up tables, respectively.
19 citations
10 Oct 2005
TL;DR: A methodology for implementing FPGA-based accelerator (FBA) from a high-level specification language is described and applied to acceleration of astrophysical N-body application with two types of platforms.
Abstract: In this paper, we describe a methodology for implementing FPGA-based accelerator (FBA) from a high-level specification language. We have constructed a software package specially tuned for accelerating particle-based scientific computations with an FBA. Our software generates (a) a suitable configuration for the FPGA, (b) the C source code for interfacing with the FBA, and (c) a software emulator. The FPGA configuration is build by combining components from a library of parametrized arithmetic modules; these modules implement fixed-point, floating-point and logarithmic number system with flexible bitwidth and pipeline stages. To make certain our methodology is effective, we have applied our methodology to acceleration of astrophysical N-body application with two types of platforms. One is our PROGRAPE-3 with four XC2VP70-5 FPGAs and another is a minimum composition of CRAY-XD1 with one XC2VP50-7 FPGA. As the result, we have achieved peak performance of 324 Gflops with PROGRAPE-3 and 45 Gflops with the minimum CRAY-XD1, sustained performance of 236 Gflops with PROGRAPE-3 and 34 Gflops with the CRAY-XD1.
16 citations
23 May 2005
TL;DR: The results show that it is possible to use this hybrid-LNS architecture to build multiplierless DCT and IDCT transforms having only a minimal reduction in image quality, suitable for implementation on existing mid-range FPGA technologies where there are limitations on the size of on-chip memory and high-speed computing elements.
Abstract: This paper presents an evaluation of an algorithm for performing the forward and inverse discrete cosine transforms (DCT) on digital images using a hybrid-logarithmic number system (hybrid-LNS) instead of linear binary arithmetic. The algorithm has been simulated using Matlab/sup /spl reg// where the accuracy of the fractional part of the logarithm has been limited to 8 bits and has been calculated using just 4, 6 or 8 binary address bits of the linear input data. The results show that it is possible to use this hybrid-LNS architecture to build multiplierless DCT and IDCT transforms having only a minimal reduction in image quality. The algorithm is suitable for implementation on existing mid-range FPGA technologies where there are limitations on the size of on-chip memory and high-speed computing elements.
13 citations
01 Jan 2005
TL;DR: A Bayesian pixel-based segmentation algorithm in hardware is implemented, and it is found that certain portions of the algorithm running on a mid-range FPGA could significantly outperform an implementationRunning on a high-end PC.
Abstract: Image segmentation is a process used in computer vision to automatically divide up an image. We investigate the suitability of FPGAs and Log Arithmetic for image processing. We implemented a Bayesian pixel-based segmentation algorithm in hardware, and found that certain portions of the algorithm running on a mid-range FPGA could significantly outperform an implementation running on a high-end PC
12 citations
13 Mar 2005
TL;DR: Matlab simulations of the hybrid logarithmic structure show that its performance is superior to that of recently published fixed point solutions, while offering a significantly reduced complexity when compared to floating point equivalents proposed for the WCDMA downlink in receiver applications.
Abstract: The paper compares and contrasts the performance of a root raised cosine matched filter implemented using hybrid logarithmic arithmetic with that of standard binary and floating point implementations. Hybrid logarithmic arithmetic is advantageous for FIR digital filters since it removes the necessity for the use of high speed array multipliers. These can be replaced by simple lookup table structures for conversion to and from the logarithmic domain. Matlab simulations of the hybrid logarithmic structure show that its performance is superior to that of recently published fixed point solutions, while offering a significantly reduced complexity when compared to floating point equivalents proposed for the WCDMA downlink in receiver applications. The use of hybrid logarithmic arithmetic also has the potential to reduce the power consumption, latency and hardware complexity for mobile handset applications.
04 Apr 2005
TL;DR: The research described in this paper aims to investigate whether FPGAs and logarithmic arithmetic are a viable compute-platform for high performance computing by implementing lattice QCD for this platform.
Abstract: In this paper, we discuss the implementation of a lattice quantum chromodynamics (QCD) application to a Xilinx VirtexII FPGA device on an Alpha Data ADM-XRC-II board using Handel-C and logarithmic arithmetic. The specific algorithm implemented is the Wilson Dirac Fermion Vector times matrix product operation. QCD is the scientific theory that describes the interactions of various types of sub-atomic particles. Lattice QCD is the use of computer simulations to prove aspects of this theory. The research described in this paper aims to investigate whether FPGAs and logarithmic arithmetic are a viable compute-platform for high performance computing by implementing lattice QCD for this platform. We have achieved competitive performance of at least 936 MFlops per node, executing 14.2 floating point equivalent operations per cycle, which is far higher than the previous solutions proposed for lattice QCD simulations.
30 Aug 2005
TL;DR: A new algorithm is given for computing trigonometric functions using the logarithmic number system (LNS) based on the laws of sines and cosines, which is accurate to 22 bits when intermediate steps are performed with 23-bit precision LNS.
Abstract: A new algorithm is given for computing trigonometric functions using the logarithmic number system (LNS). Based on the laws of sines and cosines, the algorithm uses novel addressing of ROMs with the middle-order bits of the LNS representation. Error analysis and simulation show the algorithm is accurate to 22 bits when intermediate steps are performed with 23-bit precision LNS. A VLIW software implementation having throughput of one trigonometric result every 17 cycles is suggested that uses special instructions to access small ROMs containing logarithmic sines and cosines. Also, the proposed algorithm can be implemented fully in hardware having throughput of one trigonometric result every one or two cycles using minor low-cost modifications to an existing LNS ALU design.
01 Jan 2005
TL;DR: A simple model of dithers for floating-point is introduced, its practical use is discussed, and its necessity and possibilities are investigated.
Abstract: Dithering is widely used for decreasing the bias in fixed-point quantization and rounding. Since floating-point digital signal processors (DSP’s) and floating-point arithmetic are becoming widely used, it is timely to investigate the necessity and possibilities of dithering for floating-point numbers. The paper introduces a simple model of dithers for floating-point, and discusses its practical use.
Patent•
01 Jun 2005TL;DR: In this article, a method and ALU for implementing logarithmic arithmetic in a multi-stage pipeline is described, where each stage computes a stage output based on the stage input and the corresponding look-up table.
Abstract: A method and ALU for implementing logarithmic arithmetic in a multi-stage pipeline is described herein. According to one embodiment, a master function is decomposed into two or more sub-functions. Memory associated with the pipeline stores a look-up table for each stage of the pipeline, where each table represents function values generated based on the corresponding sub-function, and where the look-up table associated with one stage differs from the look-up table(s) associated with at least one other stage. Each stage computes a stage output based on the stage input and the corresponding look-up table. By combining the stage outputs, the multi-stage pipeline outputs the logarithmic arithmetic output.
10 Oct 2005
TL;DR: Presented high-level synthesis describes scheduling for wide class of DSP algorithms through cyclic scheduling using integer linear programming while minimizing the schedule period in the terms of clock cycles.
Abstract: Presented high-level synthesis describes scheduling for wide class of DSP algorithms. Several FPGA vendors or even ASIC designs are targeted via Handel-C compiled by Celoxica DK3.1 compiler. Using the authors' approach, the designer can easily change type of used pipelined arithmetic modules and then check new performance. The optimal time schedule is found by cyclic scheduling using integer linear programming while minimizing the schedule period in the terms of clock cycles. Experimental results in HW implementation, performed on logarithmic arithmetic and floating-point arithmetic, confirm significant influence of the period on the resulting performance of DSP algorithms.
TL;DR: A biasing scheme is proposed for substantially reducing the complexity of the lookup table for logarithmic number systems, effective when repeated accumulation of products is needed.
Abstract: Logarithmic arithmetic can provide advantages especially in high-speed, moderate precision computations. A drawback of the logarithmic number system is the cumbersome addition and subtraction operations, involving lookup table accesses. A biasing scheme is proposed for substantially reducing the complexity of the lookup table. The approach is effective when repeated accumulation of products is needed, as in finite impulse response (FIR) filter implementations.
18 Aug 2005
TL;DR: Using the techniques proposed here, RLNS with dynamic range and precision suitable for MPEG applications can be synthesized, and bipartite RLNS achieves area savings and shorter delays compared to naive RLNS.
Abstract: The Logarithmic Number System (LNS) has area and power advantages over fixed-point and floating-point number systems in some applications that tolerate moderate precision. LNS multiplication/division require only addition/subtraction of logarithms. Normally, LNS is implemented with ripple-carry binary arithmetic for manipulating the logarithms; however, this paper uses carry-free residue arithmetic instead. The Residue Logarithmic Number System (RLNS) has the advantage of faster multiplication and division. In contrast, RLNS addition requires table-lookup, which is its main area and delay cost. The bipartite approach, which uses two tables and an integer addition, is introduced here to optimize RLNS addition. Using the techniques proposed here, RLNS with dynamic range and precision suitable for MPEG applications can be synthesized. Synthesis results show that bipartite RLNS achieves area savings and shorter delays compared to naive RLNS.
01 Jan 2005
TL;DR: The proposed hardware algorithm for improving the speed of the linear digit‐recurrence logarithmic algorithm only includes small table lookup operation, digit‐multiplication, and simple square operations when the word length of the operand is less than or equal to 64 bits.
Abstract: A hardware algorithm is proposed for improving the speed of the linear digit‐recurrence logarithmic algorithm. The convergence rate of this logarithmic algorithm is exponential. Furthermore, the size of the lookup tables used in the algorithm is smaller than the size of the lookup tables used in the digit‐recurrence algorithms. When the word length of the operand is less than or equal to 64 bits, the operations involved in each stage of the logarithmic computation only include small table lookup operation, digit‐multiplication, and simple square operations. We conclude that the hardware implementation of our proposed algorithm is very efficient.
01 Jan 2005
TL;DR: This paper aims to provide a history of the noise cancelling performance of the LNS Lookup Operation and some of the techniques used to achieve this goal.
Abstract: vi Acknowledgments, v Acoustics, 16 Adder, 37 ANC Filtered-X, 3 History, 1 Leaky LMS, 3 Secondary Path, 5 Appendices, 57 Appendix Matlab Routines, 62 ROM Compiler in PERL, 67 Architecture Filter, 50 Area, 8, 10 Band-limited noise cancelling performance, 11 Bibliography, 74 Bow-tie Effect, 22 Column Circuits, 44 Convergence, 12, 33 Cost, 8 Dedication, iv Die Per Wafer, 9 Earlab, 17 Enhancements, 54 Error near zero (enz), 22 Expected Value, 59 Filter, 50, 53 Direct Form, 51 Pipelining, 55 Transposed, 51 Fixed-point, 21, 28 Gradient, 60 Headphones, Noise Cancelling, 7 HSPICE, 69 Implementation, 34 Input Builder, 19 Introduction, 1 Leug, Paul, 1 LMS Derivation, 58 LNS, 34 Adder, 35 Modelling, 19 Multiplication, 35 Logarithmic number system, see LNS Lookup Operation, see ROM Matlab, 14 Media Players, 7 Model Active Noise Control, 16 ADC, 17 Modelling, 14 Multiplexer, 37 Performance, 11, 58 Pipelining, 55 Power, 10
01 Jan 2005
TL;DR: This chapter describes two arithmetic systems that employ nonstandard encoding of numbers that offer important advantages in the efficiency of their operation and may be at the same time more power or energy-efficient, faster, and/or smaller than other systems.
Abstract: This chapter describes two arithmetic systems that employ nonstandard encoding of numbers. The logarithmic number system (LNS) and the residue number system (RNS) are singled out because they are shown to offer important advantages in the efficiency of their operation and may be at the same time more power or energy-efficient, faster, and/or smaller than other systems. The impact of arithmetic in a digital system is not only limited to the definition of the architecture of arithmetic circuits. Arithmetic affects several levels of the design abstraction because it may reduce the number of operations, the signal activity, and the strength of the operators. The choice of arithmetic may lead to substantial power savings, reduced area, and enhanced speed. LNS is considered as an alternative to floating-point representation. RNS arithmetic faces difficulties with sign detection, division, and magnitude comparison. These difficulties may outweigh the benefits it presents for addition, subtraction, and multiplication as far as general computing is concerned. The chapter also discusses RNS and power dissipation.
01 Jan 2005
TL;DR: Venkataraman and Mahalingam as mentioned in this paper improved accuracy in logarithmic multiplication using operand decomposition using ODEs, improving the accuracy of the ODE.
Abstract: Venkataraman, Mahalingam, "Improving accuracy in logarithmic multiplication using operand decomposition" (2005). Graduate Theses and Dissertations.
27 May 2005
TL;DR: Simulation results show that this method of sinusoidal signal generation, based on the combination of an IIR digital filter and Coordinate Rotations Digital Computer (CORDIC) arithmetic, outputs signals with higher SNR and higher frequencies, compared to the direct CORDIC algorithm.
Abstract: This paper proposes a new method of sinusoidal signal generation, which is based on the combination of an IIR digital filter and Coordinate Rotations Digital Computer (CORDIC) arithmetic. Theoretical analysis of the method is discussed. Simulation results show that, at the same level of hardware consumption, this method outputs signals with higher SNR and higher frequencies, compared to the direct CORDIC algorithm.
01 Jan 2005
TL;DR: This paper uses multidigit multidimensional logarithmic number system (MDLNS) to implement hardware efficient decimation filter architecture for communication receiver applications and proposes a new MDLNS based digital filter that achieves the required stop-band attenuation with considerable reductions in hardware.
Abstract: In this paper, we use multidigit multidimensional logarithmic number system (MDLNS) to implement hardware efficient decimation filter architecture for communication receiver applications. We have considered single, two and three dimensional two-digit MDLNS architectures with a few nonbinary bases. The new MDLNS based digital filter, has advantages of 50% reduced read only memory (ROM) array and an optimal real nonbinary base, which reduces the overall hardware requirements. The proposed two-digit 2D logarithmic decimation filter achieves the required stop-band attenuation with considerable reductions in hardware compared to conventional decimation filter architectures. The proposed 2D architecture requires sixteen 3-bit adders, one 8-bit ROM and an 8-bit shifter for each filter coefficient, whereas conventional filter architecture needs 13-bit multipliers for each coefficient
27 Apr 2005
TL;DR: A lightweight arithmetic for embedded signal processing, whose hardware complexity is similar to that of the integer one, which even out-performs the hand-optimized 32-bit code with integer arithmetic.
Abstract: This paper presents a lightweight arithmetic for embedded signal processing, whose hardware complexity is similar to that of the integer one. In our simulations, its 16-bit version has 40.18dB signal to round-off error ratio over the IEEE single-precision floating-point arithmetic, which even out-performs the hand-optimized 32-bit code with integer arithmetic.
18 Aug 2005
TL;DR: It is shown that the use of a 2-DLNS representation results in significant lower error variance compared to floating-point number systems and the hardware complexity required with the error performance comparable to classic LNS can be significantly reduced due to smaller size of ROMs compared with LNS.
Abstract: Multidimensional logarithmic number system (MDLNS) is a recently developed number representation that is very efficient for implementing the Inner Product Step Processor (IPSP). The MDLNS provides more degrees of freedom than the classical LNS by virtue of the orthogonal bases and ability to obtain reduction of hardware complexity from the use of multiple digits. This paper presents an analysis of errors introduced in data mapping from real numbers to 2-dimentional LNS (2-DLNS). Due to non-uniform error distribution, mapping space is divided by pre-assigned segments, where error performance can be uniquely characterized. Mapping errors are collected piece-wisely over all of the segments. In 1-digit 2-DLNS, error collection can be simplified by using pattern-matching scheme. Expressions for error variance are derived. It is shown that the use of a 2-DLNS representation results in significant lower error variance compared to floating-point number systems. The hardware complexity required with the error performance comparable to classic LNS can be significantly reduced due to smaller size of ROMs compared with LNS. The results of the error analysis have been verified by numerical simulations.
TL;DR: A conjunctive notation is used, also known as DIGILOG, to introduce a flexible means in creating configurable arithmetic of arbitrary order using a single module type that allows the Mitrion hardware compiler to match the hardware closer to the demands of the specific algorithm.
Abstract: The scientific community has gratefully embraced floating-point arithmetic to escape the close attention for accuracy and precision required in fixed-point computational styles. Though its deficiencies are well known, the role of the floating-point system as standard has kept other number representation systems from coming into practice. The paper discusses the relation between fixed and floating-point numbers from a pragmatic point of view that allows to mix both systems to optimize FPGA-based hardware accelerators. The method is developed for the Mitrion "processor on demand" technology, where a computationally intensive algorithm is transformed into a dedicated. The large gap in cycle time between fixed and floating-point operations and between direct and reverse operations makes the on-chip control for the fine-grain pipelines of parallel logic very complicated. Having alternative hardware realizations available can alleviate this. The paper uses a conjunctive notation, also known as DIGILOG, to introduce a flexible means in creating configurable arithmetic of arbitrary order using a single module type. This allows the Mitrion hardware compiler to match the hardware closer to the demands of the specific algorithm. Typical applications are in molecular simulation and real-time image analysis.
15 Mar 2005
TL;DR: The design, optimization and implementation of floating- point arithmetic modules on FPGA to be used in DSP appkications are presented, making them suitable for different requirements of signal formats in digital signal processing.
Abstract: This paper presents the design, optimization and implementation of floating- point arithmetic modules on FPGA to be used in DSP appkications. These modules are floating-point multiplier, floating-point adderhbtractor, floating-point complex multiplier, floating-point complex adder/subtractor and floating-point multiplier-accumulator (MAC). The simulation and the Synthesis results for these modules are provided. All the modules presented in this paper support creation of custom floating-point format, making them suitable for different requirements of signal formats in digital signal processing. Fast Fourier Transform (FF'"), which is one of the most utilized operations in digital signal processing and communications, is used as an application example. A butterfly unit that can be used in Fast Fourier Transform (FFT) is designed using these optimized arithmetic modules. A pipelined FFT is presented using the designed butterfly unit. The design targeted Xilinx (Virtex 11) FPGA series.
01 Jan 2005
TL;DR: It is shown that the FIR filters implemented using 2-DLNS result in lower error-to-signal variance than that implemented using LNS and FPNS as well as potential hardware reduction of the entire filter.
Abstract: Multi-dimensional logarithmic number system (MDLNS) is a recently developed number representation that is very efficient for implementing the inner product step processor (IPSP). The effects of data mapping and conversion in finite-impulse response (FIR) digital filters implemented with 1 digit 2-dimensional logarithmic number (2-DLNS) are examined. Expressions for the ratio of output variance with errors to output variance without errors are derived. The simulation results indicate that the experimental results are in good agreement with the theoretical results. It is shown that the FIR filters implemented using 2-DLNS result in lower error-to-signal variance than that implemented using LNS and FPNS as well as potential hardware reduction of the entire filter