Showing papers on "Memory refresh published in 1995"

Dynamic non-volatile memory update in a computer system

Abstract: A computer system wherein a portion of code/data stored in a non-volatile memory device can be dynamically modified or updated without removing any covers or parts from the computer system. The computer system of the preferred embodiment includes a flash memory component coupled to a computer system bus for storing non-volatile code and data. Using the present invention, the contents of a portion of the flash memory may be replaced, modified, updated, or reprogrammed without the need for removing and/or replacing any computer system hardware components. The flash memory device used in the preferred embodiment contains four separately erasable/programmable non-symmetrical blocks of memory. One of these four blocks may be electronically locked to prevent erasure or modification of its contents once it is installed. This configuration allows the processing logic of the computer system to update or modify any selected block of memory without affecting the contents of other blocks. One memory block contains a normal BIOS. An electronically protected flash memory area is used for storage of a recovery BIOS which is used for recovery operations. The present invention also includes hardware for selecting one of the two available update modes: normal or recovery. Thus, using a mode selection apparatus, either a normal system BIOS or a recovery BIOS may be activated.

Interrupt-based hardware support for profiling memory system performance

Abstract: Fueled by higher clock rates and superscalar technologies, growth in processor speed continues to outpace improvement in memory system performance. Reflecting this trend, architects are developing increasingly complex memory hierarchies to mask the speed gap, compiler writers are adding locality enhancing transformations to better utilize complex memory hierarchies, and applications programmers are recoding their algorithms to exploit memory systems. All of these groups need empirical data on memory system behavior to guide their optimizations. This paper describes how to combine simple hardware support and sampling techniques to obtain such data without appreciably perturbing system performance. The idea is implemented in the Mprof prototype that profiles data stall cycles, first level cache misses, and second level misses on the Sun Sparc 10/41.

Distributed processing memory chip with embedded logic having both data memory and broadcast memory

Abstract: Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data memory (202) by the embedded logic (206) with minimal handshaking with a remote CPU. In a functioning system, the memory chips are organized in a hierarchical manner and include address-associative memory systems.

Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory

Abstract: A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).

A multilevel-cell 32 Mb flash memory

Abstract: A flash memory with multilevel cell significantly reduces the memory per-bit cost. A 32 Mb multilevel-cell (MLC) flash memory storing two bits of data per cell achieves 32 Mb memory storage capacity using 16 M flash memory cells. This 32 Mb flash memory on a 0.6 /spl mu/m process has a 2.0/spl times/1.8 /spl mu/m/sup 2/ flash cell. In MLC operation, the logical flash memory cell achieves two bits per cell using four possible states, defined by four flash cell threshold voltage ranges. The relationship between the threshold voltage ranges stored in the flash memory cell and the corresponding logic levels is shown in this paper, which also shows a plot of the four threshold voltage distributions, each with a separation range.

Method and apparatus for automatically scrubbing ecc errors in memory via hardware

Abstract: The present invention provides a method and apparatus for automatically scrubbing ECC errors in memory upon the detection of a correctable error in data read from memory. This is performed by providing in a memory controller (MC) memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output (72, 64) from the ECC error checking and correcting unit and a writeback path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data. The memory control logic then obtains exclusive control over the first data buffer and the writeback path to control writing of the corrected read data onto the writeback path and subsequently to memory.

Method and apparatus for dynamically adjusting power/performance characteristics of a memory subsystem

Abstract: An apparatus and method for dynamically adjusting the power/performance characteristics of a memory subsystem. Since the memory subsystem access requirements are heavily dependent on the application being executed, static methods of enabling or disabling the individual memory system components (as are used in prior art) are less than optimal from a power consumption perspective. By dynamically tracking the behavior of the memory subsystem, the invention predicts the probability that the next event will have certain characteristics, such as whether it will result in a memory cycle that requires the attention of a cache memory, whether that memory cycle will result in a cache memory hit, and whether a DRAM page hit in main memory will occur if the requested data is not in one of the levels of cache memory. Based on these probabilities, the invention dynamically enables or disables components of the subsystem. By intelligently adjusting the state of these components, significant power savings are achieved without degradation in performance.

Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories

Abstract: A memory and sense amplifier with latched output included therein derives high speed and noise immunity with precharged logic circuits through the separation of sense amplifier enablement and resetting by use of the precharge operation. Inclusion of bit line decoders which are wholly or partially self-resetting and self-precharging in sense amplifier support circuitry allows high performance at extremely short memory operation cycle times. A multiplexor is included which is usable in operating cycles as well as test cycles of the memory and further, in combination with other elements of the memory and sense amplifier arrangement, enables the pipelining of plural memory operations in a single memory cycle.

A secure memory card with programmed controlled security access control

Abstract: A secure memory card includes a microprocessor on a single semiconductor chip which interconnects through an internal bus to a number of non-volatile addressable memory chips (103a, 103b, ...103n). The microprocessor includes an addressable non-volatile memory for storing a number of key values. Each chip's memory (54) is organized into a number of blocks, each block including a number of rows of byte locations. Each row includes a lock bit location, the total number of which provide storage for a lock value. Each memory chip (103a, 103b, ...103n) is constructed to include security control logic circuits (30) arranged to perform a predetermined key validation operation by comparing key values against the bit contents of lock bit locations during an authentication procedure with a host computer.

Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller

Abstract: An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.

Hierarchical data storage system employing contemporaneous transfer of designated data pages to long write and short read cycle memory

Abstract: A method and system control approach for contemporaneous transfer of designated replacement pages from a main store to an associated memory having a write cycle 10× longer than a read cycle thereof (e.g. nonvolatile semiconductor memory). Each designated data page includes an associated home address within the nonvolatile semiconductor memory. The approach includes designating at least two data pages of the main store for transfer to the nonvolatile semiconductor memory; and upon occurrence of a predetermined condition, contemporaneously transferring the designated data pages from the main store to the nonvolatile semiconductor memory for writing into the nonvolatile semiconductor memory at their associated addresses. Preferably, the designated data pages are simultaneously written in the nonvolatile semiconductor memory subsequent to a simultaneous erase of their associated home addresses.

Main memory system and checkpointing protocol for fault-tolerant computer system

Abstract: A mechanism for maintaining a consistent state in main memory without constraining normal computer operation is provided, thereby enabling a computer system to recover from faults without loss of data or processing continuity. In a typical computer system, a processor and input/output elements are connected to a main memory via a memory bus. A shadow memory element, which includes a buffer memory and a main storage element, is also attached to this memory bus. During normal processing, data written to primary memory is also captured by the buffer memory of the shadow memory element. When a checkpoint is desired (thereby establishing a consistent state in main memory to which all executing applications can safely return following a fault), the data previously captured in the buffer memory is then copied to the main storage element of the shadow memory element. This structure and protocol can guarantee a consistent state in main memory, thus enabling fault-tolerant operation.

Flash memory system having memory cache

Abstract: The present invention discloses an electronic memory system having semipermanent memory storage, a memory device for rapid data transfer and temporary memory storage, and controller for monitoring and controlling writes to the semipermanent memory storage.

Nonvolatile SRAM cells and cell arrays

Abstract: A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, a logic high output from this memory cell (400) is at about VDD; and in a second state, a logic low output is about VSS. The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between VDD (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and VSS (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed. In the second state, first programmable memory element (515) is programmed, while second programmable memory element (520) is not programmed. The memory cell (400) may be used to store the configuration information of a programmable logic device (121).

Method and apparatus for performing write operations in multi-level cell storage device

Abstract: A memory contains a plurality of memory cells that are capable of storing one or more bits of data in each memory cell. The memory stores, in response to a write operation, data corresponding to the write operation in a first set of the memory cells such that each cell of the first set of the memory cells stores a single bit. Thereafter, data from the first set of memory cells are transferred to a second set of the memory cells such that each cell of the second set of the memory cells stores more than a single bit of data. The write operation to the first set of cells is executed in a foreground operation, and in a subsequent background operation, data from the first set of memory cells are transferred to the second set of memory cells. The memory cells are non-volatile flash electrically erasable programmable read only memory (EEPROM) cells, and therefore require erasure before programming. Typically, memory cells are reclaimed in a background operation. However, if not enough memory cells are available for a write operation, then a set of memory cells are reclaimed in a foreground operation, and more than one bit of the data are stored in the reclaimed memory cells.

Self-enabling pulse trapping circuit

Abstract: An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. An external input is used to terminate and change a burst operation. Circuitry is provided to monitor the external input during burst operations and provide an appropriate control signal.

Circuit and method of operating a ferrolectric memory in a DRAM mode

Abstract: A static ferroelectric memory circuit is described which has an array of ferroelectric memory cells fabricated as single capacitors using a ferroelectric dielectric and arranged as a static random access memory (SRAM). Data can be stored in a non-volatile manner on the memory cells by controlling the voltage placed upon the plates of the cell. A method is described for operating the ferroelectric memory as a dynamic random access memory (DRAM). Test methods are described for testing the memory cells and identifying whether a defect is result of a ferroelectric material defect or a physical defect, such as a short, open or high leakage.

High-performance integrated bit-mapped graphics controller

Abstract: A low-cost high-performance technique for providing bit-mapped graphics display controllers is described whereby video frame buffer memory and video controller functions are integrated together on a single chip, permitting very wide video memory formats without the usual penalties of high pin count, package count, and wiring complexity. The wide video memory format relaxes timing requirements on the video frame buffer memory and provides greater accessibility of the video frame buffer memory for pixel data accesses other than display refresh accesses.

Semiconductor memory with a timing controlled for receiving data at a semiconductor memory module to be accessed

Abstract: In a semiconductor memory, a plurality of semiconductor memory modules (21, ....2n) are connected through a common clock signal line and one or more other signal lines to an accessing circuit. The accessing circuit has a timing information storage unit (3A, 3B) for storing beforehand access timing information associated with the respective semiconductor memory modules and a timing varying unit (6A, 6B) for varying a data receiving timing at a transfer destination in compliance with a semiconductor memory module to be accessed, on the basis of the access timing information stored in the timing information storage unit.

Non-volatile memory system of multi-level transistor cells and methods using same

Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Method and apparatus for processing memory-type information within a microprocessor

Abstract: A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor (200-216). Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined (214-216) for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed (218-230) in accordance with any one of a number or processing protocols including write-through processing (220), write-back processing (222), write-protect processing (224), restricted-cacheability processing (226), uncacheable speculatable write-combining processing (230), or uncacheable processing (228). By providing memory-type information explicitly within the microprocessor the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor (200) capable of generating speculative memory microinstructions (202-204).

Non-volatile semiconductor memory device for storing multi-value data

Abstract: A non-volatile semiconductor memory device having a plurality of electrically rewritable memory cells for storing multi-value data The cells are arranged in an array and are coupled to a plurality of bit lines which transmit and receive data to and from the memory cells The device also includes a plurality of sense amplifiers for sensing and amplifying the potentials of the bit lines; a plurality of data latches forming data to be written in the memory cells; a plurality of verify circuits for checking whether the data is correctly written in the memory cells and a plurality of switches The switches control the connections of the sense amplifiers, data latches and verify circuits to the bit lines Write control devices set the potentials of the bit lines in accordance with the contents of the data latches The switches are set in an open state after data is read from the memory cells onto the bit lines and the sense amplifiers almost simultaneously operate after the switches are set in an open state to sense and amplify the data read onto the bit lines

Method and apparatus for a game delivery service including flash memory and a game back-up module

Abstract: A communications terminal for receiving digital data services at a location remote from a transmitter comprises a service controller, a bus system, a random access memory and a non-volatile memory. The non-volatile memory preferably comprises FLASH memory. Data is first loaded into random access memory, preferably SRAM and there checked for errors and error-corrected. The data is preferably loaded in blocks into FLASH memory in a predetermined manner to further secure the service data and to permit the use of byte-wide memories accessed as word-wide memories. A service back-up memory is further connected to the bus for storing service data during suspension of play of a service. The service back-up memory preferably comprises a FLASH memory card having its own basic input output service (BIOS) control. A method of storing back-up service data in a home communications terminal comprises the steps of storing current service data in a first FLASH non-volatile memory and storing previous service data in a state in which play of the service is suspended is a second FLASH non-volatile memory, the service back-up memory described above.

Non-volatile dynamic random access memory

Abstract: A memory device including a memory for storing data having volatile and non-volatile capability; an access circuit for reading/writing the data stored in a volatile state at an address in said memory in accordance with an access command indicating the address; a transfer circuit for transferring the data stored in said memory from the volatile state into a non-volatile state; and a recall circuit for recalling the data stored in said memory in the non-volatile state into the volatile state, wherein said recall circuit selectively performs a recall operation for a section of said memory which includes the address before said access circuit performs a read/write operation for the data when the data at the address is stored in the non-volatile state.

Computer configuration system and method with state and restoration from non-volatile semiconductor memory

Abstract: A computer system and method provides a user the ability to restore operation to a previous state from a non-volatile semiconductor memory. The computer system includes flash EEPROM (electrically erasable programmable read only memory) or another non-volatile semiconductor memory for storing hardware configuration and other state information prior to a system power-down. The configuration information is used at power up to reconfigure devices coupled to the processor, such as a hard disk drive controller, video controller, sound card, and so on. Remaining memory in the computer system can be restored either from a hard disk drive (or other mass storage device), or from flash memory. The flash memory may be combined with fast semiconductor memory, such as dynamic random access memory (DRAM) in a module, such that the necessary amount of non-volatile memory may be added whenever fast semiconductor memory is added.

Multibus cached memory system

Abstract: A method and apparatus for use in computer systems utilizes a memory chip employing multiple distributed SRAM caches directly linked to a single DRAM main memory block. Each cache is directly linked to a different bus. Each chip further contains a partially distributed arbitration and control circuit for implementing cache policy and arbitrating memory refresh cycles.

Programmable erasure and programming time for a flash memory

Abstract: A method for controlling the programming and erasure time of a nonvolatile memory array in a memory device. A first value is defined, the first value representing a predetermined number of times a program or erase operation is to be reinitiated on the memory array. A write state machine of the memory device then initiates a program or erase operation on the nonvolatile memory array. The nonvolatile memory array is subsequently verified to determine if the program or erase operation was successful. If unsuccessful, the program or erase operation is repeated either until successful, or until the operation is repeated the predetermined number of times.

Programmable built-in self-test function for an integrated circuit

Abstract: A method and apparatus for providing programmable self-testing in a memory. Registers in the memory are programmed with a sequence of instructions for performing the self-test of the memory. The sequence of instructions is run to perform the self-test of the memory, and the results are checked. The memory includes a clock multiplier which allows the registers to be programmed at a first clock rate, then the memory is tested at a second clock rate which is faster than the first clock rate.

Memory device with programmable self-refreshing and testing methods therefore

Abstract: A programmable self-timed refresh circuit for a semiconductor memory array and methods for programming the self-refresh rate and for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.

Method and integrated circuit adapted for partial scan testability

Abstract: A method and apparatus are taught which modify digital integrated circuits for partial scan testing and do so with little or no impact on the circuit's performance characteristics. Illustratively, the scan memory elements are selected from among all memory elements in a circuit based on their ability to eliminate feedback cycles in the circuit and on considerations of the potential performance degradation due to the inclusion of scan memory elements. A feedback cycle is defined as a feedback path from the output of a memory element to the input of said memory element.