Showing papers on "Mixed-signal integrated circuit published in 1988"

Winner-Take-All Networks of O(N) Complexity

Abstract: We have designed, fabricated, and tested a series of compact CMOS integrated circuits that realize the winner-take-all function. These analog, continuous-time circuits use only O(n) of interconnect to perform this function. We have also modified the winner-take-all circuit, realizing a circuit that computes local nonlinear inhibition.

Integrated circuit chip stacking

Abstract: A device for increasing the density of integrated circuit chips on a printed circuit board. A plurality of integrated circuits are packaged within chip carriers and stacked, on one top of the other, on a printed circuit board. Each of the input/output data terminals, power and ground terminals of the chips are connected in parallel. Each chip is individually accessed by selectively enabling the desired chip.

Knowledge based method and apparatus for designing integrated circuits using functional specifications

Abstract: The present invention provides a computer-aided design system and method for designing an application specific integrated circuit which enables a user to define functional architecture independent specifications for the integrated circuit and which translates the functional architecture independent specifications into the detailed information needed for directly producing the integrated circuit. The functional architecture independent specifications of the desired integrated circuit can be defined at the functional architecture independent level in a flowchart format. From the flowchart, the system and method uses artificial intelligence and expert systems technology to generate a system controller, to select the necessary integrated circuit hardware cells needed to achieve the functional specifications, and to generate data and control paths for operation of the integrated circuit. This list of hardware cells and their interconnection requirements is set forth in a netlist. From the netlist it is possible using known manual techniques or existing VLSI CAD layout systems to generate the detailed chip level topological information (mask data) required to produce the particular application specific integrated circuit.

Design for testability of mixed signal integrated circuits

Abstract: A starting point for a set of design for testability (DFT) principles that can be used with mixed signal integrated circuits is presented. The authors argue that an effective DFT technique should enhance the ability to perform digital signal processing and other modern test techniques on analog macros embedded in the integrated circuit, since quality will be a driving force with increasing integration. The proposed test methodology consists of (1) establishing the digital test model for testing of digital logic and (2) establishing the analog test mode and each of the submodes (called test configurations) for serial or parallel testing of analog partitions. Digital and analog circuitry must be isolated from each other, i.e. an uncontrolled analog signal must not be able to affect the digital test mode and vice versa. >

A symbolic analysis tool for analog circuit design automation

Abstract: An analysis tool has been developed to generate symbolic design equations for analog circuits. This tool (SYNAP) works in conjunction with a symbolic mathematics program (MACSYMA) to create both exact and simplified analytic expressions needed for circuit design and forms the cornerstone of a non-fixed-topology analog circuit design system. SYNAP performs DC, AC, noise, and offset analyses for time-invariant analog circuits with one stable operating point and generates code for the new design system. >

Automated circuit design method

Abstract: An automated technique for the design of microwave and similar circuits using a knowledge based computer system containing a library of fixed-topology circuits and an associated store of knowledge concerning the performance and limitations of these circuits over a variety of operating conditions. The method of the invention permits a relatively unskilled user to specify a circuit by performance parameters only, and to obtain as an end product a coded output that will drive a conventional mask fabrication system used to produce the circuit. Important features of the invention include its use of a unified data structure in which both physical and electrical characteristics of every circuit element are stored together in the rationally consistent manner to facilitate circuit layout, and its use of a circuit compaction procedure that makes use of the unified data structure and minimizes the circuit area without adversely affecting electrical circuit performance.

Design for testability for mixed analog/digital ASICs

Abstract: A description is given of the concept and issues of design for testability for mixed analog-digital circuits, an architecture for testable circuits of this type, general testing procedure, and the concept of analog test tables. The analog test tables contain information such as what parameters are selected for testing, what nodes need to be accessible, and testing conditions. >

How to automate analog IC designs

Abstract: Knowledge-based systems that have made the computer-aided design (CAD) of analog circuits feasible are discussed. The three systems-Idac, Oasys, and Opasyn-were formally announced in 1987. Although they differ widely in philosophy, all use common building blocks and produce sized-schematic diagrams showing how transistors, capacitors, and so forth are connected, complete with the components' values-from which custom circuits can be synthesized. These building blocks, however, unlike the ones used in semicustom analog IC design, are not fixed designs from a library. Rather, they can be varied infinitely, according to rules given to the tools by human experts, so that they approach the ideal performance far more closely than is possible with a limited choice of fixed blocks. All told, Idac, Oasys, and Opasyn can automatically synthesize analog circuits from 13 classes of analog building blocks and can produce over 100 distinct circuit topologies. The characteristics of the three systems are discussed and compared. >

Two-mode driver circuit

Abstract: A CMOS driver circuit for integrated circuits capable of operating in two modes The first, high speed, mode allows the driver circuit on an integrated circuit device to drive the internal signals (12) of the device to the outside world (13) for standard operation of the integrated circuit devices The second mode causes the driver circuit to behave as a weak driver for easily testing the integrated circuit

Single chip integrated circuit computer architecture

Abstract: Microcomputer architecture is provided that facilitates a fully integrated circuit computer on a single integrated circuit chip. The architecture includes use of an integrated circuit ROM for program storage, an integrated circuit RAM or scratch pad memory for alterable operand storage, and integrated circuit logic. Additional architectural features include serial data communication, pulse modulated communication, eight bit instruction bytes, sixteen bit operand words, and shared I/O channels.

CODECS: a fixed mixed-level device and circuit simulator

Abstract: Mixed-level device and circuit simulation allows the use of one- or two-dimensional numerical models for critical devices in a circuit configuration CODECS is a mixed-level device and circuit simulator that has been developed to support a variety of numerical models and analyses capabilities Effective coupling of device and circuit simulation capabilities is achieved by a proper choice of algorithms and architecture Several examples illustrate the advantages of CODECS for simulating both MOS and bipolar circuits >

Development of a switched capacitor based multi-channel transient waveform recording integrated circuit

Abstract: A full-custom integrated circuit addressing the problem of transient analog signal recording is presented. The chip includes 2048 sample-and-hold cells, fast-clock-generation logic, and readout amplifiers. The sample-and-hold circuits are divided into 16 channels of 128 samples per channel. One read amplifier is used per channel. Clock signals are generated by on-chip redundant interleaved shift registers. The circuit is designed in an inexpensive and widely available 3- mu m, single-metal, double-polysilicon CMOS process that allows easy integration of high-density digital and analog circuitry with the possibility of very-low-power operation. Prototypes have been fabricated and proved to be operational. >

Integrated monolithic circuit having a test bus

Abstract: For the testing of an integrated monolithic circuit (IC) the integrated monolithic circuit with a test bus which extends along a functional part of the circuit which is partitioned into macro circuits and which is coupled to the macro circuits, each macro circuit comprising a test interface circuit which is connected in series with test interface circuits of the other macro circuits; via the test interface circuits, the macro circuits can be coupled to the test bus. As a result, macro circuits can be separately tested and in the case of a hierarchic design of integrated circuits, utilizing previously designed marco circuits and test programs for previously designed macro circuits, test development times can be substantially reduced; this is an increasingly important aspect of increasingly complex circuits.

Analog and digital control systems

Abstract: Analog and digital control systems , Analog and digital control systems , مرکز فناوری اطلاعات و اطلاع رسانی کشاورزی

Device for structural testing of an integrated circuit

Abstract: Between a bit line decoder and the memory of an integrated circuit, there is interposed a gate circuit which is cascade-connected with a logic block of the integrated circuit. This arrangement makes possible the structural testing of the integrated circuit. Structural testing means to read and check the response given on the outputs of the logic blocks for a given state imposed on its inputs. This arrangement results in a reduction of the space required on the integrated circuit for testing, when compared with other solutions, which require specific connection circuits. This arrangement is particularly adapted to integrated circuits with a memory and with decoders that provide access to the memory. The arrangement will find particular application in the testing of memory cards where EPROM or EEPROM circuits are used.

An Analog CMOS Backward Error-propagation LSI

Abstract: The design of a novel cascadable CMOS analog IC archi- tecture that implements the Backward Error Propagation algorithm is described, Forward and backward propagation signals coexist simultaneously in this unclocked system, and internal analog weights are stored as charges on capacitors. This IC will speed up convergence of this algo- rithm many orders of magnitude over conventional software implementations, allowing a variety of applications to be tested in layered learning experiments.

Integrated pin electronics for a VLSI test system

Abstract: Drivers, comparators, active loads, and per-pin timing circuitry for a VLSI test system are placed in two CMOS integrated circuits. This level of integration allows fast, low-capacitance pin electronics to be manufactured at relatively low cost. Novel design and calibration techniques are used to overcome limitations of CMOS technology. >

A unified built-in-test scheme: UBIST

Abstract: An original BIST (built-in self-test) scheme is proposed to cover some shortcomings of self-checking circuits and to ensure all tests needed for integrated circuits. In the BIST scheme, self-checking techniques and built-in self-test techniques are combined in an original way and take advantage one from the other. This results in a unified BIST scheme (UBIST), allowing a high fault coverage for all tests needed for integrated circuits, e.g. offline test (design verification, manufacturing test, and maintenance test) and online concurrent error detection. >

1.3- mu m CMOS/bipolar standard cell library for VLSI computers

Abstract: The CMOS/bipolar standard cell library has been enhanced from 2 to 1.3 mu m for application to VLSI computers, such as 32-bit supermini- and microcomputers. This library has macrocells such as a 256-kb/8.4-ns ROM, 32-bit/4.5-ns carry propagation circuits for a 32-bit ALU, 4-kbyte/17-ns cache memory including an address translation function, and a 64-bit/37-ns multiplier. High integration density is obtained by using CMOS-based circuits and fast operation is achieved by using CMOS/bipolar sense circuits and drivers. In the cache memory, a functional sense amplifier, in which a conventional sense amplifier and a comparator are merged, is used. How to combine CMOS and bipolar devices in the macrocells along with application of the library to the VLSI computers is discussed. >

iCOACH: a circuit optimization aid for CMOS high-performance circuits

Abstract: iCOACH is a two-pass iterative circuit optimizer which generates a polycell-based layout from a gate-level description file and user-defined timing constraints The first pass is to place and route the cells and extract the interconnection parameters The second pass optimizes the circuit at the transistor level and makes necessary pitch-matchings Although iCOACH has a layout style similar to the polycell approach, it is distinct in two important aspects First, iCOACH does not rely on any fixed cell library Instead it generates customized cells by invoking the circuit optimizer and performs the transistor-level optimization for both static and dynamic CMOS circuits Second, although the cells in the same row are required to have the same height, different rows can have different heights to make circuit more compact Dynamic circuits are considered, with a careful treatment of reliability issues related to charge sharing and noise margin A novel polycell layout style for dynamic CMOS circuits is introduced A 4-bit ALU and a 32-bit adder are used to demonstrate the capability of iCOACH >

Physical assembly for analog compilation of high voltage ICs

Abstract: A description is given of the aspects of mixed analog and digital physical assembly relevant to analog silicon compilation. The approach addresses system-level analog design automation through silicon compilation; currently this consists of the synthesis of analog and predesigned digital blocks. The compilation is based on successive decompositions of high-level specifications and physical assembly requirements into those of lower level subblocks and devices. The driving applications are high-voltage application-specific integrated circuits (ASICs). Details of analog and system level physical assembly to satisfy a set of mixed analog, digital, and high-voltage requirements are presented together with the results from an implementation of the compiler. >

A field store system with single 1-Mbit field memory

Abstract: A field store system that stores 6-b NTSC video signals sampled at three times the scanning frequency (3 f/sub sc/) was developed using a single 1-Mb field memory is reported. The system uses four ICs: the single field memory, a controller, an analog-to-digital converter, and a digital-to-analog converter. The analog composite video signal is converted to 6-b digital with f/sub sc/ sampling by the analog-to-digital converter (ADC). Because the configuration used for the field memory is 4-b-wide*256 K words, a 6-4 converter converts 4-bit data read from the field memory to 6-b data for the digital-to-analog converter (DAC). The 6-b DAC converts the signal back to analog. The write/read access rate for the memory is 1.5 times faster than the ADC and DAC conversion rate. Special picture effects such as still, strobe, and search can be realized even from a video disk recorded in the constant linear velocity mode. >

CMOS circuit speed optimization based on switch level simulation

Abstract: The authors present a tool for transistor sizing for the purpose of speed optimization. The tool, called SLOP (switch-level optimization), is based on a switch-level simulation program for CMOS circuits. Consequently, the results are always verified by simulation. It gives the delay-area curve and the final sizes of each transistor according to the maximum width limitation specified by the user. Experimental results are presented. The typical improvement in circuit speed is 60%-90% with an area increase of 80%-110%. >

Noise, crosstalk and distortion in mixed analog/digital integrated circuits

Abstract: In mixed analog/digital circuits, op-amp noise, aliased noise, crosstalk from digital circuits, and distortion limit the dynamic range available. Op-amp design, gain partitioning and layout are the key in achieving >25-dB signal-to-noise ratios in an analog path containing 25 op amps. The authors present methods used to maximize dynamic range and measured results obtained from ASIC (application-specific integrated-circuit) devices. >

Semiconductor integrated circuit technology for eliminating circuits or arrays having abnormal operating characteristics

Abstract: In a semiconductor integrated circuit, power lines or ground lines of a plurality of circuit blocks having equivalent functions are coupled via a switch circuit to a common main power line or main ground line on a semiconductor integrated circuit chip or semiconductor wafer. The main power line is supplied with power source potential and said main ground line with ground potential. A switch control circuit selectively switches the switch circuit ON or OFF so that defective circuit blocks may be deactivated.

Integrated circuit testing method and apparatus and integrated circuit devices for use therewith

Abstract: In a so-called "scan-design" arrangement for testing integrated circuits, whether at the device level or at system level, problems associated with the storage and handling of vast amounts of data from increasingly complex devices are addressed by testing a pair of identical integrated circuits simultaneously and using the binary vector generated by scanning one of these integrated circuits as the reference against which to compare the binary vector produced by scanning the other integrated circuit. A plurality of "scan-designed" integrated circuits may be connected in series, possibly in a ring, and each compared with its predecessor. Zero-display coupling across each device may be employed to allow each successive integrated circuit to be compared with the same reference circuit in the chain or ring.

Analog integrated circuit having intrinsic topologies and characteristics selectable by a digital control

Abstract: An integrated analog circuit having a circuit topolo­gy and intrinsic characteristics which may be selected by digital control means is formed by batteries of simi­lar circuit components arranged substantially in paral­lel or in a matrix array, anyone of which may be isola­ted or not by means of a dedicated integrated switch and by alternative interconnection paths among the different circuit components and/or batteries of circuit components, which may be also be selected by closing a relative inte­grated switch. A dedicated nonvolatile memory, integra­ted on the same chip may be permanently programmed and determine a certain configuration of all the integrated switches thus selecting a particular component or more compo­nents of each of said batteries of functionally similar components, and/or selecting a certain intercon­nection path among the different circuit components in order to form a functional integrated circuit having the desired topology and intrinsic characteristics. The integrated nonvolatile memory is programmed by means of a software program which may take as input data the desired values of the different parameters which determine the intrinsic characteristics of the functional analog circuit and the type of functional analog circuit itself.

A mixed-mode analog-digital simulation methodology for full custom designs

Abstract: The authors present a solution to the problem of mixed-mode analog/digital simulation for full custom designs. By efficiently incorporating two specialized simulators-a circuit simulator and a switch-level simulator-in a single computing environment with a common user interface, they have succeeded in simulating full-custom circuits with tightly coupled feedback between the analog and digital portions. The proposed methodology can be applied to a mixed-mode simulation of a purely digital or purely analog circuit in which one portion requires a much higher order of accuracy than the other. >

Challenges in computer-based analysis/simulation and design of power electronic circuits

Abstract: Challenges in the area of analysis/simulation tools for power electronics are outlined, along with a proposal for a hierarchy of tools. It is noted that circuit nonlinearities, wide variations in circuit time constants leading to mathematically stiff circuit description equations, the necessity of being able to obtain the switching instant with high accuracy, and the sensitivity of circuit performance to small parasitics make the task of providing comprehensive simulation very difficult. It is also noted that the design process must be tailored by recognizing that power electronic circuits are different from digital circuits, and hence need a different process. Some essential elements of such a design process are described, and known problems that need to be solved before one can design power electronics circuits completely using computer-based tools are identified. Some of the problems to be addressed in the near future are described. >