Showing papers on "Moore's law published in 2011"

Fifty Years of Moore's Law

Abstract: The 1959 invention of the planar silicon transistor led to the development of the integrated circuit (IC) and the growth trend in IC complexity known as Moore's Law While Moore's observation came in 1965, his original trend line showing a doubling of components per chip each year began with one component in 1959 Thus, we have now experienced 50 years of Moore's Law This paper provides a history of Moore's Law through its many changes and reinterpretations, containing possibly a few new ones as well

The Economic Limit to Moore's Law

Abstract: There have been numerous papers and discussions about the lives and deaths of Moore's Law, all of them dealing with several technological questions. In this paper, we consider economic limitations to the exponential growth of the number of components per chip. As the presented growth model shows, economics constitute indeed a potential slow-down mechanism.

Biologically-inspired massively-parallel architectures — Computing beyond a million processors

Abstract: Moore's Law continues to deliver ever-more transistors on an integrated circuit, but discontinuities in the progress of technology mean that the future isn't simply an extrapolation of the past. For example, design cost and complexity constraints have recently caused the microprocessor industry to switch to multi-core architectures, even though these parallel machines present programming challenges that are far from solved. Moore's Law now translates into ever-more processors on a multi-, and soon many-core chip. The software challenge is compounded by the need for increasing fault-tolerance as near-atomic-scale variability and robustness problems bite harder. We look beyond this transitional phase to a future where the availability of processor resource is effectively unlimited and computations must be optimised for energy usage rather than load balancing, and we look to biology for examples of how such systems might work. Conventional concerns such as synchronisation and determinism are abandoned in favour of real-time operation and adapting around component failure with minimal loss of system efficacy.

Exascale Research: Preparing for the Post-Moore Era

Abstract: Executive Summary • Achieving exascale performance at the end of this decade or the beginning of next decade is essential for progress in science – including progress on problems of major societal impact (such as weather or environmental impact); essential for the continued certification of the nuclear stockpile; and essential to our national security. • The rate of advance in the performance of CMOS technology is slowing down and is likely to plateau mid next decade. No alternative technology is ready for deployment. • Therefore, achieving exascale performance in 20 years may not be significantly cheaper than achieving it in 10 years – even if we could afford the wait. • It is essential (for continued progress in solving major societal problems, nuclear stockpile, security) to have a sustained growth in supercomputer performance and sustained advantage over competitors and potential enemies. • To achieve this continued growth, we need research on (a) using CMOS more efficiently and (b) accelerating the development and deployment of a CMOS replacement. • (a) is (or should be) the focus of exascale research: How to get significantly higher compute efficiencies from a fixed transistor or energy budget. (b) is essential to explore, even if not for exascale in 10 years, as it will be necessary to continue beyond exascale.

Moore's Law in the innovation era

Abstract: Traditional transistor scaling methods served our industry well for more than three decades until the early 1990s when leakage current and active power constraints threatened to end the continued improvements provided by Moore's Law. The end of the traditional scaling era ushered in the beginning of the innovation era. Process technology innovations such as strained silicon, high-k metal gate transistors, and copper + low-k interconnects have enabled continued performance improvements for scaled devices. Microprocessor design and architecture innovations such as multi-core designs combined with power gates were significant contributors to improved performance and improved power efficiency. Future computing products demand small form factors and long battery life that can be met through a combination of transistor innovation, System-on-Chip and System-in-Package integration techniques.

CMOS nanoelectronics at the time of diversifications

Abstract: Nanoelectronics linear scaling appeals for new 3D integration schemes enabling to continue Moore's law. Unique opportunities exist to increase the devices performances, system complexity and reduce power consumption of mobile, handheld objects. Devices other than CMOS can be co-integrated with CMOS to interface the outside Multiphysics world (MEMS, sensors and actuators, RF devices, power devices,…) allowing new functionalities. 3D Wafer Level Packaging and System on a Wafer pave the way to these new routes.

Energy-Aware System Design: Algorithms and Architectures

Abstract: Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moores law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints. Energy-Aware System Design: Algorithms and Architectures provides state-of-the-art ideas for low power design methods from circuit, architecture to software level andoffers design case studies in three fast growing areas of mobile storage, biomedical and security.Important topics and features:- Describes very recent advanced issues and methods for energy-aware design at each design level from circuit andarchitecture toalgorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level- Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts - Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency- Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camera systems.Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.

Scaling-Up Microelectronic Production: Multinational Corporations Under Moore's Law

Abstract: Microelectronics is a special type of General Purpose Technology (GPT), bringing disruptive innovations, not in one shot, but by successive waves for 40 years. Rational innovators maximize present value, over product cycles, before the anticipated obsolescence under Moore’s Law. Among the multiple local maxima, the proven best dynamic option may be a two-phase, scaling-up plan at two-sites: high-skill workers improvise in pilot production, and debug the production process; low-wage labor mass-produce by prepared routines, on costly equipment. This study yields new insights: outsourcing to multiple sites can be complementary, inter-temporally; multinational corporations excel in coordinating the unilateral, product-specific, cross-border information transfers, hierarchically. This analysis is deduced from the documented practice of two dominant firms: Seagate Technology in the vertically integrated hard-disk-drive (HDD) industry; the Hon Hai-Foxconn Group, with more than half of the world market share of the electronics manufacturing service (EMS) industry. This framework may help to interpret the economic co-evolution of America, China, Japan and Taiwan – the intermediary in between.

More than Moore or More Moore: a SWOT analysis | NIST

Abstract: Over the last decade, the world of semiconductors has broadened its horizon from More Moore to More than Moore. Some first hypothesized the end of Moore’s law and the beginning of a new era. They saw it as an OR gate while some saw it as a NOR gate. Since then it has been an AND gate as Moore’s law has continued to move down it’s persistent scaling path. Even if it fades, i.e. the end of More Moore, both will technologies will flourish. The reason is that More than Moore is complementary to More Moore semiconductor technology. More than Moore is largely made up of MEMS, which integrate microelectronics with micromechanical structures. Some include 3D packaging, LEDs, and Photovoltaic cells into the mix. In the future there are NEMS, or Nano-ElectricalMechanical-Systems. In all cases the use manufacturing methods and metrology evolved from semiconductors. Metrology is critical to all these technologies, because to make something, you must be able to measure it, and to do that you must be able to see it. This presentation examines the Strengths, Weaknesses, Opportunities and Threats (SWOT) for both classical semiconductor markets and these emergent technologies. It delves into how their technologies are evolving and the economic impact of this evolution. It addresses such questions as: • Is scaling measurably slowing? • Are design costs getting too high? • What are the critical factors for a Moore’s Wall scenario? • As chips become an ever big-player game, will there be enough research centers to support metrology development. • How fragmented is the More than Moore Market? • Who are the leading players? • Will they cross the valley of death from MEMS to Bioelectronics?

Work around Moore’s Law: Current and next Generation Technologies

Abstract: Interconnect dimensions and CMOS transistor feature size approach their physical limits, therefore scaling will no longer play an important role in performance improvement. So, instead of trying to improve the performance of traditional CMOS circuits, integration of multiple technologies and different components in a heterogeneous system that is high performance will be introduced “moore than more” and CMOS replacement”beyond CMOS” will be explored. This paper focuses on Technology level trends where it presents “More Moore”:New Architectures (SOI, FinFET, Twin-Well),”More Moore” :New Materials (High-K, Metal Gate, Strained-Si) ,”More than Moore”:New Interconnects Schemes (3D, NoC, Optical, Wireless), and ”Beyond CMOS” :New Devices (Molecular Computer, Biological computer, Quantum Computer) .

Challenges of future silicon IC technology

Abstract: The silicon IC technology continues to scale following Moore's law for over fifty years. Now, we are approaching a critical crossroad as we are about at the limit of conventional optical lithography — the enabler of our business. Besides lithography, new materials, device structures, and interconnect schemes must also be developed in order to keep us on the scaling curve. In addition, we not only have to follow the laws of physics but also those of economics: device manufacturing cost can not increase out of proportion from one generation to the next.

Bridging Lithography Processes with NAND Flash ECC Complexity

Abstract: The NAND Flash memory is the technological driver for both critical dimensions scaling and process technologies. In order to keep pace with the Moore's Law, the scale chip dimensions decrease to the point where variability effects become significant. Particularly, when printed features go down below the 20 nm, transistors structures are strongly affected by pattern roughness caused by the randomness in advanced lithographies (e.g. Extreme UV), leading to variability induced data errors in the memory functionality. Two treatments for variability are known: roughness smoothing processes at the process stage and on-chip error correcting algorithms. This paper describes a holistic framework, which trades-off between lithography processes and error control codes complexity to ensure data integrity in probabilistic 16 nm memories.

Extension of Moore's Law via Strained Technologies- The Strategies and Challenges

Abstract: In order to extend the Moore’s law, the interests have been devoted to several different areas, such as the use of strained technology, the high-k/metal-gate, high mobility channel materials etc. Among these efforts, strained technology seems to be the most successful one for its development over several generations and more Moore becomes the most recent interest. However, the reliability and variability become a great concern. In this paper, we will first give an overview on the strainsilicon technology, such as eSiGe, eSi:C, stress memorization technique (SMT), dual stress liners (DSL), and replacement highk/metal-gate (RMG) process, after the 90nm CMOS generation. Then, the reliability and the design guideline for a trade-off between performance and reliability will be addressed. A technology roadmap in terms of the ballistic transport theory will be outlined. Then, the variability of the strained CMOS devices with focus on the experimental discrete dopant profiling will be demonstrated. Finally, the strategies and challenges of strainedsilicon devices on advanced 3D device structure and IC will be discussed.

Moore's law and the impact on trusted and radiation-hardened microelectronics.

Abstract: In 1965 Gordon Moore wrote an article claiming that integrated circuit density would scale exponentially. His prediction has remained valid for more than four decades. Integrated circuits have changed all aspects of everyday life. They are also the 'heart and soul' of modern systems for defense, national infrastructure, and intelligence applications. The United States government needs an assured and trusted microelectronics supply for military systems. However, migration of microelectronics design and manufacturing from the United States to other countries in recent years has placed the supply of trusted microelectronics in jeopardy. Prevailing wisdom dictates that it is necessary to use microelectronics fabricated in a state-of-the-art technology for highest performance and military system superiority. Close examination of silicon microelectronics technology evolution and Moore's Law reveals that this prevailing wisdom is not necessarily true. This presents the US government the possibility of a totally new approach to acquire trusted microelectronics.

Full-Throttle DSL

Abstract: Broadband connectivity and new ser vices such as YouTube, IP video, and cloud computing are changing our lives, and we would never want to miss out on them. The associated data rates are as predictable as Moore's law, as they are enabled by the availability of low-cost, highly integrated broad band communication ICs. Advanced modulation and coding incorporating sophisticated adaptive signal processing techniques are pushing the data rate close to the theoretical limit given by Shannon's law. Important advantages such as increased bandwidth, improved energy efficiency, feature enhance ment, and cost reduction are conferred by innovations in integrated circuits and technologies. Finally, standardization with the involvement of semiconductor and telecom system companies and also service and content providers is most important for the success and deployment of new communication technologies and services.

A novel methodology for architecture-level exploration of 3D SoCs

Abstract: Three-dimensional (3D) integration is an emerging technology that is expected to lead to tremendous benefits in terms of power, delay and silicon area. Moreover, 3D technology continues interconnect advances beyond the CMOS scaling predicted by Moore's Law, which enable new capabilities not available in 2D ICs. This paper proposes a physical design framework that enables rapid evaluation of 3D SOCs under different optimization goals. For demonstration purposes we apply the proposed framework for the 3D physical design of an embedded processor. Experimental results shown that 3D integration can alleviate the constraints posed by increased wire-length, such as power consumption, by about 20% compared to the 2D implementation.

Performance Evaluation of Intel and Portland Compilers Using Intel Westmere Processor

Abstract: In recent years, we have witnessed a growing interest in optimizing the parallel and distributed computing solutions using scaled-out hardware designs and scalable parallel programming paradigms. This interest is driven by the fact that the microchip technology is gradually reaching its physical limitations in terms of heat dissipation and power consumption. Therefore and as an extension to Moore’s law, recent trends in high performance and grid computing have shown that future increases in performance can only be reached through increases in systems scale using a larger number of components, supported by scalable parallel programming models. In this paper, we evaluate the performance of two commonly used parallel compilers, Intel and Portland’s PGI, using a state-of-the-art Intel West mere-based HPC cluster. The performance evaluation is based on two sets of experiments, once evaluating the compilers’ performance using an MPI-based code, and another using OpenMP. Our results show that, for scientific applications that are matrices-dependant, the MPI and OpenMP features of the Intel compiler supersede PGI when using the defined HPC cluster.

Physical design exploration of 3DIC wireless transceiver using through-si-vias

Abstract: 3DIC's, the flagship for the “More than Moore Law” movement are already an integral part of the Semiconductor and Manufacturing industry and lot of investigations are going on within different sectors of the industry to efficiently fabricate 3DIC's. If you peep deep into the design process, everyone is trying to make it upward compatible with the 2D design for effective reusability. The methodology to design and verify the 3DIC involves a collaboration of different people from EDA, CAD, Physical design, Fabrication, TSV and Modeling departments. Different aspects need to be considered for the 3DIC apart from the miniaturization and the resulting space, cost & signal loss savings. The considerations include Power & clock Distribution, Thermal analysis, EMI, ESD protection scheme etc. This paper focuses on the physical design process steps carried out to develop a 3DIC Wireless Transceiver and it throws light into some of the process intricacies which are faced while carrying out the design and verification of such an IC stacking.