Showing papers on "MOSFET published in 1977"

Very small MOSFET's for low-temperature operation

Abstract: The improvements in the device characteristics of n-channel MOSFET's that occur at low temperatures are considered in this paper. The device parameters for polysilicon gate FET's with channel lengths of the order of 1 µm have been studied both experimentally and theoretically at temperatures ranging from room temperature down to liquid nitrogen temperature. Excellent agreement was found between the experimental dc device characteristics and those predicted by a two-dimensional current transport model, indicating that device behavior is well understood and predictable over this entire temperature range. A device design is presented for an enhancement mode FET with a channel length of I µm that is suitable for operation at liquid nitrogen temperature.

Fabrication method for integrated circuits with polysilicon lines having low sheet resistance

Abstract: A method and structure for polysilicon lines which include a silicide layer for providing a low sheet resistance. The invention may be employed in a polysilicon gate MOSFET process for integrated circuits as well as other integrated structures. In the method a first layer of polysilicon is deposited followed by a deposition of a metal of the silicide forming type. Another polysilicon layer is then deposited on top of the silicide forming metal to produce a three layer structure. The three layer structure is subjected to heat, for example, during the reoxidation step in a gate fabrication process, the metal reacts with the polysilicon at two reaction fronts to form a silicide. The resultant silicide has a much lower resistivity than doped polysilicon and therefore provides a second conductive layer which can be used more compatibly and efficiently in connection with the normal metal layer employed in integrated circuits to give a two-dimensional degree of freedom for the distribution of signals.

Double boron implant short-channel MOSFET

Abstract: Threshold voltage and current-voltage characteristics are presented for a double boron-ion-implanted-n-channel enhancement MOSFET device for high speed logic circuit applications. A 15-Ω. cm-high resistivity p-type

Electrical properties of the Si–SiO2 interface and its influence on device performance and stability

Abstract: The two electrically active centers at the Si–SiO2 interface which can influence the performance and stability of MOSFET’s and bipolar transistors used in integrated circuits are interface traps and fixed charges. This paper is a brief review of the properties of interface traps and fixed charge, how these electrically active centers affect silicon device characteristics, and the largely empirical methods used to control the densities of these centers. These methods have been so successful that interface traps and fixed charge show no performance and stability problems in many types of integrated circuits.

Grooved Gate MOSFET

Abstract: Grooved Gate type MOS FET's which realize a short channel device with high punch-through breakdown voltage and little threshold voltage (VT) fluctuation, are fabricated by using a promising photoresist technique. A proposed, self-aligned gate MOS FET structure (Grooved Gate MOS FET) is based on two-dimensional analyses of short channel devices. A characteristic feature of the device is negative source and drain junction depth. The fabricated 21 stage ring oscillator displays a high circuit performance for delay and power product of 0.12 pJ.

Dopant profiles determined from enhancement‐mode MOSFET dc measurements

Abstract: Simplified algorithms are described which allow the determination of the dopant profile in the gate region of a four‐terminal enhancement‐mode metal‐oxide‐silicon field‐effect transistor (MOSFET). The method calls for the dc measurement of the source‐body voltage VSB as a function of the gate‐source voltage VGS for a fixed minority‐carrier channel current. The profile depth is proportional to dVSB/dVGS and the dopant density is inversely proportional to d2VSB/dV2GS. Only the oxide and silicon dielectric constants and the oxide thickness are needed in the computations. The data acquisition was computerized and includes the use of an operational amplifier circuit. The method is illustrated by the profile of a phosphorus layer implanted in an n‐type silicon substrate.

A transistor method for measuring changes in double layer potentials

Abstract: A standard silicon device, the metal oxide semiconductor field effect transistor (MOSFET), has been modified by replacing the metal gate electrode with a conducting electrolyte solution. It is shown that this device has the capability of measuring changes in the total double layer potential at the electrolyte/insulator interface. Preliminary results for the SiO 2 /electrolyte interface show changes considerably less rapid than those predicted by the Nernst equation.

A new short channel MOSFET structure (UMOST)

Abstract: A new MOSFET structure with a trapezoidal U-shaped channel defined by anisotropic etching is described. The structure results in very short channel devices almost free of short channel effects and achieves higher speed without the use of submicron photolithography. A simplified theory for the structure is presented and compared with experimental results obtained on 1–10 μm channel length devices. This structure may prove useful in the study of conduction in short channel MOSFETs without introducing the complicating two dimensional short channel effects.

Manufacturing a low voltage n-channel MOSFET device

Abstract: A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.

Complementary MOSFET device

Abstract: A CMOS FET device having a P well layer diffused in an N type semiconductor substrate, a P channel MOS transistor formed on the N type semiconductor substrate, and an N channel MOS transistor provided in the P well layer, wherein the source of the P channel MOS transistor is made to have the same potential as the N type semiconductor substrate and for the source of the N channel MOS transistor is made to have the same potential as the P well layer, thereby suppressing the operation of a parasitic bipolar transistor whose base is constituted by the N type semiconductor substrate and/or a parasitic bipolar transistor whose base is formed of the P well layer.

An Introduction to Silicon Inversion Layers

Abstract: In this article the inversion layer, a gas of electrons (or holes) formed at the surface of p (or n) type silicon by an electric field, is described. Inversion layers are of importance as they form the basic of operation of surface controlled devices such as the metal-oxide-silicon field effect transistor (MOSFET), the metal-nitride-oxide silicon memory transistor (MNOS) and the more recently introduced charge coupled device. At low temperatures the inversion layer is electrically decoupled from the bulk silicon and possesses considerable advantages for the investigation of transport phenomena. These stem from the two dimensional nature of the electron gas imposed by the surface potential well and the direct electrical control of the carrier concentration and Fermi energy. The nature of the Si-SiO2 interface is considered end also some of the experimental methods used for obtaining information about its electronic properties. Both room temperature and low temperature properties of the MOS device ...

Constant voltage circuit comprising an IGFET and a transistorized inverter circuit

Abstract: A constant voltage circuit comprises an IGFET for deriving an output voltage for a load from a power supply and an inverter circuit responsive to the output voltage for controlling the IGFET in a negative feedback manner to stabilize the output voltage against fluctuations in the supply voltage and the load. The IGFET may be a depletion or an enhancement MOSFET. The inverter circuit preferably comprises an enhancement and a depletion or an enhancement MOSFET. Either a resistor or another IGFET may be connected between the inverter circuit and ground. The constant voltage circuit is readily manufactured as an IC together with an IGFET circuit used as the load.

A low input capacitance voltage follower in a compatible silicon-gate MOS-bipolar technology

Abstract: Using a compatible silicon-gate p-MOS-bipolar technology (SIGBIP), a voltage follower is described with protected MOSFET input stage featuring less than 1-pA input current, less than 0.1-pF input capacitance, 10-MHz bandwidth, 20-/spl mu/V p-t-p noise from 1 Hz to 100 kHz. Offset drift is less than 30 /spl mu/V//spl deg/C. The circuit is based on a new very high-gain differential stage which allows full bootstrapping of all its input capacitances. The circuit measures only 0.9 mm/SUP 2/ and is mounted in a 4-pin TO-18 package. The circuit can successfully be used for charge measurements, and especially for wide-band measurements from very high impedance sources (>10 M/spl Omega/) as occurring in bioelectronics, biochemistry, etc.

Mos type semiconductor device

Abstract: PURPOSE:To reduce the generation of carriers due to an impact ionization, to impress the change of the potential of a section where one of carriers generated is integrated at a minimum even on the integration of one of carriers generated in the first conduction type semiconductor layer and to increase the conductance of a MOSFET by extending a depletion layer in a second conduction type second semiconductor layer and weakening the field strength of the depletion layer. CONSTITUTION:A low-concentration N impurity layer 8 extends a depletion layer in a high-concentration N impurity layer 3 for a drain and weakens field strength in the depletion layer, and reduces the generation of carriers causing the lowering of source-drain withstanding voltage. A high-concentration P impurity layer 9 prevents the lowering of built-in voltage between a high-concentration N impurity layer 2 for a source and a P-type silicon substrate 1 even when holes in carriers generated are integrated to the front surface of the high-concentration N impurity layer 2 for the source, and obviates the inflow of electrons to the P-type silicon substrate 1 from the high-concentration N impurity layer 2 for the source. Accordingly, the increase of withstanding voltage, that is, fining-of a MOSFET is realized, and reliability is improved.

Field-effect transistor of high dielectric strength

Abstract: PURPOSE: To prepare the MOSFET of high dielectric strength by covering the upper portion of the surface of a substrate between a gate electrode and a drain layer with a shielded electode through a layer containing impurities at a low concentration. COPYRIGHT: (C)1978,JPO&Japio

Combined transistor integrated circuit - has N-MOS, CMOS, D-MOS JFET and bipolar transistor on same silicon chip

Abstract: The integrated circuit combines MOSFET, CMOSFET, DMOSFET, JFET and bipolar transistors on the same silicon ship using a sequence of processes so that analog functions can be performed as well as digital. All the components have the same p-type substrate. N-type zones are formed by implantation and diffusion. The insulating regions for the p-channel JFETs and MOSFETs and the collector regions of npn bipolar transistors are formed in these zones.

Silicon MESFETs for improved VHF and UHF mixer performance

Abstract: Silicon MESFET devices were evaluated for their potential to improve conventional VHF and UHF communication systems based on reported high frequency capabilities and theoretical square law operation. MESFET and MOSFET discrete devices of the same geometry were tested in RF circuits to compare performance. The MESFET devices were clearly superior to the MOSFET devices at VHF and UHF frequencies in terms of noise figure, gain bandwidth product, and range of square law operation. An experimental TV receiver was constructed with silicon MESFET devices for several functions. One double balanced MESFET mixer was used for both VHF and UHF bands. The mixer had +2 db of conversion gain and could handle two + 4 dBm signals with -40 db third order intermodulation products.

Method of manufacteuring insulating gate type field effect transistor

Abstract: PURPOSE:To accurately set the short channel length of the double diffusion type MOSFET by performing the formation of the base area by the ion injection method.

MOS switch with hysteresis

Abstract: An MOS circuit possessing hysteresis and positive feedback for fast switching includes a first MOSFET having its gate connected to an input. A second depletion mode MOSFET has its drain connected to the source of the first MOSFET and its source connected to ground. A third depletion mode MOSFET has its drain connected to the source of the first MOSFET and its gate and source connected to the drain of a fourth MOSFET and to the gate of a fifth MOSFET. The gate of the fourth MOSFET is connected to the gate and source of a sixth depletion mode MOSFET and to the drain of the fifth MOSFET. The fifth MOSFET has its source connected to ground.

Circuit for detecting battery voltage

Abstract: PURPOSE:To provide a circuit for detecting the voltage of batteries in electronic clocks, etc. without being affected by temperatures by using a difference amplifying circuit, containing the MOSFET, one input terminal of which circuits is connected to a voltage dividing circuit, and the other to a constant-voltage source.

Synchronisation separator for recorded composite TV signals - has two MOSFET switches allowing easy setting of separation level

Abstract: The synchronisation pulse separator, for recorded composite TV Signals, has the composite signal passing one way directly to a first MOSFET changeover switch and the other way via a clamping MOSFET switch to the second input of the first switch. The first switch is controlled by the blanking pulses and its output contains the composite signal minus the synchronisation pulses. The control signal for the clamping switch is derived from the composite signal. The advantage lies in the cut-out level for synchronisation pulse separation being easily set and stable.

Rapid determination of semiconductor doping and flatband voltage in large MOSFET's

Abstract: A simple method is presented for accurate determination of the semiconductor doping concentration, flatband voltage, and gate‐oxide thickness from capacitance measurements on large MOSFET’s. Conventionally, MOS capacitors are used to determine the doping profile from deep‐depletion capacitance measurements, which unfortunately require a rapidly varying voltage across the capacitor. It is demonstrated that gate‐substrate capacitance of MOSFET’s can be measured conveniently in deep depletion with a slowly varying gate‐substrate bias. This is accomplished by reverse biasing the source and drain diodes to prevent the buildup of minority carriers at the semiconductor surface under the gate area. Measurements on MOSFET’s fabricated on n‐type 〈111〉 Si gave ND=4.1×1014/cm3, VFB=−1.5 V, and tox=1064 A, in agreement with resistivity, voltage threshold, and ellipsometry measurements, respectively.

High performance inverter circuits

Abstract: The invention disclosed herein is a high performance inverter circuit using MOSFETs having varying threshold voltages produced by selectively varying ion implantation doses in the channels of the MOSFETs and using a slightly depletion type MOSFET, rather than a conventional depletion type, in the output stage.

Semiconductor integrated circuit

Abstract: PURPOSE:To suppress ringing by absorbing a nose generated at the time of driving at a high speed a large capacity load connected to a semiconductor integrated circuit, by a capacitor provided between power source lines in the integrated circuit. CONSTITUTION:Output buffers f0-f7 which become loads are connected to a semiconductor integrated circuit. Also, between a power source line Lv and Le, a MOSFET Mr and a capacitor Cg are connected. An FET Mr is an N channel type and turned on by connecting the gate to the power source Lv, and operates as a resistance of a time constant circuit. The capacitor Cg bypasses a high frequency component through a power source Vcc, and stabilizes a level of the line Le. An input signal of output buffers f0-f7 rises to an H level from an L level, a MOSFET Mb (Mb0-Mb7) is turned on, and when charge stored in loads Cl0-Cl7 is discharged, its charge is stored temporarily in the capacitor Cg, and thereafter, discharged gradually through inductances lg, ls. In such a way, the generation of a current noise is prevented, and ringing is suppressed.

A short channel MOSFET model

Abstract: The MOSFET equivalent circuit model described incorporates short channel and temperature effects. It includes expressions for the device current in the subthreshold, triode and saturation regions and uses a field dependent mobility and a drain voltage dependent threshold voltage. The drain current-voltage characteristic and its first derivative are continuous in all regions. Relationships for the gate-source and gate-drain capacitances are derived as a function of the device potentials using a field dependent mobility. Using the closed form expressions of this model, simulations were performed for micron long devices having uniform and ion-implanted channel profiles and compared with data at room, above room and liquid nitrogen temperature.

C-mos circuit of high voltage operation

Abstract: PURPOSE:To obtain the output voltage of high potential with the input signal of low voltage, by constituting C-MOS inverter circuit with MOSFET of P and N channel, further providing N channel MOSFET and applying the input signal of opposite phase to the gate. CONSTITUTION:C-MOS circuit is constituted with the P channel MOSFET T21 200V or more in dielectric strength and the N channel MOSFET T22 having the same breakdown voltage. Further, branching resistors R21 and R22 are provided, the junction point is connected to the gate of the element T21, and one end is connected to the gate of the element T22 via the inverter INV consisting of C-MOS via the N channel MOSFET T23. With this constitution, the power supply VDD is applied to the element T21 and the resistor R21, and when the input VIN is fed to the element T23 and the inverter INV, high voltage output signal having opposite phase as the input signal is appeared at the output Vout.

Constant voltage supply system - uses MOS devices coupled in stabilising chain for high performance

Abstract: A highly accurate and stable voltage supply is provided using MOS devices for digital circuit applications. The first stabilising stage consists of an MOSFET in series with a resistor (R1) and coupled to the supply voltage (VD). Further stabilising stages are provided with an MOSFET (T3) controlled by the output of the first stage (V1) over a second transistor (T2). The two transistors (T2, T3) are complimentary. Additional stabilising stages (T4, T5), (T6, T7) provide the level of performance required.

Semiconductor integrated circuit and process for production of the sam e

Abstract: PURPOSE:To simultaneously form an n-channel MOSFET and bipolar transistor on one substrate by using anisotropic etching, and prevent impairment of their characteristics.