Showing papers on "MOSFET published in 2023"
5 citations
TL;DR: In this paper , a novel analytical loss formulation was proposed to predict the efficiency of three-phase inverters using silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs).
Abstract: This paper presents a novel analytical loss formulation to predict the efficiency of three-phase inverters using silicon carbide (SiC) metal—oxide—semiconductor field-effect transistors (MOSFETs). The proposed analytical formulation accounts for the influence of the output current harmonic distortion on the conduction losses as well as the impact of the output parasitic capacitances and the deadtime on the switching losses. The losses are formulated in balanced conditions to select suitable SiC MOFETs for the desired target efficiency. To validate the proposed methodology, a 3-phase inverter is designed to present full load efficiency in excess of 99% when built using SiC MOSFETs antiparalleled with SiC Schottky diodes selected for the specified full load efficiency. Experimental assessment of the designed inverter efficiency is compared with the expected values from the proposed analytical formulation and shown to match or exceed the predicted results for loads ranging from 40% to 100% of full load.
4 citations
TL;DR: In this article , a closed-loop active gate driver (AGD) based on the printed-circuit-board (PCB) Rogowski Coil is proposed for optimizing the switching performance of SiC.
Abstract: The superior characteristics of the silicon carbide metal-oxide-semiconductor field-effect transistor (SiC mosfet ) allow its wide use for improving the efficiency and power density of power electronic systems. However, the higher switching speed exacerbates the problems of overshoot, oscillation, and electromagnetic interference (EMI), which need to be properly addressed. In this article, a novel stage-detection closed-loop active gate driver (AGD) based on the printed-circuit-board (PCB) Rogowski Coil is proposed for optimizing the switching performance of SiC mosfet s. And its stage identification threshold design can weaken the influence of the varying nonlinear parameters, especially for the turn- on process. First, the gate driver trajectory and the switching process of the SiC mosfet are analyzed. The optimal driver parameter dynamic configuration among the existing stage-control schemes is defined and unified, which aims to optimize the tradeoff between the overshoot and switching loss. Then, the parameter design of the PCB Rogowski Coil is illustrated. And the operation principle and working process of the proposed AGD are introduced. Finally, the performance of the proposed AGD and the effectiveness of the stage-control schemes are verified in the double-pulse test under different conditions. The experimental results show that the proposed AGD can not only reduce the overshoot and suppress the oscillation but also optimize the compromise of the switching loss and switching time.
4 citations
TL;DR: In this paper , the authors studied quantum effects on MOSFET in fractal dimensions based on the concept of "product-like fractal measure" introduced recently in literature by Li and Ostoja-Starzewski.
Abstract: The MOSFET is a semiconductor microelectronic single-chip used in different technical aspects in computer engineering and nanotechnology. However, there are many self-assembly micro- and nano-electronic processes generating fractal patterns where millions of metallic nanoparticles are self-assembled into fractal electronic circuits. This proves the importance of fractals in nano-devices such as MOSFET. In this letter, we study quantum effects on MOSFET in fractal dimensions based on the concept of "product-like fractal measure" introduced recently in literature by Li and Ostoja-Starzewski. This study shows that fractal quantum mechanical effects occurring in micro- and nanoelectronics deserve to be considered seriously. Graphical abstract Variations of the electric potential for different values of fractal dimensions.
4 citations
TL;DR: In this article , a voltage-dependent formulation for highvoltage (HV) and low-voltage MOSFETs is proposed to capture the carrier velocity saturation effect in the drift region of HV transistors.
Abstract: This brief presents a compact model to capture the major difference between high-voltage (HV) and low-voltage MOSFETs, i.e., the carrier velocity saturation effect in the drift region of HV MOSFETs. We discuss the numerical and behavioral issues that can arise in SPICE simulations with the existing current-dependent formulation in Berkeley-Short-Channel-IGFET model (BSIM) for HV transistors. We then demonstrate how a voltage-dependent formulation can mitigate them without losing simplicity and accuracy. We also validate the proposed model against experimental data of HV transistors.
3 citations
TL;DR: In this article , a source field plate design with an air gap has been studied on a lateral β-Ga2O3 MOSFET with the objective of achieving improvement in high power as well as RF performance by employing exhaustive TCAD simulations.
Abstract: In the present work, source field plate design with an air gap has been studied on lateral β – Ga2O3 MOSFET with the objective of achieving improvement in high power as well as RF performance by employing exhaustive TCAD simulations. A comprehensive investigation of various analog Figure of Merits (FoMs) and RF Figure of merits (FoMs) have been carried out and a thorough comparison has been drawn between the proposed device β-Ga2O3 MOSFET with source field plate and air gap, the β-Ga2O3 MOSFET with gate field plate and the conventional β-Ga2O3 MOSFET. It can be noted that the proposed design yields significantly higher breakdown voltage and Power Figure of Merit (PFoM) as compared to gate field plate design and conventional device without any of these designs and also, the proposed design demonstrates improvement in RF performance as compared to gate field plate design.
3 citations
TL;DR: In this article , a scalable converter-based self-powered (SCS) gate driver is further proposed, which exhibits simplification of basic topology and sufficient gate driver power handling capability regardless of the switching requirement of main loop power device.
Abstract: In the hardware design of battery energy storage system (BESS) interface, in order to meet the high-voltage requirement of grid side, integrating 10-kV silicon-carbide (SiC) MOSFET into the interface could simplify the topology by reducing the component count. However, the conventional gate driver design is challenging and inextensible in BESS, since the high-voltage rating and high dv/dt bring the requirements of high-voltage isolation and low common-mode capacitance. Therefore, in this article, a scalable converter-based self-powered (SCS) gate driver is further proposed. A 5-kV input power extracting converter based on a voltage-balanced SiC MOSFET stack is constructed to self-power the gate driver, which exhibits simplification of basic topology and sufficient gate driver power handling capability regardless of the switching requirement of main loop power device. Besides this, the power extracting converter is designed to act as a clamping resistor-capacitor-diode (RCD) snubber circuit, which makes the SCS gate driver scalable to the series connection of power devices. Analysis and design consideration are given in detail, followed by the experimental verification using 10-kV/10-A SiC MOSFETs.
3 citations
TL;DR: In this paper , the authors proposed a compact-interleaved package for high-temperature SiC power devices, which can handle three key considerations: packaging parasitic parameters, direct electrode measurement structure, and packaging materials.
Abstract: Due to the outstanding material properties, silicon carbide (SiC) power device is the most promising alternative to silicon devices and can work at higher junction temperature. However, existing packaging technologies obstruct the use of SiC devices at high temperature and impede the continued exploration of SiC devices in high-temperature applications. This article proposes a novel hermetic metal packaging method called compact-interleaved package. The compact-interleaved power module handles the mentioned problems from three key considerations: packaging parasitic parameters, direct electrode measurement structure, and packaging materials. Based on the elaborate high-temperature double pulse test platform, dynamic characteristics of 1.2-kV/13-mΩ 4H-SiC power mosfet are studied under the condition of extremely high junction temperature (up to 550 °C) and extremely high switching speed (about 3 kA/μs). The dynamic characteristics of SiC mosfet are theoretically analyzed and verified by experimental measurements. Compared with other SiC bipolar devices, SiC mosfet maintains outstanding dynamic characteristics at extremely high temperatures and has an optimal operating high-temperature range. Finally, this article demonstrates an extreme-high-temperature power electronic converter to verify the superiority of the packaging method, and also proves the extreme-high-temperature power converting capability of SiC mosfet .
3 citations
TL;DR: In this article , the authors proposed a general framework to automatically derive analytical solutions for surface potential in MOSFETs by leveraging the universal approximation power of deep neural networks, and applied the derived potential function to the building of 130 nm MOS-FET compact models and circuit simulation.
Abstract: The continued scaling-down of nanoscale semiconductor devices has made it very challenging to obtain analytic surface potential solutions from complex equations in physics, which is the fundamental purpose of the MOSFET compact model. In this work, we proposed a general framework to automatically derive analytical solutions for surface potential in MOSFET, by leveraging the universal approximation power of deep neural networks. Our framework incorporated a physical-relation-neural-network (PRNN) to learn side-by-side from a general-purpose numerical simulator in handling complex equations of mathematical physics, and then instilled the “knowledge’’ from the simulation data into the neural network, so as to generate an accurate closed-form mapping between device parameters and surface potential. Inherently, the surface potential was able to reflect the numerical solution of a two-dimensional (2D) Poisson equation, surpassing the limits of traditional 1D Poisson equation solutions, thus better illustrating the physical characteristics of scaling devices. We obtained promising results in inferring the analytic surface potential of MOSFET, and in applying the derived potential function to the building of 130 nm MOSFET compact models and circuit simulation. Such an efficient framework with accurate prediction of device performances demonstrates its potential in device optimization and circuit design.
2 citations
TL;DR: In this article , the improvement of SiC power MOSFET performance achieved using high-κ gate-dielectrics instead of the standard SiO2 is investigated by means of advanced gate-impedance characterization.
Abstract: In this work, the improvement of SiC power MOSFET performance achieved using high-κ gate-dielectrics instead of the standard SiO2 is investigated by means of advanced gate-impedance characterization. The benefit of using high-κ gate-dielectrics with high dielectric constant is demonstrated by comparing SiC MOSFETs with pure high-κ, a stack of SiO2/high-κ, as well as pure SiO2. Namely, the fabricated high-κ SiC MOSFETs show a superior performance to commercial SiC MOSFETs with SiO2/SiC interface with respect to channel resistance and interface quality. The proposed characterization approach is non-destructive and applicable to packaged power devices.
2 citations
TL;DR: In this paper , the authors investigated the effects of temperature fluctuation on the noise parameter performance, and the Hot-Carrier Injection (HCI) degradation of the device Recessed Source/Drain Junctionless Gate All Around (Re-S/D-JL-GAA) and JL GAA MOSFETs.
TL;DR: In this paper , the authors examined the responses of radiation-sensitive p-channel MOSFETs to irradiation and subsequent annealing at room temperature and higher temperatures to investigate their use as a dosimeter for measuring ionizing radiation.
TL;DR: An ultrafast short-circuit protection scheme for TO-247 packaged silicon carbide (SiC) is presented in this article , where PCB coils are fabricated near a single interconnect trace between the power device and the dc busbar.
Abstract: Silicon carbide (SiC) mosfet s offer significant advantages in terms of improved efficiency and reduced size of power electronic converters. However, they possess lesser short-circuit withstand time than silicon devices. An ultrafast short-circuit protection scheme for TO-247 packaged SiC mosfet s is presented in this article. The protection scheme utilizes printed circuit board (PCB) coils to sense the rate of change of current through SiC mosfet s in a half-bridge circuit. The PCB coils are fabricated near a single interconnect trace between the power device and the dc busbar. To ensure minimal intrusion inside the power-loop, the methodology of selecting the minimum trace length for a desired mutual inductance between the coil and the interconnect trace is presented through finite-element analysis. Experimental results for an SiC mosfet subjected to a hard switched fault and a fault under load are presented, and the protection circuit response time under 25 ns is reported. Lastly, the peak current-mode control of a buck converter is implemented using the designed PCB coil-based sensor as current feedback sensor. Therefore, the PCB coil is demonstrated to be an effective alternative for Hall effect and magnetic core-based sensors in current control applications with dc/dc converters.
TL;DR: In this article , the quantum effect has been induced on junctionless double gate metal-oxide-semiconductor field effect transistors (JL-DGMOSFET) with gate oxide stack to study its effect on different device parameters like surface potential, threshold voltage, Id, Vg, gm, channel length etc.
TL;DR: In this article , the electrolumiscence of a gate pulsed MOSFET was measured at room and cryogenic temperatures with a spectrometer and two different amplitudes of the gate pulse.
Abstract: To reach the theoretical performance limit of 4HSiCMOSFETs the SiC/SiO2interfacedefects along the inversion channel need to be fully identified in order to be avoided. We employa measurement technique that allows to observe energetically resolved trap states at the SiC/SiO2 interface by measuring the electrolumiscence of a gate pulsed MOSFET. The spectra are recorded at room and cryogenic temperatures with a spectrometer and two different amplitudes of the gate pulse. Comparison of the results to literature allows for identification of the L1 line of the D1 center with an energy of 2.9 eV and suggests donoracceptorpair recombination or Z1/2 to be responsible for the emission around 2.5 eV. Ionization energies of PbC and related vacancy centers determined via ab initio calculations show similar results as the experimental data and provide a possible classification of the trap level around 1.8 eV.
TL;DR: In this paper , the authors evaluated nanometer gate length germanium transistors, including the electrical and thermal components, and compared them with silicon (Si) transistors and concluded that optimizing the channel region to fit the band gap energy is the most crucial aspect for designing transistors.
Abstract: This study evaluated nanometer gate length germanium (Ge) transistors, including the electrical and thermal components, and compared them with silicon (Si) transistors. Nanometer-scale Ge and Si junction-less field-effect transistors (JLFETs) were treated for both NFET and PFET devices under a transient response. Consequently, the electrical and thermal self-consistent simulations revealed that hole carrier transport is more challenging at the channel region for PFET, inhibiting process shrinking. Moreover, the results show that self-heating can reach a dangerous stature, particularly when the channel region is thick. This is because the operation of the nanometer-scale Ge and Si JLFETs depends on the quantum effect, which increases the band-gap energy. The suitable channel design for Ge and Si transistors is almost similar; a heavier doping concentration is favorable for Si transistors. The study concludes that optimizing the channel region to fit the band-gap energy is the most crucial aspect for designing transistors.
TL;DR: In this paper , the authors reported an NO2 p-type doped and Al2O3 bilayer passivated diamond metal-oxide-semiconductor field effect transistor (MOSFET) fabricated on a misoriented heteroepitaxial diamond substrate.
Abstract: In this letter, we report an NO2 p-type doped and Al2O3 bilayer passivated diamond metal–oxide–semiconductor field-effect transistor (MOSFET) fabricated on a misoriented heteroepitaxial diamond substrate. The MOSFET demonstrated a high breakdown voltage of 3659 V, the highest reported among diamond MOSFETs. MOSFETs with a gate length of $2.5~\mu \text{m}$ exhibited a maximum drain current density of 372 mA/mm and maximum available power density (Baliga’s figure-of-merit) of 173 MW/cm2. In addition, the maximum mobility was estimated to be ${187}\,\text {cm}^{{2}}/\text {V}\cdot \text{s}$ , and the subthreshold swing was 189 mV/dec. This study explores the prospects of misoriented heteroepitaxial diamonds in power electronic device applications.
04 Mar 2023
TL;DR: In this article , a review of the principal failure mechanisms during short circuit (SC) and unclamped inductive switching (UIS) events on SiC power MOSFETs is presented.
Abstract: Silicon Carbide (SiC) power MOSFETs are emerging as powerful switches to be used where compactness and light weight of the circuit are mandatory, as in aerospace converters, because the switching speed of SiC devices is faster than their silicon (Si) counterpart and therefore smaller inductors can be used. On the other hand, the operation out of the safe operating area of power semiconductor devices becomes critical especially where device, circuit and system reliability are important. In the aerospace sector, SiC devices still lag Si IGBTs and the gap needs to be filled. In this paper, a review of the principal failure mechanisms during short circuit (SC) and unclamped inductive switching (UIS) events on SiC power MOSFETs is presented.
TL;DR: Han et al. as mentioned in this paper proposed an automatic prediction method of the threshold voltage of the metaloxide-semiconductor field effect transistors (MOSFET) using machine learning.
Abstract: Machine Learning In article number 2200302, Cheol E. Han, Jae Woo Lee, and co-workers propose an automatic-prediction method of the metal–oxide–semiconductor field-effect transistors MOSFET Vth (threshold voltage) using machine learning (ML). The ML model eliminates the ambiguity in Vth extraction and provides objective Vth prediction for most FET schemes used in the semiconductor industry and research field.
TL;DR: In this article , a TCAD simulation study is implemented to study the effect of the variation of doping concentration and recess gate to achieve enhancement mode operation in β-Ga2O3 MOSFET with a channel thickness of 240 nm.
TL;DR: In this article , a chip-level series-connected low voltage (LV) SiC module based on planar packaging is proposed to compromise cost and parasitic inductance, and the performance of the proposed module is comparable with that of HV module with a single chip.
Abstract: In medium voltage (MV) and high voltage (HV) applications, HV SiC mosfet with a single chip competes with series-connected low voltage (LV) SiC mosfet . The cost of the former is high due to immature process, and the parasitic inductance of the latter is large due to series-connected devices. In this article, a novel chip-level series-connected SiC mosfet module based on planar packaging is proposed to compromise cost and parasitic inductance. Several LV chips are connected in series through metal layers, and then packaged as a whole. Compared with HV module with a single chip, the proposed module has significant advantages in cost. Considering the effects of the buffer layer and direct bonded copper on the parasitic inductance, junction temperature, thermal stress, and electric field, electro-thermo-mechanical simulation is conducted to optimize the structure. Compared with existing series-connected structures, the parasitic inductance of the proposed module is reduced by at least 50.15%. Finally, 6.5 kV chip-level series-connected module with six 1.2 kV SiC mosfet is fabricated and tested. The results show the performance of the proposed module is comparable with that of HV module with a single chip, which means that the application of the proposed module in MV and HV conditions is promising.
07 Feb 2023
TL;DR: In this article , an optimal set of structural parameters for a lateral gallium oxide MOSFET with a discrete field plate is designed using the suggested method, and the breakdown voltage is increased by 19.7%.
Abstract: The main barrier preventing the simulation design and optimization of wide bandgap semiconductor power devices is poor numerical convergence. Currently, the uncalibrated two-dimensional electric field distribution is the main foundation for the breakdown voltage optimization of gallium oxide power devices. This work achieves proper calibration of the current-voltage (I-V) characteristics as well as the breakdown voltage evaluation by enhancing the numerical method. An optimal set of structural parameters for a lateral gallium oxide MOSFET with a discrete field plate is designed using the suggested method. Thanks to the improved electric field profile, the breakdown voltage is increased by 19.7%, and on-state resistance did not degrade. This work resolves the wide-bandgap semiconductors' poor convergence problem and offers a workable strategy for the subsequent theoretical simulation and optimization of gallium oxide power devices.
TL;DR: In this paper , a dynamic current balancing method based on a new active gate driver (AGD) is proposed to improve the current sharing in high power applications, which can be easily used for multiple paralleled devices.
Abstract: In high-power applications, parallel connection of discrete silicon carbide (SiC) mosfet s is necessary to increase the current rating. However, the unbalanced dynamic current during switching transient may cause unequal power loss and thermal distribution, which is a great challenge in parallel applications. In this article, a dynamic current balancing method based on a new active gate driver (AGD) is proposed to improve the current sharing. The principle of the AGD is based on di/dt feedback control and voltage controlled current source to adjust gate drive current of SiC mosfet s. Therefore, the switching trajectory of the paralleled devices can be changed to achieve current balance. In addition, by using master-slave control strategy, the proposed AGD can be easily used for multiple paralleled devices. The double pulse tests are conducted to verify the effectiveness of the proposed AGD. For two paralleled devices, the turn- on and turn- off switching energy imbalances are reduced from 13.4% and 56.0% (12.1% and 52.9%) to 8.8% and 15.3% (8.0% and 8.8%) by the current source (current sink) circuit. For six paralleled devices, the degrees of turn- on and turn- off switching energy imbalances can be reduced from 21.8% and 16.1% to 11.8% and 7.8% by the proposed AGD.
TL;DR: In this paper , a gate driver circuit using auxiliary low-power SiC-MOSFET is proposed to suppress the crosstalk spike without additional negative gate-source voltage or control signal.
TL;DR: In this article , the authors proposed an on-chip active turn-off driver for silicon carbide (SiC) MOSFETs to realize the fast turnoff speed and low EMI noises.
Abstract: Silicon carbide (SiC) MOSFET has significant advantages in high-voltage (HV) and high-frequency (HF) applications due to its electrical characteristics. In order to make use of its merits, the active driver is necessary for SiC MOSFET. During the turn-off operation of SiC MOSFET, it is critical to prevent the channel current from disappearing prematurely, which has not been addressed in existing active drivers. This brief proposes an on-chip active turn-off driver to realize the fast turn-off speed and low EMI noises. The mechanism is that the turn-off driving current needs to be adjusted rapidly according to the operating state of SiC MOSFET, which can also ensure that EMI noises and overshoots are under control. Then, the proposed turn-off driver is fabricated in a $0.18~\mu \text{m}$ BCD process and occupies a 0.99mm2 active area. Finally, using the proposed active turn-off driver, the turn-off operation of SiC MOSFET has experimented with the 15A and 90A load current, respectively. SiC MOSFET realizes a high turn-off performance, about 200ns turn-off time with low EMI noises, demonstrating that the proposed on-chip active turn-off driving technique is suitable for SiC MOSFET under different loads.
TL;DR: In this paper , a recessed source trench silicon carbide (SiC) MOSFET with integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulations.
Abstract: In this article, a recessed source trench silicon carbide (SiC) MOSFET with integrated MOS-channel diode (MCD) is proposed and investigated by TCAD simulations. The MCD features a short channel, and the channel length could be adjusted by varying the recessed depth. Owing to the drain-induced barrier lowering effect, a low potential barrier for electrons to flow through the JFET region to the N+ source region is formed, which successfully eliminates the bipolar degradation of the parasitic body p-i-n diode. Besides, the recessed source trench introduces an additional depletion region and homogenizes the distribution of the OFF-state electric field. As a result, a low gate-to-drain capacitance and a high breakdown voltage (BV) are obtained. Simulation results indicate that compared with the SiC trench MOSFET with integrated self-assembled three-level protection Schottky barrier diode, a 78.7% reduction in gate-to-drain capacitance and a 24.4% improvement in BV could be achieved in the proposed SiC MOSFET.
TL;DR: In this article , the authors propose a solution to solve the problem of the problem: this article ] of "uniformity" and "uncertainty" of the solution.
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TL;DR: In this paper , the performance of n-type junctionless (JL) double-gate (DG) MOSFET-based biosensors with and without gate stack (GS) has been studied.
Abstract: In this article, the performance of n-type junctionless (JL) double-gate (DG) MOSFET-based biosensors with and without gate stack (GS) has been studied. Here, the dielectric modulation (DM) method is applied to detect biomolecules in the cavity. The sensitivity of n-type JL-DM-DG-MOSFET and n-type JL-DM-GSDG-MOSFET-based biosensors have also been evaluated. The sensitivity (ΔVth) improved in JL-DM-GSDG MOSFET/JL-DM-DG-MOSFET-based biosensors for neutral/charged biomolecules is 116.66%/66.66% and 1165.78%/978.94%, respectively, compared with the previously reported results. The electrical detection of biomolecules is validated using the ATLAS device simulator. The noise and analog/RF parameters are compared between both biosensors. A lower threshold voltage is observed in the GSDG-MOSFET-based biosensor. The Ion/Ioff ratio is higher for DG-MOSFET-based biosensors. The proposed GSDG-MOSFET-based biosensor demonstrates higher sensitivity than the DG-MOSFET-based biosensor. The GSDG-MOSFET-based biosensor is suitable for low-power, high-speed, and high sensitivity applications.
TL;DR: In this paper , a novel 4H-SiC trench MOSFET with Inverted-T groove (IT-UMOS) is proposed and investigated by numerical TCAD simulations.
Abstract: A novel 4H–SiC trench MOSFET with Inverted-T groove (IT-UMOS) is proposed and investigated by numerical TCAD simulations in this paper. The IT-UMOS features an Inverted-T groove beneath the gate trench. As a result, compared with the conventional trench MOSFET (C-UMOS) and step-UMOS, the IT-UMOS boasts a much lower gate-drain charge owing to the introduction of Inverted-T groove, thus a lowest switching loss is attained. In addition, the maximum oxide electric field during the blocking state in IT-UMOS is significantly reduced, which means the breakdown capability is not compromised. The dynamic figure of merit (FOM) Ron,sp × Qgd of IT-UMOS is the lowest among these three structures.