Showing papers on "Multiplexer published in 1998"

Method and apparatus for fair and efficient scheduling of variable-size data packets in an input-buffered multipoint switch

Abstract: An input-buffered multipoint switch having input channels and output channels includes multi-level request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multi-level request buffer associated with each input channel and each request buffer has multiple request registers for storing data cell transfer requests of different priorities. The multi-level request registers are linked in parallel to the scheduler to allow arbitration among requests of different input channels and different priority levels. The preferred arbitration process involves generating masks that reflect the output channels required by the same priority level requests. Utilizing masks to arbitrate between multiple requests in an input-buffered switch reduces arbitration cycle time and minimizes HOL blocking.

A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

Abstract: A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3/spl times/ the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10/sup -14/.

Optical devices and methods of fabrication thereof

Abstract: An optical device includes a waveguide bounded by a region containing a photonic band gap the properties of which determined the transfer characteristic of the waveguide. Such a device may serve as a component of, for example a wavelength division multiplexer, a monochromatic laser or a chemical sensor. It may serve as an optical bus for an electronic component such as a microprocessor. These devices are particularly suitable for incorporation in optical and optoelectronic integrated circuits as they permit the fabrication of waveguides having right-angle bends with a radius of the order of 2 νm.

Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A second local processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the second processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the second processor and the data transfer switch and configured to perform three dimensional graphic operations. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A multiplexer is coupled to the interface unit and provides access between a selected number of I/O device driver units and external I/O devices via output pins. A plurality of external I/O devices are coupled to the multimedia processor.

System for remote powering and communication with a network of addressable, multichannel sensing modules

Abstract: A multidrop network of multichannel, addressable sensing modules (ASM's), to be embedded within a composite structure, remotely powered, and interrogated by a personal computer through a non-contacting inductive link. Each ASM contains a microprocessor with non-volatile memory, multiplexer, programmable gain and filter instrumentation amplifier, and sigma delta analog to digital converter (all housed in two thin surface mount packages). An embedded mothernode includes circuitry for power and data reception (into the structure), and data transmission (back out of the structure). The external interrogation system communicates into the network of ASM's by modulating the AC waveform that delivers power to the embedded electronics. Once addressed, each ASM powers up its programmable (gain & filter) sensing channels (3 full differential or 5 pseudo differential) and data conversion elements. Sensed data are pulse code modulated, including error checking, which serially modulate an RF carrier for wireless transmission out of the composite to the interrogating computer. These advanced, micro-miniature sensing networks may be applied to a wide variety of military, medical, & civil structures.

Wavelength routing-based photonic packet buffers and their applications in photonic packet switching systems

Abstract: Photonic packet buffers are essential components in photonic packet switching systems. We present a wavelength routing-based photonic packet buffer based on a state-of-the-art arrayed-waveguide grating (AWG) multiplexer. We show how this new packet buffer can be effectively used in the implementation of photonic packet switching systems. We also propose and examine two different photonic packet switch architectures.

Integrated bi-directional axial gradient refractive index/diffraction grating wavelength division multiplexer

Abstract: A wavelength division multiplexer that integrates an axial gradient refractive index element with a diffraction grating to provide coupling from a plurality of input optical sources (each delivering a single wavelength) which are multiplexed to a single polychromatic beam for output to a single output optical receiver. The device comprises means for accepting optical input from at least one optical source, the means including a planar surface (20a); a coupler element (20) comprising an axial gradient refractive index collimating lens (26) having a planar entrance surface onto which the optical input is incident and a homogeneous index boot lens (24, 28) affixed to the axial gradient refractive index collimating lens and having a planar but tilted exit surface (20b); a diffraction grating (22) on the tilted surface of the homogeneous index boot lens which combines a plurality of spatially separated wavelengths from the optical light; and means to output at least one multiplexed, polychromatic output beam, the means including a planar surface (20a). The device may be operated in the forward or reverse direction as a multiplexer or demultiplexer.

Testing configurable LUT-based FPGA's

Abstract: We present a new technique for testing field programmable gate arrays (FPGA's) based on look-up tables (LUT's). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT's, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (l-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability), We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work.

Method and apparatus for channel equalization in wavelength division multiplexed systems

Abstract: A method and apparatus for channel performance equalization in wavelength division multiplexed (WDM) systems is disclosed Performance of the channels is estimated from optical power measurements of each signal transmitted by the channels The measurements are taken at the inputs of optical amplifiers in the transmission path of the system The channels are equalized by adjusting the optical power of the channel transmitters The method is applicable to point-to-point networks as well as more complex network configurations such as those having an add-drop multiplexer (ADM) for inserting and extracting channels from the transmission path The method can compensate for signals having different bit rates by applying an offset to the amount of optical power adjustment of the channel transmitters Furthermore, if different types of optical amplifiers are used in the transmission path, the method can accommodate different noise characteristics of the amplifiers by using their noise figures in determining the amount of optical power adjustment of the transmitters that is required to equalize channel performance

Apparatus and method of making a fused dense wavelength-division multiplexer

Abstract: The present invention relates to an apparatus and method of making a Dense Wavelength-Division Multiplexer (DWDM) using a Fused-Biconical Taper ("FBT") technique The DWDM according to the present invention comprises a multiple of Multi-window Wavelength-Division Multiplexers ("MWDMs") which cascade together in several stages, each stage has several MWDMs having an identical window spacing For a N-channel DWDM, there are 2 m-1 MWDMs cascaded in m-th stage, and the window spacing of the m-th stage MWDMs is 2 m-1 Δλ, where m is from 1 to (logN/log2), for example, the first stage(m=1) having 1 MWDM and the window spacing is Δλ, the second stage(m=2) having 2 MWDMs and the window spacing is 2Δλ, the third stage(m=3) having 4 MWDMs and the window spacing is 4Δλ, etc, and the (logN/log2)-th stage has (N/2) MWDMs with a window spacing (N/2)Δλ The number N could be 2, 4, 8, 16 or more

Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties

Abstract: The growth and the operation of all living beings are directed through the interpretation, in each of their cells, of a chemical program, the DNA string or genome. This process is the source of inspiration for the Embryonics (embryonic electronics) project, whose final objective is the conception of very large scale integrated circuits endowed with properties usually associated with the living world: self-repair (cicatrization) and self-replication. We begin by showing that any logic system can be represented by an ordered binary decision diagram (OBDD), and then embedded into a fine-grained field-programmable gate array (FPGA) whose basic cell is a multiplexer with programmable connections. The cellular array thus obtained is perfectly homogeneous: the function of each cell is defined by a configuration (or gene) and all the genes in the array, each associated with a pair of coordinates, make up the blueprint (or genome) of the artificial organism. In the second part of the project, we add to the basic cell a memory and an interpreter to, respectively, store and decode the complete genome. The interpreter extracts from the genome the gene of a particular cell as a function of its position in the array (its coordinates) and thus determines the exact configuration of the relative multiplexer. The considerable redundancy introduced by the presence of a genome in each cell has significant advantages: self-replication (the automatic production of one or more copies of the original organism) and self-repair (the automatic repair of one or more faulty cells) become relatively simple operations. The multiplexer-based FPGA cell and the interpreter are finally embedded into an electronic module; an array of such modules make it possible to demonstrate self-repair and self-replication.

Driver circuitry for programmable logic devices with hierarchical interconnection resources

Abstract: A programmable logic device has logic array blocks (“LABs”) and interconnection resources. For interconnecting signals to, from, and between the LABs, the global interconnection resources may include switch boxes, long lines, double lines, single lines, and half- and partially populated multiplexer regions. The LAB includes two levels of function blocks. In a preferred embodiment, there is one four-input second-level function block for every four-input first-level function blocks. At least one tri-state buffer is provided in each LAB. Each tri-state buffer may receive a data signal either from one or more function blocks in the associated LAB or from one or more interconnection conductors adjacent to the LAB. The tri-state buffer may buffer one of the received data signals and apply the resulting buffered signal to one or more of the interconnection conductors adjacent to the LAB.

Device and method for demultiplexing transport stream

Abstract: Device and method for demultiplexing a transport stream (TS), is disclosed, which is suitable for fast processing and transmission of transport stream packets of TV signal by a fixed length transport packet unit, the device including a synchronization and fetch controller for checking a synchronization byte of a received transport stream, a first subdecoder for comparing a packet identification number of the transport stream to an individual bit stream of the packet under the control of the synchronization and fetch controller, for filtering designated packets only, a second subdecoder for extracting a program clock reference information of the transport stream under the control of the first subdecoder, a descrambler for recovering a scramble signal from payload information in the transport stream under the control of the first subdecoder or the second subdecoder, a multiplexer for multiplexing the transport stream or descrambled signal under the control of the first subdecoder and the second subdecoder, and a third subdecoder for extracting a presentation time information of the transport stream or a stream from the multiplexer and providing a control signal to the multiplexer and the descrambler, whereby decoding the transport stream in real time on arrival thereof.

Dynamic optical add-drop multiplexers and wavelength-routing networks with improved survivability and minimized spectral filtering

Abstract: A method and apparatus for constructing an optical wavelength-routing network in which each network node is a dynamic add-drop multiplexer (OADM) with minimized spectral filtering effect on pass-through channels and survivability upon power failure. By using cascaded tunable reflection filters as the building blocks, strictly add-drop non-blocking OADMs for single input/output fibers, double input/output fibers, and 3 input/output fibers can be constructed for application to unidirectional and bidirectional ring networks and mesh networks of arbitrary degree. Methods and apparatus for minimizing various types of out-of-band and in-band crosstalk occurring within the dynamic OADMs are also described.

Article comprising a wavelength selective add-drop multiplexer

Abstract: A wavelength-selective add-drop multiplexer is disclosed for adding and/or dropping spectral components from a wavelength-division-multiplexed optical signal. (1x1) or (2x2) optical switches are used, either alone or in conjunction with other optical elements, to separate spectral components identified for drop from other spectral components.

A 200 mW 3.3 V CMOS color camera IC producing 352/spl times/288 24 b video at 30 frames/s

Abstract: A digital color camera has been monolithically realized in a standard 0.8-/spl mu/m CMOS technology. The chip integrates a 353/spl times/292 photogate sensor array with a unity-gain column circuit, a hierarchical column multiplexer, a switched-capacitor programmable-gain amplifier, and an 8-b flash analog/digital converter together with digital circuits performing color interpolation, color correction, computation of image statistics, and control functions. The 105-mm/sup 2/ chip produces 24-b RGB video at 30 frames/s. The sensor array achieves a conversion gain of 40 /spl mu/V/electron and a monochrome sensitivity of 7 V/lux/spl middot/s. For a 33-ms exposure time, the camera chip achieves a dynamic range of 65 dB and peak-to-peak fixed pattern noise that is 0.3% of saturation. Digital switching noise coupling into the analog circuits is shown to be data independent and therefore has no effect on image quality. Total power dissipation is less than 200 mW from a 3.3 V supply.

Arrayed waveguide gratings for wavelength routing

Abstract: Wavelength routing can be performed in the optical domain for both long-haul and passive optical networks. Arrayed waveguide gratings (AWGs) can perform wavelength routing for a large number of optical channels and provide a high level of functionality on an integrated chip. The AWG guides light on a planar lightwave circuit into an array of waveguides that provide dispersion to separate the different wavelengths of light. Routing functions can be performed on individual wavelengths. With this technology, optical cross-connects, optical add/drop multiplexers, and passive optical routers have been demonstrated. Performance issues-such as insertion loss, polarization dependence, passband shape, passband position, crosstalk, and temperature dependence-are being addressed so that AWGs will be practical for deployment into systems.

Output port switching device in N-WDM system

Abstract: In an output port switching device in an N-WDM system, plural ports are switched by a change-over switch 18 , and a backup light source path 19 linked to the change-over switch 18 has a wavelength-variable light source 23 . A first multiplexer 14 wavelength-multiplexes plural optical signals output from the plural ports, and a trouble-occurring port monitoring mechanism portion 17 monitors occurrence of a trouble on the basis of an optical signal split from the output optical signal. The change-over switch 18 selects and switches an optical signal to which the trouble is detected, and the backup light source path 19 is controlled so that the wavelength thereof is substantially coincident with the wavelength of the optical signal to which the trouble is detected, and the optical signal thus controlled and the output optical signals of the first multiplexer are multiplexed by a second multiplexer 15.

Decoder for error correcting block codes

Abstract: A decoder for decoding block error correction codes is described. The decoder includes a first search circuit to find roots of an error location polynomial corresponding to an error location and a second search circuit to find roots of an error location polynomial corresponding to an error location. A multiplexer is fed by the first search circuit and the second search circuit to produce an error location from the error location polynomial.

Power system for an implantable heart pump

Abstract: A power system for an implantable heart pump is provided. The system includes two batteries, a microprocessor controller, two motor drivers, a multiplexer, two stators and a TET coil. During normal operation, only one battery and one motor driver are in use at a time to drive both stators.

Apparatus and method for encoding multiple video programs

Abstract: A video encoding apparatus includes a plurality of encoders for encoding each of a plurality of video programs received from external; a multiplexer for multiplexing outputs of the plurality of encoding means; a buffer for temporarily storing and transmitting signal multiplexed by the multiplexer; and a central controller for receiving monitoring information with respect to buffer fullness from the buffer and providing quantization parameters to be applied to respective pictures to be now encoded with the respective encoders. The sum of the bit rates of all the multiplexed video programs is constant, but each of the video programs allows for a variable bit rate (VBR) by synchronously controlling each of a video encoders by means of the central controller, thereby maintaining a relatively uniform picture quality within one picture.

Multiple channel multiplexer/demultiplexer devices

Abstract: Multiple channel optical multiplexing/demultiplexing devices that utilize only a single constant, non-variable wavelength selective optical filter have many advantages. The wavelength-selective optical filter (30) is a conventional fixed wavelength optical interference filter having an angle shift property wherein the wavelength-selectivity changes with changing angles of incidence upon the filter. Because such filters are transparent to a different center wavelength and depending on the angle of incidence of a light beam, multiplexing/demultiplexing is achieved by varying the angle of incidence of a light beam (40) upon a single, constant and non-variable optical interference filter. Two such exemplary systems utilize a multiple reflection chamber adapted to transmit a light beam at successively varied angles of incidence upon a single interference filter.

Data processing system, circuit arrangement and program product including multi-path scan interface and methods thereof

Abstract: A data processing system, circuit arrangement, program product, and method thereof utilize a multi-path scan interface that is capable of providing multiple scan paths into a plurality of scan ring segments in an integrated circuit device. The multi-path scan interface utilizes one or more multiplexers coupled between scan in and scan out ports and at least one scan ring segment to provide alternate scan paths depending upon select signals supplied to each multiplexer. With such a configuration, a standardized scan interface may developed for interfacing with a wide variety of scan ring segments, and optionally, for multiple purposes. As a result, the amount of custom circuitry necessary to provide access to scan ring segments is significantly reduced.

Method and apparatus for generating error detection data for encapsulated frames

Abstract: An error detection generator calculates error detection data for insertion into encapsulated frames. The error detection generator is configured to calculate multiple error detection values and insert them into corresponding fields of the encapsulated frames. The error detection generator includes a controller, three cyclic redundancy check (CRC) engines and at least one multiplexer. Each CRC engine is selectively enabled by the controller to calculate a frame check sequence (FCS) value on a different portion of the frame. Downstream CRC engines also receive the outputs from the upstream CRC engines so that these earlier FCS values may be used during subsequent calculations. The outputs of the CRC engines are also inserted into the appropriate fields of the encapsulated frames by the multiplexer.

Programmable interconnect matrix architecture for complex programmable logic device

Abstract: Routing an input signal to an output of a programmable interconnect matrix is accomplished via multi-level routing architecture. The routing may include selecting the input signal from a number of input signals at a first level of the routing architecture to provide an intermediate signal. The intermediate signal may then be selected at a second level of the routing architecture to provide the output signal. Selecting the input signal and/or the intermediate signal may be accomplished by programming one or more mutliplexers. In a further embodiment, the method includes dividing a plurality of input signals into segments, each segment including a number of the plurality input signals. From the segments, at least one of the input signals may be selected to produce the intermediate signal. Further still, a method of interconnecting signals by coupling an input of a connection circuit of a programmable logic device to an output thereof through a multi-level routing architecture within the connection circuit is provided. The coupling may be accomplished by first coupling the input to a first intermediate signal path at a first level of the multi-level routing architecture and then coupling the intermediate signal path to the output at a second level of the multi-level routing architecture. In each case, the coupling may be accomplished by appropriate selection using one or more multiplexers at the various levels of the multi-level routing architecture.

Optical fiber wavelength multiplexer and demultiplexer

Abstract: The present invention relates to an optical fiber wavelength multiplexing or demultiplexing device comprising: An optical fiber wavelength multiplexing device comprising: an array of input single-mode fibers (101 to 105) designed for carrying light beams at different wavelengths (λ1, λ2, λ2, . . . ,λn), an output single-mode fiber (161) designed for carrying the whole set of such light beams, a dispersing system (107) receiving light beams from the input fibers (101 to 105) in an end plane and generating superimposed light beams designed for the output fiber (161) in an output plane, an array of converging microlenses (171 to 175) being located in the input plane, whereas a microlens corresponds to each input fiber, wherein the microlens array has the same pitch as the input fiber anlay and produces diverging beams whose respective central axes are parallel and which are directed to a collimating lens (108) which produces parallel collimated beams whose respective central axes are converging on the dispersing system. The demultiplexer comprises the same elements, whereas the roles of the input/output fibers and planes are reversed.

Phased array system architecture

Abstract: Architecture for driving an ultrasound phased array. The architecture includes a series of amplifiers (38) which produce discrete driving signals. The amplifiers number less than the number of transducer elements (32) in the array (31) and an integrated circuit multiplexer chip (34) is coupled to each transducer and to all the amplifiers. A controller (40) provides first control signals to the amplifiers (38) causing the amplifiers to produce their discrete driving signals. The controller (40) further provides second control signals to each multiplexer chip (34) and these signals cause the multiplexer chips to pass a specified one of the driving signals to a selected one of the transducer elements (32). The result is that a focused ultrasonic beam is formed on a selected target volume.

Fiber optic dense wavelength division multiplexer with a phase differential method of wavelength separation utilizing a polarization beam splitter and a nonlinear interferometer

Abstract: A dense wavelength division multiplexer for separating an optical signal into optical channels is provided. The dense wavelength division multiplexer of the present invention includes a manner for inputting an optical signal where the optical signal comprises a plurality of optical channels; a manner for separating one or more of the plurality of optical channels by introducing a phase difference between at least two of the plurality of optical channels, where the manner of separation includes a polarization beam splitter; and a manner for outputting the separated plurality of optical channels along a plurality of optical paths. The dense wavelength division multiplexer of the present invention provides an ease in alignment and a higher tolerance to drifts due to the increase in the width of the pass band. Its separators may also be placed in a multi-stage parallel cascade configuration to provide for a lower insertion loss. It may also be easily modified to perform the add/drop function as it separates channels. The material required to manufacture and implement the dense wavelength division multiplexer is readily available and do not require special or expensive materials or processes. It is thus cost effective.

High-speed test system for a memory device

Abstract: A memory device requires a minimum of two input/output lines from an external testing device to be coupled thereto A first DQ line from the memory device provides a direct data path from the array so that the external tester can read data from the array at the maximum speed of the memory device Test mode circuitry for multiplexing and comparing multiple DQ lines during address compression mode is coupled to two or more DQ lines, including the first DQ line The compression mode testing circuitry can include on-chip comparators that compare the data simultaneously written to, and read from, the memory device The comparison circuitry outputs a data test flag indicating whether or not the data read from the memory device matches The test flag is output through a multiplexer to a second DQ line As a result, the speed of the device can be tested from the first DQ line, while the results of on-chip comparison can be sampled at the second DQ line The compare circuitry compares not only bits of a given data word, but also at least one bit from another data word Therefore, rather than employing two compare circuits that compare first and second data words, and a third compare circuit that compares the results of the first two compare circuits, the present invention avoids the need for the third compare circuit by comparing the first data word in a first compare circuit with at least one bit from the second data word

Method and apparatus for a data transmission rate of multiples of 100 MBPS in a terminal for a wireless metropolitan area network

Abstract: A method and apparatus for a data transmission rate of multiples of 100 mega-bits per second (Mbps) in a terminal for a wireless metropolitan area network. A terminal includes a first media access control unit (MAC) unit for receiving Fast Ethernet data packets at a rate of 100 Mbps for communication over a wireless link, n−1 additional MAC units for receiving Fast Ethernet data packets at a rate of 100 Mbps for communication over the wireless link, a multiplexer having n inputs, wherein each input is coupled to receive the data packets from a corresponding one of the MAC units and wherein the output of the multiplexer provides time-division multiplexed data, a packet formatting apparatus coupled to the output of the multiplexer for formatting the time division multplexed data according to radio frames, and a wireless transceiver coupled to the packet formatting apparatus for communicating the radio frames over a wireless link wherein the wireless link has a maximum bandwidth capacity of at least n times 100 Mbps. Each MAC unit can include a rate control unit and a rate buffer for temporarily storing data packets received by the corresponding MAC unit prior to providing them to a corresponding one of the inputs of the multiplexer. Each MAC unit can include a corresponding layer-two or layer-three switch having a 100 Mbps port. The maximum transmission rate is limited only by the bandwidth of the wireless link.