A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

TLDR: A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process to achieve the high data rate without speed critical logic on chip, using multiple phases tapped from a PLL using the phase spacing to determine the bit time.

Abstract: A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-/spl mu/m HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3/spl times/ the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10/sup -14/.