Showing papers on "Pass transistor logic published in 1980"

Test system for LSI circuits resident on LSI chips

Abstract: A test system performs dynamic testing of complex logic modules at full system clock rates and is resident on each LSI chip under test. The system logic is designed to be included on each LSI chip to reduce the time and computation required to detect and isolate faults in systems built from one or more chips. The on chip system includes switchable transmission gates to alter logic paths, a control shift register in the test function, an input shift register, an associated test generator and accumulator, an output shift register and an associated generator and accumulator. This logic provides test operands for the logic function under test and analyzes the resultant operands. Test operands are produced using a shift register connected to all inputs of the logic function under test. Checksum logic together with a shift register produce a running checksum of all output states of the module under test at the operative clock rate of the LSI.

Design of 2.5-micrometer Josephson current injection logic (CIL)

Abstract: This paper describes Josephson Current Injection Logic (CIL) circuits. The design of the basic logic circuits, the two-and four-input OR and AND gates, and a timed inverter circuit, is presented in full detail and the logic delay and its sensitivity to design and fabrication parameters are investigated using detailed models of devices based on a 2.5-µm technology. The nominal logic delay of the circuits is estimated at 36 ps per gate for an average fan-in of 4.5 and fan-out of 3. The corresponding average power dissipation is 3.4 microwatts per gate. Finally, experimental delay measurements are presented for two-input and four-input OR and AND gates. The delay experiments are in excellent agreement with computer simulations.

Analysis of GaAs FET's for integrated logic

Abstract: This paper presents an analysis of the speed and power dissipation of various GaAs FET inverter circuits as prototypes of integrated logic circuit design. The analysis provides analytical expressions to assess the switching performance of enhancement-mode and depletion-mode MESFET's and JFET's with respect to switching-speed and power-dissipation capabilities in optimized configurations. Various load elements are described and analyzed for circuit applications. The various logic gates, now under development, are compared in their switching performance and a review of the state of the art is given. Prospects of large-scale integration (LSI) of gigabit logic for GaAs FET's are assessed.

Josephson-logic devices and circuits

Abstract: A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.

Quasi-normally-off MESFET logic for high-performance GaAs IC's

Abstract: The stringent pinchoff voltage control required by the normally-off GaAs FET logic approach appears to be a very serious limitation to its LSI capability. This paper presents the operation and performance of a more tolerant logic IC approach intented to succeed in manufacturing high-performance digital GaAs IC's with LSI complexities. The so-called "quasi-normally-off" MESFET's are utilized, i.e., transistors operating as enhancement-mode devices but having a pinch-off voltage indifferently positive or negative (-0.3 to +0.2 V typically). As well as the genuine normally-off logic, quasi-normally-off digital IC's require a single power supply with a small voltage value (about +3 V). Six alternative circuit configurations, which exhibit different complexity-performance tradeoffs, have been studied by computer simulation. Furthermore, file performance capability of this logic was experimentally tested on 11-stage ring-oscillator circuits fabricated with 1 × 35 µm gate MESFET's. Minimum propagation delays in the range 95-135 ps (depending on the logic gate configuration) and speed-power products of 200-250 fJ (at V_{DD} = 2.5 V) were achieved. From these results, propagation times in the range 100-200 ps and figures of merit of 50-200 fJ can be expected for logic gates with 10-20-µm FET geometry and LSI-circuit fan-in/loading conditions.

Programmable sequential logic circuit devices

Abstract: The programmable sequential logic circuit device is constructed to sequentially form an output signal to an external circuit and the circuit state for the next operation in accordance with input signals applied from outside and the internal state of the circuit. The device includes a first logic array for producing product terms of the input signals, a second logic array for producing sum terms of the first logic array, a two-dimensionally arrayed flip-flop array and means for setting the state of the flip-flop array. The flip-flop array is arranged in a plurality of rows of stages each including a plurality of serially connected flip-flop circuits. The inputs of respective rows are connected to the outputs of the second logic array, the outputs of the setting means are applied to the inputs of respective stages and the outputs thereof are parallelly fed back to the first logic array.

Asynchronous circuit responsive to changes in logic level

Abstract: An integrated circuit operable with low power consumption and high reliability is disclosed. The circuit comprises a logic circuit receiving an input logic signal at its input, detection means for detecting a change in the logic input signal, means responsive to an output of detection means for producing a control signal, and control means responsive to the control signal for setting the logic circuit at a predetermined condition irrespective of the input logic signal.

Current Injection Logic Gate with Four Josephson Junctions

Abstract: A novel current switching Josephson logic gate in which four junctions are connected in a loop is described. This four-junction logic gate can reduce an inductance included in the loop as small as possible, so that the higher switching speed and the smaller device size is expected. The switching threshold and the switching characteristics of the gate are investigated both theoretically and experimentally. Logic circuits based on the gates are also experimentally demonstrated.

High current static MOS driver circuit with low DC power dissipation

Abstract: A static push-pull driver circuit employs an enhancement mode input transistor and two parallel load transistors, with an input logic voltage on the gate of the input transistor and its complement on the gates of the load transistors. One load transistor is a depletion mode and the other a "low-threshold" device; the threshold voltage of the low-threshold transistor is much less than that of the enhancement mode input transistor.

Voltage regulator for a controlled field generator

Abstract: A voltage regulator which regulates field current through a controlled field generator used to charge a battery, including a battery voltage sensing circuit which generates logic control signals in response to the battery voltage being above or below a predetermined level, an over-current sensing circuit which generates logic control signals in response to the charging current of the generator being above or below a predetermined level of charging current, a logic gate for gating the logic control signals, and a control circuit responsive to the signals from the logic gate to continue or interrupt field current through the field winding.

Dynamic logic circuits operating in a differential mode for array processing

Abstract: The disclosure teaches various logic circuits operating with Dynamic Differential Logic (DDL). In a particular embodiment MOS transistors of n-channel type are used with circuits arranged to avoid any dc path from clock input to ground. The input capacitance of the active devices is used for temporary storage thereby reducing circuit complexities. Coupling between stages is provided by clock driven transistors connected so that the transistor at the higher voltage side cuts off early in the period of clock pulse decay, thereby isolating adjacent stages without unnecessary delay. The use of such circuits in array processors is described.

Design of multiplexer universal-logic-module networks using spectral techniques

Abstract: A technique is described for the optimal synthesis of n-variable combinational logic circuits with Multiplexer universal logic modules, which may readily be implemented without excessive computer storage requirements. The method requires knowledge of the Rademacher-Walsh spectrum, which is an alternative representation of the truthtable vector of the function being considered. It makes use of a property of chosen subsets of these spectra coefficients, which when operated upon can give good indications of the merits of particular decompositions. It is found that an optimal choice of control input variables, and hence aminimal number of multiplexer modules in the realisation, can be made by relatively few tests on the spectral coefficient values.

Logic circuit with improved switching

Abstract: A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

Power Design for Gigabit Josephson Logic Systems

Abstract: An ac power system design in described for powering, at near gigahertz frequencies, 16K Josephson latching logic circuits distributed uniformly over 16 chips. The power system distributes a sinusoidal current waveform from a single source to the many chip quadrants through a tree system of thin-film transformers that have branching secondaries and multiple turn primaries to maintain nearly constant current amplitudes throughout the system and small phase skews at the logic-circuit level. The sinusoidal waveform is clipped on-chip to provide the trapezoidal waveform required by the logic circuits. The ratio of the duration of the up-portion of the trapezoidal half-cycle to the half-cycle period (the logic cycle) is defined as the active duty cycle for the logic. The 16K circuit-power design is capable of providing an 80-percent duty cycle at a 1.7-ns logic cycle while keeping current levels in the system below 300 mA. An approximate expression is derived that predicts that for any power-system design of this type the product of the system size, the highest frequency of operation, and the chip-quadrant current level is a constant.

Adaptable nonlinear transmission line terminator

Abstract: A nonlinear transmission line terminator terminates a transmission line having an input from any one of a plurality of logic types. Emitter coupled logic (ECL), transistor logic (TTL), Schottky transistor logic (STTL), low power Schottky transistor transistor logic (LSTTL), complementary MOS (CMOS) and the like are accommodated by impressing the voltage representing a "0" of the logic circuitry being accommodated on one reference terminal and the corresponding "1" voltage on another reference terminal. The terminator presents a very high impedance when the input signal from the transmission line is of an amplitude falling within the "0" and "1" voltage range. When the input signal falls outside the voltage range, the impedance of the terminator matches that of the transmission line to reduce line reflections by providing a path for current to flow from the transmission line to the appropriate one of the "1" or "0" reference terminals. The terminator further has constant current circuitry for maintaining the current flow at or below a predetermined level irrespective of the amplitude of the input voltage signal.

Fast level shift circuits

Abstract: A logic level converter for translating an input signal that swings between first and second voltage levels to an output signal that swings between third and fourth voltage levels. The input signal and its complement are first translated to the desired output levels in a pair of conventional CMOS inverters to produce complementary logic signals. The faster edge of each translated logic signal is used by logic means to control the output signal. Specifically, the leading edge of one logic signal and the trailing edge of the other logic signal are used to control the output signal. The resulting logic level shift circuit provides both fast rise and fall times, and substantially equal propagation delays for both high-to-low and low-to-high signal transitions.

High speed current mode logic for LSI

Abstract: A high speed/low power logic family is described which combines the best features of current mode logic (CML), emitter-coupled logic (ECL), and emitter function logic (EFL). This is combined with a low voltage-current source, using the principle of current imaging, to provide three levels of series gating with reduced supply voltages. With relatively slow transistors ( f_1 =500 MHz) circuit structures have been fabricated which provide several logic levels with a total delay of 2 ns and total power dissipation of 2 mW per circuit structure. The paper also describes the implementation of ROM's, RAM's, and PLA's using the principle of current steering. An analysis is given for circuit operation with variation in supply voltage and temperature. Three fabricated LSI chips are described with an average of 1000 equivalent gates per chip.

Multi-level logic gate implementation in GaAs ICs using schottky diode-FET logic

Abstract: An extension of the Schottky diode-FET logic circuit approach for ultra high-speed, low-power planar GaAs digital ICs to configurations allowing up to three levels of logic to be performed in one gate, will be reported.

High Density Integrated Computing Circuitry with Multiple Valued Logic

Abstract: It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic. In this correspondence, a useful quaternary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms. The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs. A significant savings in integrated devices and thus increased packing density could be obtained in each case.

Integrated memory circuit

Abstract: The integrated circuit is operable with low power consumption and high reliability. This circuit comprises a logic circuit (11) receiving an input logic signal (Ao-An) at its input, detection means (17) for detecting a change in the logic input signal, means responsive to an output of detection means for producing a control signal (CE), and control means responsive to the control signal for setting the logic circuit at a predetermined condition irrespective of the input logic signal.

Data bus fault detector

Abstract: An error detection circuit detects prolonged sequences of unchanged logic state in a data busing structure. The circuit generates a complementary two rail logic output from a pair of flip-flops. The circuit includes a comparator which compares the logic state of the data input from the bus with the output of one of the flip-flops, and which inputs alternate opposite logic states to that flip-flop as long as the data input exists for a time in the same logic state as the output of the one flip-flop during a cycle. The complementary two rail output changes every cycle to actively exercise the error detection circuit and prevent silent failures therein. The circuit is self-checking because internal failures yield non-complementary outputs.

Capacitor-coupled logic using GaAs depletion-mode f.e.t.s

Abstract: A new method of interconnecting depletion-mode GaAs f.e.t. logic stages, using capacitive coupling, eliminates the need for a negative power supply and is more tolerant of processing spreads, particularly of pinch-off voltage. The technique may be combined with conventional level shifting, operating at very low current. The use of capacitance may be extended to achieve clocked dynamic data storage with very low power dissipation.

A complete single-supply microprocessor-compatible 8-bit DAC

Abstract: A functionally complete, microprocessor-compatible digital-to-analog converter which operates on a single +5 V supply is described. This monolithic bipolar chip is fabricated using a linear compatible I/SUP 2/L process and contains both a precision reference and a voltage output buffer, along with the DAC and input logic. Laser wafer trimming of on-chip thin-film resistors is used to guarantee output response linearity as well as the absolute calibration of end points. The new circuit techniques which were developed to allow low-voltage single-supply operation with no sacrifice in performance are described and analyzed in detail.

High speed, non-saturating, bipolar transistor logic circuit

Abstract: A bipolar transistor logic circuit comprises an input terminal for receiving digital logic signals, an output terminal, an output driver including a current sink transistor and a current source transistor, and a control stage coupled between the input terminal and the output driver. When the control stage is nonconducting, the current source transistor is turned ON and the current sink transistor is turned OFF providing a first digital logic signal at the output terminal. When the control stage is conducting, the current source transistor is initially turned OFF and the current sink transistor is turned ON providing a second digital logic signal at the output terminal. If the output load does not provide the amount of current required by the current sink transistor, the current source transistor is turned ON by the control stage and provides the current sink transistor with collector current to prevent the sink transistor from saturating. In an embodiment providing a tri-state output capability, a second input terminal for receiving digital logic signals is coupled to the aforementioned control stage and to a second control stage. When both control stages are conducting, both the current source transistor and the current sink transistor are turned OFF. As a result, the output terminal is set to a high impedance state and neither provides current to nor withdraws from the output load.

Low pinch-off voltage f.e.t. logic (l.p.f.l.): I.s.i. oriented logic approach using quasinormally off GaAs m.e.s.f.e.t.s.

Abstract: A new l.s.i. oriented logic approach, low pinch-off voltage f.e.t. logic (l.p.f.l.), leading to highly versatile logic gates capable of combining high speed and low power consumption and requiring a standard fabrication process, is introduced and structures of complex logic gates realisable with this approach are described. Furthermore, a tentative comparison of the l.p.f.l. approach with other m.e.s.f.e.t. logic approaches to date is presented to show their respective design trade-offs which dictate the range of applications open to each of these approaches. The comparison is based on both computer simulations and experimental measurements on test circuits such as ring oscillators, flip-flops and binary frequency dividers.

Circuit arrangement using emitter coupled logic and integrated injection logic

Abstract: In a circuit using integrated injection logic and emitter coupled logic circuits, a unique arrangement is used to facilitate the interface between various circuit sections. An embodiment in an AM/FM digital tuner circuit is shown. Specifically, the integrated injection logic circuits are stacked with the current supply for the integrated injection logic stack being directly connected to the same power supply operating potential as the current supply for the emitter coupled logic circuits. Such arrangement reduces the magnitude of the potential difference between logic signal voltage levels between the respective logic circuits. Representative interface circuits between integrated injection logic circuits and emitter coupled logic circuits are disclosed. An interface circuit using emitter coupled logic is disclosed for fast level shift between upper and lower level circuits within the integrated injection logic stack.

Logic gate having a noise immunity circuit

Abstract: A field effect transistor (FET) logic gate wherein a plurality of FETs is coupled to an output enhancement mode FET through a noise immunity circuit, such noise immunity circuit including a Schottky diode. A biasing network ensures that any conducting one of the input transistors produces a forward voltage drop between its input and output less than the forward drop of the Schottky diode circuit ensuring that the voltage at the gate electrode of the output transistor is less than the threshold voltage of such output transistor in the presence of noise. In one embodiment the logic gate includes a coupling FET having a gate electrode coupled to the gate electrode of the output transistor through the noise immunity Schottky diode circuit, and a source electrode coupled to the plurality of input transistors. A first current source is coupled to the gate of the coupling transistor and provides a sufficient voltage to drive the output transistor into full conduction when the input transistors are in low conduction states. A second current source is coupled to the drain electrode of the coupling transistor and supplies a predetermined amount of current to a conducting one, or ones, of such input transistors. The current supplied by the second current source is determined in accordance with the fan-out requirements of the logic gate and is independent of a bias voltage provided by the first current source at the gate electrode of the output transistor to place the output transistor into full conduction.

MOSFET Convolved logic

Abstract: A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers, as contrasted to an algebraic accumulation of delays with conventional logic techniques. This results in an N-factor improvement in the power-delay product over conventional techniques, where N is the number of logic operations being performed.

High Density Integrated Computing Circuitry with Multiple Valued Logic

Abstract: It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic In this correspondence, a useful quatemary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs A significant savings in integrated devices and thus increased packing density could be obtained in each case

Design and implementation of three-valued logic systems with M.O.S. integrated circuits

Abstract: A method of design of three-valued logic circuits which reduces the need for complementary pairs of m.o.s. integrated circuits is presented. Circuits of basic ternary operators (inverters, NAND and NOR) are utilising single m.o.s. transistors. Based on these ternary operators it is possible to design simpler and cheaper three-valued logic systems. As examples, the construction of the Jk arithmetic circuit and the T-gate are described.