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Showing papers on "Physical design published in 1977"


Journal ArticleDOI
TL;DR: In this article, the authors developed circuit design criteria which lead to optimal performance in applying the six-port technique to the measurement of microwave parameters, and a circuit which approximately satisfies these new design goals is described.
Abstract: In a companion paper, circuit design criteria were developed which lead to optimal performance in applying the six-port technique to the measurement of microwave parameters. A circuit which approximately satisfies these new design goals is described. Together with its several variants, it promises to become, in many applications, the "preferred" six-port circuit.

159 citations



Proceedings ArticleDOI
K. A. Chen1, M. Feuer1, K. H. Khokhani1, N. Nan1, S. Schmidt1 
01 Jan 1977
TL;DR: An automatic system for routing the metal connections on integrated circuit chips that has been used successfully at IBM in the physical design of bipolar logic chips is described.
Abstract: This paper describes an automatic system for routing the metal connections on integrated circuit chips. The system contains three major sections: global wiring, vertical channel assignment, and horizontal bilateral channel allocation. Since its initial development in 1972, this system has been used successfully at IBM in the physical design of bipolar logic chips.

59 citations


01 Sep 1977
TL;DR: In this paper, a technique for determining the applicability of a particular process for the fabrication of large-scale integrated (LSI) circuits was described for determining whether a given process can achieve a desired result.
Abstract: A technique is described for determining the applicability of a particular process for the fabrication of large-scale integrated (LSI) circuits. Test arrays were developed to isolate various critical processing steps in a fabrication sequence and a statistical evaluation of these steps was carried out that related yield or success in achieving a desired result to the number of times the results were attempted. It was found that, in general, yield is a sensitive function of physical dimensions as is the packing density of a particular array. It is, therefore, possible to generate an optimum set of physical dimensions or design rules that maximize the expected number of working circuits on a wafer.

35 citations


Patent
15 Dec 1977
TL;DR: In this article, a pulsed laser is applied to individual circuits in wafer form using a step and repeat operation each circuit is measured, the transistor to be trimmed determined and a first trim performed The circuit is remeasured and if still out of specification, retrimmed The process is repeated until a desired degree of balance is achieved.
Abstract: In a monolithic integrated circuit having a combination of bipolar and junction field effect transistors, a pulsed laser is employed to trim the transistors to achieve balanced circuit performance The laser is applied to individual circuits in wafer form using a step and repeat operation Each circuit is measured, the transistor to be trimmed determined and a first trim performed The circuit is remeasured and, if still out of specification, retrimmed The process is repeated until a desired degree of balance is achieved

27 citations



Journal ArticleDOI
TL;DR: A generalized tuning technique is described which makes the design of a tuning algorithm, and automated tuning, amenable to a universal computer mechanization, and improves the yield and speed of operation of the tuning process.
Abstract: A high-performance RC active filter realized as a thick or thin-film hybrid integrated circuit presents special fabrication problems. A filter of this type is so sensitive to its parameters that in a large proportion of cases, a circuit so constructed will not meet its performance specifications even if the tightest practicable tolerances are held on the circuit components. As a consequence, the filter network must be tuned after fabrication. It is not feasible to adjust circuit capacitors, hence all tuning must be accomplished by resistor adjustment, and these adjustments can only increase resistance. In this paper, a generalized tuning technique is described which makes the design of a tuning algorithm, and automated tuning, amenable to a universal computer mechanization. In addition to eliminating the analysis and software preparation required to set up a process-control system, the generalized algorithm improves the yield and speed of operation of the tuning process. The central idea of this tuning scheme is to estimate transfer function coefficient errors based on capacitor measurements and then to choose resistance values for the circuit in such a way as to minimize these errors. The operation of the algorithm is sequential, with succeeding resistance values chosen to minimize the cumulative error due to preceeding process steps.

21 citations


Proceedings ArticleDOI
13 Jun 1977
TL;DR: The design principles of an automatic system that has the ability to choose the physical design for a data base and to adapt this design to changing requirements are presented.
Abstract: Physical data base design, the selection of organizational structures and access mechanisms for a data base, is one of the most important responsibilities of a Data Base Administrator (DBA). A DBA often has difficulty in performing this task; he lacks the information needed to choose a design that is well matched to the data base's mode of use.This paper presents the design principles of an automatic system that has the ability to choose the physical design for a data base and to adapt this design to changing requirements. The components of such a system include: an information gathering module that collects global statistics on the overall usage pattern of the data base; a predictor that projects observed usage statistics into the future; a design evaluator that computes a figure of merit for any proposed design; and a heuristic proposer that synthesizes a small set of candidate designs for detailed consideration. These principles have been applied to the design of a system that selects secondary indices for an inverted file system.

13 citations


Patent
John H. Lee1, Peter A. Lind1
25 Jul 1977
TL;DR: In this article, a solid-state programmable control circuit provides multiple time selected application of A.C. power to one or more utilization circuits or devices using a crystal controlled time base generator.
Abstract: A solid-state programmable control circuit provides multiple time selected application of A.C. power to one or more utilization circuits or devices. The control circuit uses a crystal controlled time base generator which is synchronized to commercial A.C. power. Stand-by battery power is provided to maintain timing when A.C. power is lost. A time display plug-in module is used with the circuit for setting the time for the control circuit. Programming can be done at a point remote from the control circuit.

12 citations


01 Jan 1977
TL;DR: A new automatic IC mask layout code, SICLOPS is being developed which avoids most of the problems inherent in the present generation of layout codes such as lack of flexibilityy inefficient use of area, and restricted design complexity.
Abstract: A new automatic layout code (Sandia Integrated Circuit Layout Program System-SICLOPS) is being developed which avoids earlier problems, provides flexibility for designing ICs using different technologies, and provides the basis necessary to design highly complex chips bordering on VLSI complexity. The SICLOPS layout approach relies on a structured hierarchical layout using modules consisting of assemblies of standard cells or bonding pads and macrocells. One of the keys to efficiency is the use of the same routing algorithms at each stage of the layout to optimize the layout for the individual modules prior to incorporating the modules in the overall chip layout. The SICLOPS program is expected to generate a CMOS IC layout using a silicon gate technology which is approximately a factor of five higher in device density than a metal gate technology. (RWR)

11 citations


Patent
01 Nov 1977
TL;DR: In this paper, an apparatus for simulating error conditions associated with an integrated circuit, the integrated circuit being an in-line component of an electronic circuit, is presented, in which two decoders decode the voltage level specification and integrated circuit pin specification portions of the stored control information, respectively.
Abstract: An apparatus for simulating error conditions associated with an integrated circuit, the integrated circuit being an in-line component of an electronic circuit. The apparatus, in response to the receipt of specified commands, accepts and stores data and control information, the control information including an integrated circuit pin specification portion and a voltage level specification portion, the data information specifying integrated circuit pin number identification. Two decoders decode the voltage level specification and integrated circuit pin specification portions of the stored control information, respectively. A switching circuit connected to a source of voltage levels and to the electronic circuit, and responsive to the decoded integrated circuit pin specification, applies to the integrated circuit pin specified by the stored data information a voltage level specified by the decoded voltage level specification. The voltage level is applied as a non-in-line input signal to the integrated circuit pin or a non-in-line output signal from the integrated circuit pin in accordance with the decoded integrated circuit pin specification. Provision is made for employing a data processor to programmatically control the simulation of errors. A process for using the apparatus to develop and evaluate diagnostic programs is disclosed.

Proceedings ArticleDOI
07 Nov 1977
TL;DR: The concept of statistical worst-case, circuit design based on simulation using the 3-sigma circuit models, derived via the solution of quadratic programming is introduced.
Abstract: Introduced in this paper is the concept of statistical worst-case, circuit design based on simulation using the 3-sigma circuit models. Here, the 3-sigma model is defined as a model, which, if being utilized for circuit analysis, will simulate the performance of a circuit design which is 3-sigma away from the nominal characteristics. For illustrations, the 3-sigma circuit models of an ECL circuit design are derived via the solution of quadratic programming.

Journal ArticleDOI
TL;DR: The design details and achieved performance of each of the major elements of the technology are described, including the 1A Processor and several esss.
Abstract: The physical design of large electronic switching systems (esss) requires a comprehensive set of technologies and design tools. The technology used for the 1A Processor and several esss consists of silicon integrated circuits, thin-film hybrid circuits, discrete component packaging, and apparatus to interconnect, power, and communicate with these devices. The application tools consist of comprehensive design guidelines and computer aids for circuit, logic, thermal, and physical design. In addition, computer aids are provided for documentation and preparation of information for manufacturing and testing. This paper uses text and illustrations to describe the design details and achieved performance of each of the major elements of the technology.

Journal ArticleDOI
TL;DR: A new computer program CALMOS has been developed for the automatic layout of MOS-LSI circuits and provides an automatic 100% routing with emphasis on the minimization of the interconnection area.
Abstract: A new computer program CALMOS has been developed for the automatic layout of MOS/LSI circuits. It provides an automatic 100-percent routing with emphasis on the minimization of the interconnection area. The program runs on a minicomputer and allows for interactive design.

Proceedings ArticleDOI
07 Nov 1977
TL;DR: The initial design of a comprehensive hierarchical intergrated circuit design system, intended for the design and layout of large-scale integrated circuits by means of a combination of manual and algorithmic techniques is described.
Abstract: This paper describes the initial design of a comprehensive hierarchical intergrated circuit design system, that is currently being implemented at Stanford University. This system encourages the use of structured hardware design techniques. It is intended for the design and layout of large-scale integrated circuits by means of a combination of manual and algorithmic techniques.

Journal ArticleDOI
TL;DR: The circuit-design aspects of an integrated circuit to perform two-tone telephone dialing are described, believed to be unique in that it combines both the crystal-controlled frequency synthesizer and the output amplifier on the same chip.
Abstract: The circuit-design aspects of an integrated circuit to perform two-tone telephone dialing are described. The circuit is believed to be unique in that it combines both the crystal-controlled frequency synthesizer and the output amplifier on the same chip. Moreover, no external power supplies are required; the circuit is powered by the telephone-line current. Designed to require a minimum number of external components, the LSI chip provides an economical and accurate two-tone dialing unit. A typical application circuit for existing telephone apparatus is shown and aspects of future development are discussed.

Proceedings ArticleDOI
01 Jan 1977
TL;DR: The computer-aided system described herein has been a significant factor in the rapid development of No. 4 ESS and the benefits of computerized data generated from design inception through manufacturing and testing applications has been realized.
Abstract: An overview is given of the development and operation of a large computer-aided design (CAD) system for the physical realization and documentation of Electronic Switching Systems. The No. 4 ESS physical characteristics contain frames of equipment which include a large number of plug-in digital logic thin film circuit packs.An integrated computer support system with data base management control has been developed to assist in the design of such systems. Specifications for the CAD system were jointly established by user and programming teams.The CAD system is used in a hierarchial manner. Programs are executed to design and build data bases at the circuit pack level. These data bases then form the building blocks to progess to the next level of circuit pack electrical interconnection or frame level of design and documentation. Subsequent use of the frame level data base, together with a data base which describes the physical (geometric) relationship of circuit packs in the frame yields still another data base which contains backplane detailed wiring requirements.The entry of design changes and the data base management of the large number of data bases are accomplished by the formal application of data verification and check programs following each change transaction.The computer-aided system described herein has been a significant factor in the rapid development of No. 4 ESS. Cost and schedule effectiveness has been achieved. The benefits of computerized data generated from design inception through manufacturing and testing applications has been realized.

Journal ArticleDOI
TL;DR: CAD methods for I/SUP 2/L circuits that permit the use of existing, tried CAD programs are described and illustrated, and their application in the design of the I/Sup 2-L basic gate, computer simulation of I/ SUP 2/ L logic circuits, interconnection pattern generation, and preparation of a final layout plan are illustrated.
Abstract: Thanks to the simple, regular structure of its basic gates, integrated injection logic (I/SUP 2/L) is particularly suited to automated design (CAD) procedures for evolving large-scale integrated digital circuits. This paper describes CAD methods for I/SUP 2/L circuits that permit the use of existing, tried CAD programs, and illustrates their application in the design of the I/SUP 2/L basic gate, computer simulation of I/SUP 2/L logic circuits, interconnection pattern generation, and preparation of a final layout plan.

Patent
22 Jul 1977
TL;DR: In this paper, an integrated circuit comprises components for the basic functions of a timepiece and additional components for controlling the operation mode of the basic components, which can be applied to two or more types of timepieces, thereby reducing the kinds of integrated circuits that need to be prepared.
Abstract: An integrated circuit comprises components for the basic functions of a timepiece and additional components for controlling the operation mode of the basic components. By properly controlling the operation mode of the basic components, the integrated circuit can be applied to two or more types of timepieces, thereby reducing the kinds of the integrated circuits that need to be prepared.

Proceedings ArticleDOI
07 Nov 1977
TL;DR: SICLOPS as mentioned in this paper is a new IC mask layout code, which avoids most of the problems inherent in the present generation of layout codes such as lack of flexibilityy inefficient use of area, and restricted design complexity.
Abstract: A new automatic IC mask layout code, SICLOPS is being developed which avoids most of the problems inherent in the present generation of layout codes such as lack of flexibilityy inefficient use of area, and restricted design complexity. The basic architecture, philosophy, and assumptions used in developing the code are described.


Journal ArticleDOI
TL;DR: A symbolic layout technique, associated with network recognition programs, enables a fast and secure design that has been applied to CMOS technology and practical results demonstrate its efficiency.
Abstract: A design method, based upon the use of standardized basic elements is proposed. A symbolic layout technique, associated with network recognition programs, enables a fast and secure design. That method has been applied to CMOS technology and practical results demonstrate its efficiency.

Proceedings ArticleDOI
01 Feb 1977
TL;DR: In this article, the authors present a translation of SAE PREPRINT 770292 to all PHASES OF ENGINEERING DESIGN, ESPECIALLY CAR DESIGN.
Abstract: IN ORDER TO REDUCE THE CORROSION OF A JOINT COMPRISING SEVERAL METALS IT IS NECESSARY TO UNDERSTAND THE BASIC PROCESSES OF SOME TYPES OF CORROSION AND TO RECOGNIZE THE FACTORS INFLUENCING THE RATE OF CORROSION. ONCE THIS HAS BEEN UNDERSTOOD, THE DATA ARE APPLIED TO ALL PHASES OF ENGINEERING DESIGN, ESPECIALLY CAR DESIGN, E.G., THE SELECTION OF MATERIALS, PREVENTIVE MEASURES AND PHYSICAL DESIGN. THE FINAL STAGE MUST BE THE DETERMINATION OF THE POSSIBILITY OF APPLYING THE DESIGN OF MECHANICAL COMPONENTS. THE DISCUSSION DEALS WITH EACH OF THE SPECIFIC FIELDS WHICH FORM THE OVERALL DESIGN. THIS IS A TRANSLATION OF SAE PREPRINT 770292.

Journal ArticleDOI
TL;DR: The interconnection algorithm originally presented by Lee is outlined and some of its features are discussed and it is shown that for multilayer hybrid microcircuits the algorithm can be extended to advantage.
Abstract: The interconnection algorithm originally presented by Lee is outlined and some of its features are discussed. The implications of the various technologies to which it may be applied are presented, and it is shown that for multilayer hybrid microcircuits the algorithm can be extended to advantage. Typical results using the extended algorithm are given.

Proceedings ArticleDOI
21 Jun 1977
TL;DR: A simple analogue simulator is used to define circuit topology with lumped and distributed elements, to vary circuit parameters and to continuously display the frequency response.
Abstract: A simple analogue simulator is used to define circuit topology with lumped and distributed elements, to vary circuit parameters and to continuously display the frequency response. Parameter sensitivity can also be tested. Applications are given.

Journal ArticleDOI
TL;DR: In this article, the design of a bidirectional transistor sampling gate with prescribed specifications is presented, and the design and circuit implementation is followed by the analysis of the designed circuit.
Abstract: This design presents the principles and circuit of the sampling gate. The design of a bidirectional transistor sampling gate with prescribed specifications is presented. The introduction to the subject precedes a brief resume on conventional samplers The design and circuit implementation is followed by the analysis of the designed circuit. A discussion of stability, thermal runway and accuracy is included. A list of electronic parts used in the design project is also appended.