Showing papers on "Physical design published in 1980"

Built-in test for complex digital integrated circuits

Abstract: A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).

Algorithms for integrated circuit layout: an analytic approach

Abstract: In this thesis, the problem of designing the layout of integrated circuits is examined. The layout of an integrated circuit specifies the position of the chip of functional components and wires interconnecting the components. We use a general model under which components are represented by rectangles, and wires are represented by lines. This model can be applied to circuit components defined at any level of complexity, from a transistor to a programmable logic array (PLA). We focus on the standard decomposition of the layout problem into a placement problem and a routing problem. We examine problems encountered in layout design from the point of view of complexity theory. The general layout problem under our model is shown to be NP-complete. In addition, two problems encountered in a restricted version of the routing problem --channel routing--are shown to be NP-complete. The analysis of heuristic algorithms for NP-complete problems is discussed, and the analysis of one common algorithm is presented. The major result presented in this dissertation is a polynomial time algorithm for a restricted case of the routing problem. Given one rectangular component with terminals on its boundary, and pairs of terminals to be connected, the algorithm will find a two-layer channel routing which minimizes the area of a rectangle circumscribing the component and the wire paths. Each terminal can appear in only one pair of terminals to be connected, and the rectangle used to determine the area must have its boundaries parallel to those of the component. If any of the conditions of the problem are removed, the algorithm is no longer guaranteed to find the optimal solution.

Vertical integrated circuit package integration

Abstract: A compact assembly of similar type integrated circuit packages having a functionally similar terminal lead in non-corresponding lead positions Two interconnection packages, of a type similar to the integrated circuit packages, are nested between the integrated circuit packages to re-route an electrical path from a terminal lead location on one integrated circuit package to a functionally similar but differently located lead position on the other integrated circuit package

Complexity Theory and Design Automation

Abstract: Complexity Theory is discussed and its relationship to Physical Design (i.e. Placement/Wiring) and Test Pattern Generation is shown and developed.

A Dense Gate Matrix Layout Method for MOS VLSI

Abstract: A rapid and systematic method for performing chip layout of VLSI circuits is described. This method utilizes the configuration of a matrix composed of interacting rows and columns to provide transistor placement and interconnections. This structure, which is orderly and regular, gives high device-packing density and allows ease of checking for layout errors. Resulting layouts may be updated to new design rules automatically. This method has been used in the layout of a 20 000-transistor section of a VLSI circuit.

Macro assembler process for automated circuit design

Abstract: A process automatically generating topology data for fabricating large scale integrated circuits. Technology data, a logic function description and logic circuit components are generated and input to a data processing system together with geometric dimension data descriptive of the basic elements of the logic circuit components. The geometric dimension data is assembled into a plurality of intermediate level geometric topology patterns under control of the logic function description and the intermediate level geometric topology patterns are assembled into a prime level geometric topology representative of the logic function description. The logic circuit components are merged with the prime level geometric topology to produce a grid array to be fabricated into a large scale integrated circuit.

Yield optimization for arbitrary statistical distributions: Part II-Implementation

Abstract: A suggested test problem for proposed algorithms in yield optimization is described in detail. The problem is a current switch emitter follower (CSEF) circuit originally described by Ho, which includes a transmission line. The ideas presented in Part I of this paper [1] are applied to this circuit in order to obtain an optimal statistical design. Production yield is maximized taking into consideration statistical distributions of circuit parameters and realistic correlations between transistor model parameters. Nonlinear programming employing the analytical formuias for yield and its sensitivities is used to provide optimal nominal values for the circuit parameters. Different design specifications are assumed and corresponding optimal designs are obtained.

An Over-The-Cell Router

Abstract: A program that produces single-layer planar routing over the cells for I2L and LST2L logic arrays is described. This router has been integrated into a layout system which was previously restricted to the layout of standard cell LSI chips. When used in conjunction with a channel router, the complete routing is produced automatically. This paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.

Design of large ALUs using multiple PLA macros

Abstract: This paper describes methods of designing large Arithmetic and Logical Units (ALUs) using multiple Programmable Logic Array (PLA) macros in which the outputs are obtained in one cycle corresponding to one pass through any PLA. The design is based on the well-known technique of providing conditional sums and group carries in parallel and selecting the proper sum using gating circuits. The PLA for each group of bits uses an adder design published by Weinberger in which each bit of the sum is formed from the EXCLUSIVE-OR of two outputs of the OR array. By placing the gating circuits in front of the EXCLUSIVE-OR circuits, the sums can be obtained using two array outputs for each bit and one additional OR array output for each internal string of bits. Also discussed are how ALUs containing more than two groups can obtain the group carries using a separate carry-look-ahead PLA macro and how this macro can be compressed by using special decoders and special physical design layout techniques. Additionally, the paper demonstrates how the PLAs can be used to provide detection of overflow and of zero results, and to also provide Boolean operations.

An Integrated Mask Artwork Analysis System

Abstract: A new LSI artwork analysis and processing system, called EMAP, is described with algorithms, a database schema and applications. EMAP provides the designer with the artwork verification and processing tools which include mask artwork processing, geometrical design rule checking, connectivity analysis and electrical circuit parameter calculation. The circuit connectivity data derived from the mask artwork data is used for input to a logic simulator, a timing simulator, a circuit simulator and a circuit schematic generator.

Toward a practical computer-aid for thyristor circuit design

Abstract: It is shown that using only thyristor data sheets and a popular, easy-to-use circuit simulation program (SPICE) readily available to the public one can perform thyristor circuit simulations as a design aid.

A Simple Model of Circuit Design

Abstract: : A Simple analog circuit designer has been implemented as a rule based system. The system can design voltage followers, Miller integrators, and bootstrap ramp generators from functional descriptions of what these circuits do. While the designers works in a simple domain where all components are ideal, it demonstrates the abilities of skilled designers. While the domain is electronics, the design ideas are useful in many other engineering domains, such as mechanical engineering, chemical engineering, and numerical programming. Most circuit design systems are given the circuit schematic and use arithmetic constraints to select components values. This circuit designer is different because it designs the schematic. The designer uses a unidirectional CONTROL relation to find the schematic. The circuit designs are built around this relation; it restricts the search space, assigns purposes to components, and finds design bugs.

A Computer-Aided Design System for Hybrid Circuits

Abstract: A software system used to aid hybrid circuit design, layout, and documentation is described. The intent of the programs is to address the design needs of a company that requires a considerable number of new custom hybrids each year. The system, called HCAD, resides on a mainframe engineering computer and is available to designers on a time-share basis via interactive graphics terminals. The system acts as a design aid for the user by handling difficult computations and by storing large amounts of data while leaving most of the creative tasks to the user.

A Hierarchical Approach for Layout Versus Circuit Consistency Check

Abstract: This paper describes a CAD program which checks the circuit topology and the electrical parameters from the IC layout data against the user supplied circuit descriptions. Taking advantage of the hierarchical characteristics of the layout data, the program achieves an efficient analysis and does a clear presentation of the results.

A high performance sense amplifier for a 5 V dynamic RAM

Abstract: Increasing dynamic RAM cell density and the use of a single low-voltage power supply have made it mandatory to store the full power supply voltage in the cell and to be able to detect smaller signals reliably with the initial sense amplifier. The authors present a circuit design approach that restores the cell to a full V/SUB DD/ `1' level, preamplifies the initial charge imbalance before sensing by conventional techniques, and is used in the Fairchild 64K design. Design requirements and a detailed analysis of the amplifier are presented along with simulated results, followed by performance data. The circuit analysis shows how the key design parameters should be chosen and the effects of clock timing variations on the performance of the sense amplifier.

Modelling and verification in structured integrated circuit design

Abstract: Traditional design tools based on geometric representations do not provide an adequate base from which to construct and verify silicon implementations of complex systems. More comprehensive structural, physical and behavioural descriptions must be developed from appropriate representations. This thesis proposes models which may be used to construct unified and consistent descriptions of the structural, physical and behavoural attributes of a design. It also discusses a method of capturing these descriptions using a textual representation embedded in an object oriented programming language. A range of subsytems have been implemented within a design environment tailored to the proposed models of the design activitiy. In addition to the typical graphical feedback and mask making oriented output a comprehensibe list of verificaiton procedures has been integrated into the system. These include dimensional design rule checking, electrical calculations, connectivity verification and simulation at a number of levels of abstraction.

Computer Modeling of Monolithic GaAs IC's

Abstract: The design of GaAs monolithically integrated circuits in the RF and low microwave frequency range is a process resembling low frequency IC design more than microwave circuit design. These GaAs circuits are directly coupled on-chip in a high-impedance environment. Since tuning and matching elements are not used, the traditional microwave CAD technique of computer optimizing passive element values is not required. Rather, the task of the GaAs IC designer is to predict with computer simulation what the performance of a proposed circuit design will be, then iterate as necessary to achieve the required results.

From Electron Mobility to Logical Structure: A View of Integrated Circuits

Abstract: The microprocessor's rapid development and its appearance in many Dew theaters of application are bringing computer scientists and programming specialists increasingly into contact with new and largely unfamiliar products of integrated circuit technology. This tutorial paper introduces some of the main ideas underlying the theory, fabrication, and operation of integrated circuits and shows how logically useful functions ~ e derived from the balancing and unbalancing of electric charge in tiny semiconductor-based structures.

SIDS - A Symbolic Interactive Design System

Abstract: A new production approach to IC mask layout/checking is described which makes use of a combination of symbolic layout, computer checking and color graphics to resolve some of the problems in currently available layout systems. Techniques such as on-line design rule and connectivity checking, not found in other production systems, give the user "instant" feedback as he is designing.

Computer aided design tools for VLSI

Abstract: The computer-aided design segment of the IC industry has had some success with tools to help with the LSI design problem. Particularly, circuit and logic simulation, layout graphics, and design rule checking have been very useful. Other areas, such as testing and modeling, continue to present challenges at the LSI level. As VLSI structures become a reality, new magnitudes of CAD tools will be needed. Can existing tools be scaled to solve the problem or will new approaches be required?

CASSIOPEE-An Integrated CAD System for Integrated Circuits

Abstract: After having first introduced what is an integrated CAD system and the functions it has to perform, this paper describes the particularities of CASSIOPEE, a prototype under development at CNET-GRENOBLE, of its realization, and of the timing simulator which is its first running component.

TRICKY : Symbolic Layout System for Integrated Circuits

Abstract: TRICKY is an aid for the layout step of the integrated circuits design Starting from a symbolic sketch it automatically computes the accurate and compacted layout of the corresponding masks

Special Feature: Instruction in MOS LSI Systems Design

Abstract: Designers of next-generation computers will employ a building-block approach reflecting the interdependence of system architecture and IC design. This course prepares for that approach.

The VLSI design challenge of the 80's (Position Statement)

Abstract: The primary focus of design automation for VLSI in the 80's will not be the development of sophisticated new design tools, but rather the development of design methodologies which can utilize effectively 108 transistors/chip. Computer aids will be developed to support the management of these design methodologies, both for relatively simple synthesis tasks as well as the verification of circuits as they are generated.At the present time it is not clear which design methodology will be the most successful for any particular class of applications of VLSI. For this reason, design systems should be developed in a flexible manner to allow easy reconfiguration as new approaches to the design process emerge. The structure of one such system is shown in Fig. 1. In this approach the design tools are applied to the hierarchical data base under the control of a supervisory program, or shell, which can be reconfigured and adapt the system as new tools are added, or as the data base and/or representations of the design are altered. In this way, the designer observes the minimum perturbation as the system is updated.

Picture-processing techniques for geometrical tolerance checking of integrated-circuit layouts

Abstract: The checking of geometrical constraints on integrated-circuit layouts is notoriously slow and costly when carried out purely by software. This paper introduces a new approach, in which layers are converted into digitised pictorial form and processed by simple hardware operating like a computer peripheral. This hardware reports to the computer all cases where constraints may be violated, and these cases are investigated in detail purely by software. The advantage of this approach is the reduction in the total amount of c.p.u. time required for constraint checking.

Integrated circuits for local digital switching line interfaces

Abstract: Technological advances make exploitation of the most advanced ideas in telecommunications systems, economically feasible. The purpose of this paper is to review the functional and interface requirements, as well as circuit and technology alternatives for integrated circuit codecs, filters, and line interfaces.