Journal ArticleDOI
Built-in test for complex digital integrated circuits
B. Konemann,G. Zwiehoff,J. Mucha +2 more
TLDR
In this paper, a method for testing the logic function of complex digital integrated circuits is presented, which is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).Abstract:
A method for testing the logic function of complex digital integrated circuits is presented. The extra hardware needed is kept minimal by functional conversion of already existing components (e.g., registers). The feasibility of the proposed method is demonstrated by results from both hardware simulation and logic simulation. The method is based on an adapted version of signature analysis, and on circuit partitioning (the structure of VLSI circuits is assumed to be inherently modular).read more
Citations
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Journal ArticleDOI
Built-In Self-Test Techniques
TL;DR: The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Journal ArticleDOI
Design for Autonomous Test
McCluskey,Bozorgui-Nesbat +1 more
TL;DR: A technique for modifying networks so that they are capable of self test is presented, partitioning the network into subnets with sufficiently few inputs that exhaustive testing of the subnetworks is possible.
Journal ArticleDOI
Circular self-test path: a low-cost BIST technique for VLSI circuits
Andrzej Krasniewski,S. Pilarski +1 more
TL;DR: Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test.
Journal ArticleDOI
Fundamentals of electron beam testing of integrated circuits
E. Menzel,Erich Kubalek +1 more
References
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Proceedings ArticleDOI
A logic design structure for LSI testability
TL;DR: A logic design method that will greatly simplify problems in testing, diagnostics, and field service for LSI is described, based on two concepts that are nearly independent but combine efficiently and effectively.
Journal ArticleDOI
Encoding and error-correction procedures for the Bose-Chaudhuri codes
TL;DR: A simple error-correction procedure for binary codes which for arbitrary m and t are t -error correcting and have length 2^m - 1 of which no more than mt digits are redundancy is described.
Journal ArticleDOI
Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic
M.J.Y. Williams,J.B. Angell +1 more
TL;DR: With the increasing complexity of logic that can be fabricated on a single large-scale integrated (LSI) circuit chip, there is a growing problem of checking the logical behavior of the chips at manufacture.
Journal ArticleDOI
Polynomially Complete Fault Detection Problems
Oscar H. Ibarra,Sartaj Sahni +1 more
TL;DR: Several variations of the single fault detection problem for combinational logic circuits are looked at and it is shown that deciding whether single faults are detectable by input-output (I/O) experiments is polynomially complete, i.e., there is a polynomial time algorithm to decide if they are detectable.
Journal ArticleDOI
An Advanced Fault Isolation System for Digital Logic
TL;DR: The Navy funded Advanced Avionics Fault Isolation System (AAFIS) concept utilizes BIT logic for cost-effective fault detection and fault isolation to a digital subsystem and to the faulty module therein.