Showing papers on "Remainder published in 1996"

Chinese remainder theorem: applications in computing, coding, cryptography

Abstract: Introduction and philosophy Chinese remainder algorithm in modular computations in algorithmics in bridging computations in coding theory in cryptography tutorial in information theory tutorial in algebra list of mathematical symbols.

5. Remainder Differential Algebras and Their Applications

Abstract: In many practical problems in which derivatives are calculated, their basic purpose is to be used in the modeling of a functional dependence, often based on a Taylor expansion to first or higher orders. While the practical computation of such derivatives is greatly facilitated and in many cases is possible only through the use of forward or reverse computational differentiation, there is usually no direct information regarding the accuracy of the functional model based on the Taylor expansion. We show how, in parallel to the accumulation of derivatives, error bounds of all functional dependencies can be carried along the computation. The additional effort is minor, and the resulting bounds are usually rather sharp, in particular at higher orders. This Remainder Differential Algebraic Method is more straightforward and can yield tighter bounds than the mere interval bounding of the Taylor remainder’s (n +1 )st order derivative obtained via forward differentiation. The method can be applied to various numerical problems: Here we focus on global optimization, where blow-up can often be substantially reduced compared with interval methods, in particular for the cases of complicated functions or many variables. This problem is at the core of many questions of nonlinear dynamics and can help facilitate a detailed, quantitative understanding.

Method and system of rounding for division or square root: eliminating remainder calculation

Abstract: A method and system which provides exactly rounded division and square root results for a designated rounding mode independently of a remainder, or equivalent calculation of the relationship between the remainder and zero, for predetermined combinations of the rounding mode and the guard digit of an estimate that has several more bits of precision than the exactly rounded result, and has an error tolerance magnitude less than the weight of the least significant bit of the estimate. The estimate is generated in accordance with a quadratically converging division or square root algorithm. The method and system is described in connection with IEEE 754-1985 and IBM S/390 binary floating point architectures.

A new non-restoring square root algorithm and its VLSI implementations

Abstract: We present a new non-restoring square root algorithm that is very efficient to implement. The new algorithm presented here has the following features unlike other square root algorithms. First, the focus of the "non-restoring" is on the "partial remainder", not on "each bit of the square root", with each iteration. Second, it only requires one traditional adder/subtracter in each iteration, i.e., it does not require other hardware components, such as seed generators, multipliers, or even multiplexors. Third, it generates the correct resulting value even in the last bit position. Next, based on the resulting value of the last bit, a precise remainder can be obtained immediately without any correction or addition operation. And finally, it can be implemented at very fast clock rate because of the very simple operations at each iteration. We illustrate two VLSI implementations of the new algorithm. One is a fully pipelined high-performance implementation that can accept a new square-root instruction each clock cycle with each pipeline stage requiring a minimum number of gate counts. The other is a low-cost implementation that uses only a single adder/subtractor for iterative operation.

Quotient digit selection logic for floating point division/square root

Abstract: Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. In an alternative embodiment, where the upper four bits of the estimated partial remainder are ones while the fifth most significant bit is zero, a quotient digit of negative one is chosen. This alternative embodiment allows correct exact results in all rounding modes including rounding toward plus or minus infinity.

System and method for reducing memory fragmentation by assigning remainders to share memory blocks on a best fit basis

Abstract: A system and method for storing variable length objects such that memory fragmentation is reduced, while avoiding the need for memory reorganization. A remainder of a variable length object may be assigned to share a fixed-size block of storage with a remainder from another variable length object (two such remainders which share a block are referred to as roommates) on a best fit or first fit basis. One remainder is stored at one end of the block, while the other remainder is stored at the other end of the block. The variable length objects which are to share a block of storage are selected from the same cohort. Thus, there is some association between the objects. This association may be that the objects are from the same page or are in some linear order spanning multiple pages, as examples. Information regarding the variable length objects of a cohort, such as whether an object has a roommate, is stored in memory.

Asymptotics of the Spectrum of Douglis - Nirenberg Elliptic Operators on a Compact Manifold

Abstract: Pseudo- differential systems on closed manifolds, elliptic in the sense of DOUGLIS and Nirenberg. are considered. It is proved that the system is similar to an diagonal operator up to an operator of order - ∞, and the similarity transformation preserves ellipticity and parameter -ellipticity. The similarity transformation may be chosen so that it preserves even self adjointness up to an operator of order less than the lowest order of the diagonal entry. These results are applied to prove the eigenvalue asymptotics with the sharp estimate of the remainder in the self adjoint case as well as a rough asymptotics in the non-self-adjoint case. Another application is the eigenvalue asymptotics with the sharp estimate of the remainder for general self- adjoint elliptic boundary value problems with the spectral parameter appearing linearly in boundary conditions.

Fast IEEE Rounding for Division by Functional Iteration

Abstract: A class of high performance division algorithms is functional iteration. Division by functional iteration uses multiplication as the fundamental operator. The main advantage of division by functional iteration is quadratic convergence to the quotient. However, unlike non-restoring division algorithms such as SRT division, functional iteration does not directly provide a final remainder. This makes fast and exact rounding difficult. This paper clarifies the methodology for correct IEEE compliant rounding for quadratically-converging division algorithms. It proposes an extension to previously reported techniques of using extended precision in the computation to reduce the frequency of back multiplications required to obtain the final remainder. Further, a technique applicable to all IEEE rounding modes is presented which replaces the final subtraction for remainder computation with very simple combinational logic.

Division algorithm for floating point or integer numbers

Abstract: A computer-implemented algorithm for dividing numbers involves subtracting the divisor from the divided to generate a first intermediate result, which is then shifted by N-bits to obtain a remainder value. A portion of the remainder and a portion of the divisor are utilized to generate one or more multiples from a look-up table, each of which is multiplied by the divisor to generate corresponding second intermediate results. The second intermediate results are subtracted from the remainder to generate corresponding third intermediate results. The largest multiple which corresponds to a third intermediate result having a smallest positive value is the quotient digit. The third intermediate result that corresponds to the largest multiple is the remainder for the next iteration.

Trace asymptotics via almost analytic extensions

Abstract: In this work we give a stationary approach to results on trace asymptotics with small remainder estimates, which in this degree of generality are due to Ivrii [I], who followed the more traditional method (for getting sharp estimates) of studying the trace of an associated unitary evolution group. The originality of Ivrii’s results is that he does not require any parametrix constructions, and this permitted him to get very general results. For earlier results with parametrix constructions see Hormander [H], Chazarain [C], Helfer-Robert [HeR]. That stationary methods can also produce sharp remainder estimates is known. See Metivier [M].

Device for carrying out a division

Abstract: This device is designed for carrying out a division of a dividend A formed by "m" words with a base "b" by a divisor D. It comprises an active memory (2), a multiplication member which forms part of a calculation unit (8) provided with a first input (x i ) for "x" words of a multiplicand and with a second input (A i ) for "y" words of a multiplier. Accumulating means are provided for adding to locations of the memory (2) a multiple of a quantity db k · b j worked out by the said multiplication member, as well as testing means for providing an indication of the zero value of a separator S in the said location, and for activating the cumulation means until the testing means provide the said indication, as well as decrementation means for decrementing the value J at each indication. The remainder of the division is present in the last locations, and the quotient in the first ones.

Ramsey-remainder

Abstract: We investigate the following Ramsey-type problem. Given a natural numberk,determine the smallest integerrr(k)such that, ifnis sufficiently large with respect tok,andSis any set ofnpoints in general position in the plane, then all but at mostrr(k)points ofScan be partitioned into convex sets of sizes ⩾ k.We provide estimates onrr(k)which are best possible if a classic conjecture of Erdos and Szekeres on the Ramsey number for convex sets is valid. We also prove that in several types of combinatorial structures, the corresponding ‘Ramsey-remainder’rr(k)is equal to the off-diagonal Ramsey numberr(k, k-1)minus 1.

The division algorithm in complex bases

Abstract: Complex numbers can be represented in positional notation using certain Gaussian integers as bases and digit sets. We describe a long division algorithm to divide one Gaussian integer by another, so that the quotient is a periodic expansion in such a complex base. To divide by the Gaussian integer w in the complex base b, using a digit set D, the remainder must be in the set wT(b,D) ∩ ℤ[i], where T(b,D) is the set of complex numbers with zero integer part in the base. The set T(b,D) tiles the plane, and can be described geometrically as the attractor of an iterated function system of linear maps. It usually has a fractal boundary. The remainder set can be determined algebraically from the cycles in a certain directed graph.

Embedding grids into grids: Techniques for large compression ratios

Abstract: We return to the problem of embedding 2-dimensional (h x w) guest grid graphs into 2-dimensional (h' X w') host grid graphs, where w' < w, and h' is the smallest integer such that hw < h'w'. This 2-dimensional problem has many applications in computer science including the simulation of one grid of processors by another of different shape. Also, it can likely be applied to more complex problems such as those involving grids of higher dimension and hypercubes. It is already known that optimal dilation, namely two, is always obtainable whenever w/w', the compression ratio, is no greater than two. Only a restricted set of problem instances with compression ratios greater than two could previously be solved optimally, with respect to dilation. We introduce two new techniques, called folding with compression and folding with extension. By applying folding with compression, we show that optimal solutions always exist if w' ≥ 7h and the remainder of h' integer divided by h is no greater than h' integer divided by h. This condition includes all instances of the problem for which w/w' ≥ h ≥ 7, i.e., all instances for which the compression ratio and h are sufficiently large. There remain instances, among those of intermediate compression ratio, for which we still do not have optimal solutions. We show that some, but not all, of these can be solved by appling folding with extension.

Genetic algorithm behaviour in the solution of an inverse thermal field problem

Abstract: Discusses the performance of a simple genetic algorithm (GA) applied to a one‐dimensional inverse thermal field problem. Builds on these results by considering changes in GA performance that result from the introduction of non‐complementary crossover, stochastic remainder sampling and a combination of the two. Shows that, in comparison to the simple GA, non‐complementary cross‐over provides more rapid convergence, while stochastic remainder sampling without replacement has the opposite effect. However, when both strategies are combined, they provide considerably better performance with greater diversity within the population.

Bidirectional exact integer division

Abstract: Division of integers is calledexactif the remainder is zero. We show that the high-order part and the low-order part of the exact quotient can be computed independently from each other. A sequential implementation of this algorithm is up to twice as fast as ordinary exact division and four times as fast as the general classical division algorithm if the dividend is twice as long as the divisor. A shared-memory parallel implementation on two processors gains another factor of two in speed.

Computing by homomorphic images

Abstract: The Chinese remainder method has already been investigated by Chinese mathematicians more than 2000 years ago. For a short introduction to the history we refer to Knuth (1981). The main idea consists of solving a problem over the integers by solving this problem in several homomorphic images modulo various primes, and afterwards combining the solutions of the modular problems to a solution of the problem over the integers. In fact, the method can be generalized to work over arbitrary Euclidean domains, i.e., domains in which we can compute greatest common divisors by the Euclidean algorithm. An interesting list of different statements of the Chinese remainder theorem is given in Davis and Hersh (1981).

Computer for performing non-restoring division

Abstract: A computer that performs division in either floating point or integer representation according to a novel algorithm in which a divisor is subtracted from a dividend to generate a first intermediate result. A shifter shifts the intermediate result by N-bits, where N is an integer and 2 N is equal to the radix, to obtain a remainder. A look-up table produces one or more multipliers based upon an upper-bit portion of the remainder and an upper-bit portion of the divisor. The divisor is multiplied by each of the one or more multiples to generate second intermediate results. Each of the secondary intermediate results is then subtracted from the remainder to generate one or more corresponding third intermediate results. A current quotient digit is selected as the largest multiplier which corresponds to the third intermediate result having the smallest possible value (as among all of the third intermediate results).

Special Cases of Division

Abstract: This surveys algorithms and circuits for integer division in special cases. These include division by constants, small divisors, exact divisors, and cases where the divisor and the number base have a special relationship. The related operation of remainder is also covered. Various prior techniques are treated in a common framework. Worked examples are provided together with examples of practical application.

Digital microprocessor device having variable-delay division hardware

Abstract: The present invention is a variable-delay division (VDD) scheme implementable in hardware to execute signed and unsigned integer division and remainder operations in digital processor. The VDD scheme advantageously uses hardware utilized for multiplication to implement a 2-bits/cycle alignment step to iteratively align the divisor with the dividend. This speeds up the alignment phase of integer division. Quotient bits are produced at the rate of 1-bit/cycle using the well-known restoring scheme. For 32-bit 2's complement operands, the scheme has a delay less than a fixed-delay scheme for most operands.

An accurate time domain interconnect model of transmission line networks

Abstract: In this paper, we present a new time domain model of interconnects modeled as transmission line networks. Each element of the characteristics of a transmission line is modeled by a principal part and a remainder. The principal part consists of an impulse and an exponential function, whose Laplace transform matches the original function at infinity frequency with order 1 and at zero frequency with order 0. The remainder in the time domain consists of a cubic polynomial for a single line and a piecewise cubic polynomial for coupled lines. The model is stable, accurate, simple, and efficient to use.

Power remainder operation circuit, power remainder operation system and operation method for power remainder operation

Abstract: PROBLEM TO BE SOLVED: To execute various kinds of operations only by supplying a mode signal prepared in advance in the case of finding the solution of power remainder operation. SOLUTION: At the power remainder operation circuit of M modN, this circuits is provided with an arithmetic part for executing the 1st operation of A.A.R' modN (R' is the inverse of R under the method of modN) in response to a timing control signal corresponding to a 1st mode signal while using an integer R which a prime with N and larger than N, executing the 2nd operation of A.B.R' modN in response to a timing control signal corresponding to a 2nd mode signal while using the integer R and executing the 3rd operation of A.1.R' modN in response to a timing control signal corresponding to a 3rd mode signal while using the integer R and a timing control circuit T/C for outputting the timing control signal corresponding to the 1st or 3rd mode signal to the arithmetic part.

A uniform asymptotic expansion for the jacobi polynomials with explicit remainder

Abstract: A new asymptotic expansion is derived for the Jacobi polynonmial which holds uniformly for .An explicit expression is also given for the error term associated with the expansion. Our approach begins with a contour integral representation, followed by a suitable canonical transformation.

Encoder and decoder of an error correcting code

Abstract: An encoder and a decoder of an error correction code. A first division pattern generating circuit generates an n bit first division pattern used for dividing inputted n significant bit data in the next cycle from an n bit remainder obtained by dividing inputted data until then and inputted n less significant bit data. A second division pattern generating circuit generates an n bit second division pattern for dividing inputted n less significant bit data from the n bit remainder obtained by dividing inputted data until then. Therefore, the present invention provides the encoder and the decoder of a 2n parallel error correcting code which allows data to be coded and decoded, irregardless of whether the error correcting code is in the n more significant bits or the n less significant bits of a 2n parallel data bus.

Subtraction/shift-type dividing device producing a 2-bit partial quotient in each cycle

Abstract: A first subtracting means subtracts divisor data from dividend data or partial remainder data. In parallel with the subtraction of the first subtracting means, a comparing means performs a comparison between the highest-3-bit data of the dividend or partial remainder data and that of the divisor data. A first selecting means supplies, after shifting leftward by one bit, the dividend data or partial remainder data, or output data of the first subtracting means to a second subtracting means in accordance with a comparison result of the comparing means. A 2-bit partial quotient is determined based on the comparison result of the comparing means and subtraction results of the first and second subtracting means. As a result, the critical path is simplified and hence the delay time is shortened.

High-speed remainder arithmetic unit

Abstract: PURPOSE: To perform a high-speed remainder arithmetic operation with less hardware amount by selecting a numerical value for which the relation of a numerator and a denominator satisfies specified conditions and turning it to the input of an adder. CONSTITUTION: By selecting an N for which the relation of the numerator and the denominator satisfies a formula, turning it to the input of a first adder 8 and a second adder 9 and decoding the result in a decoder, the remainder of an arithmetic result is obtained. For instance, (b)=4 is selected in the formula. In this case, since (b) to be the denominator can be expressed as (b)=3+1, for the remainder in the case of dividing a binary number expressed by four bits by 3, the binary number expressed by four bits is decomposed into upper two bits a3 and a2 and lower two bits a1 and a0 and turned to the input of the first adder 8. Since the arithmetic result becomes three bits at maximum, it is decomposed into an upper one bit b2 and lower two bits b1 and b0 and turned to the input of the second adder 9. By encoding the arithmetic result in an encoder 10, the output of d0, d1 and d2 corresponding to remainder values 0, 1 and 2 is obtained.