Showing papers on "Residue number system published in 2021"

A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning

Abstract: Homomorphic Encryption (HE) allows untrusted parties to process encrypted data without revealing its content. People could encrypt the data locally and send it to the cloud to conduct neural network training or inferencing, which achieves data privacy in AI. However, the combined AI and HE computation could be extremely slow. To deal with it, we propose a multi-level parallel hardware accelerator for homomorphic computations in machine learning. The vectorized Number Theoretic Transform (NTT) unit is designed to form the low-level parallelism, and we apply a Residue Number System (RNS) to form the mid-level parallelism in one polynomial. Finally, a fully pipelined and parallel accelerator for two ciphertext operands is proposed to form the high-level parallelism. To address the core computation (matrix-vector multiplication) in neural networks, our work is designed to support Multiply-Accumulate (MAC) operations natively between ciphertexts. We have analyzed our design on FPGA ZCU102, and experimental results show that it outperforms previous works and achieves over an order of magnitude acceleration than software implementations.

Efficient Word Size Modular Arithmetic

Abstract: Modular multiplication is used in a wide range of applications. Most of the existing modular multiplication algorithms in the literature often focus on large size moduli. However, those large moduli oriented modular multiplication solutions are also used to implement modular arithmetic for applications requiring modular arithmetic on moduli of size inferior to a word size i.e., 32/64bits. As it happens, a large majority of applications are using word size modular arithmetic. In this work, we propose a new modular multiplication designed to be computed on one word size only. For word size moduli, in a large majority of instances, our solution outperforms other existing solutions including generalist solutions like Montgomery's and Barrett's modular multiplication as well as classes of moduli like Mersenne, Pseudo-Mersenne, Montgomery-Friendly and Generalized Mersenne.

Technique to Adjust Adaptive Digital Filter Coefficients in Residue Number System Based Filters

Abstract: The paper discusses adaptive filtering using Least Mean Square (LMS) and Recursive Least Square (RLS) algorithms. An algorithm for adjusting the coefficients of an adaptive digital filter in the Residue Number System and a procedure of developed algorithm applying depending on filter length and signal length are proposed. Mathematical modeling of the considered algorithms is performed. Examples are presented to demonstrate how the proposed technique can help the designer in the adjustment of the filter coefficients without the need for extensive trial-and-error procedures. The analysis of the denoising quality and computational complexity is made. Synthetic and real data (earthquake recording) were used while testing. The proposed algorithm surpasses the existing ones like LMS and RLS, and their modifications in a number of parameters: adaptation (denoising) quality, ease of implementation, execution time. The main difference between the developed algorithm is the sequential adaptation of each coefficient with zero error. In the known algorithms, the entire vector of coefficients is iteratively adapted, with some specified accuracy. The iterations (steps) number is determined by the input signal length for all algorithms.

Symmetric Cryptoalgorithms in the Residue Number System

Abstract: This paper presents theoretical backgrounds of the symmetric encryption based on the residue number system. The peculiarities of this approach are that in the case of restoring a decimal number based on its residuals using the Chinese remainder theorem, multiplication occurs by arbitrarily chosen coefficients (keys). It is established that cryptostability of the developed methods is determined by the number of modules and their bit size. In addition, the described methods are found to allow to almost indefinitely increase the block of plain text for encryption, which eliminates the necessity to use different encryption modes.

High-Performance Computation in Residue Number System Using Floating-Point Arithmetic

Abstract: Residue number system (RNS) is known for its parallel arithmetic and has been used in recent decades in various important applications, from digital signal processing and deep neural networks to cryptography and high-precision computation. However, comparison, sign identification, overflow detection, and division are still hard to implement in RNS. For such operations, most of the methods proposed in the literature only support small dynamic ranges (up to several tens of bits), so they are only suitable for low-precision applications. We recently proposed a method that supports arbitrary moduli sets with cryptographically sized dynamic ranges, up to several thousands of bits. The practical interest of our method compared to existing methods is that it relies only on very fast standard floating-point operations, so it is suitable for multiple-precision applications and can be efficiently implemented on many general-purpose platforms that support IEEE 754 arithmetic. In this paper, we make further improvements to this method and demonstrate that it can successfully be applied to implement efficient data-parallel primitives operating in the RNS domain, namely finding the maximum element of an array of RNS numbers on graphics processing units. Our experimental results on an NVIDIA RTX 2080 GPU show that for random residues and a 128-moduli set with 2048-bit dynamic range, the proposed implementation reduces the running time by a factor of 39 and the memory consumption by a factor of 13 compared to an implementation based on mixed-radix conversion.

Digital Filter Architecture With Calculations in the Residue Number System by Winograd Method F (2 × 2, 2 × 2)

Abstract: Improving the technical characteristics of digital signal processing devices is an important problem in many practical tasks. The paper proposes the architecture of a device for two-dimensional filtering in a residue number system (RNS) with moduli of a special type according to the Winograd method. The work carried out the technical parameters theoretical analysis of the proposed filter architecture for different RNS moduli sets by the “unit-gate”-model. In addition, the proposed architecture is compared with known digital filter implementations. The theoretical analysis results showed that the use of the proposed filter architecture makes it possible to increase the signal processing speed by 1.33 – 6.90 times, in comparison with the known device implementations. Also, in the work, the hardware simulation of the proposed filter architecture was performed on FPGA, which showed that the performance of the proposed device is 1.31 – 4.12 times higher than known digital filter architectures. The research results can be used in digital signal processing systems to increase their performance and reduce hardware costs. In addition, the developed architectures can be applied in the development of hardware accelerators for complex digital signals analysis systems.

Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study

Abstract: Processing-in-memory (PIM) has raised as a viable solution for the memory wall crisis and has attracted great interest in accelerating computationally intensive AI applications ranging from filtering to complex neural networks. In this paper, we try to take advantage of both PIM and the residue number system (RNS) as an alternative for the conventional binary number representation to accelerate multiplication-and-accumulations (MACs), primary operations of target applications. The PIM architecture utilizes the maximum internal bandwidth of memory chips to realize a local and parallel computation to eliminates the off-chip data transfer. Moreover, RNS limits inter-digit carry propagation by performing arithmetic operations on small residues independently and in parallel. Thus, we develop a PIM-RNS, entitled PRIMS, and analyze the potential of intertwining PIM architecture with the inherent parallelism of the RNS arithmetic to delineate the opportunities and challenges. To this end, we build a comprehensive device-to-architecture evaluation framework to quantitatively study this problem considering the impact of PIM technology for a well-known three-moduli set as a case study.

Residue-Net: Multiplication-free Neural Network by In-situ No-loss Migration to Residue Number Systems

Abstract: Deep neural networks are widely deployed on embedded devices to solve a wide range of problems from edge-sensing to autonomous driving The accuracy of these networks is usually proportional to their complexity Quantization of model parameters (ie, weights) and/or activations to alleviate the complexity of these networks while preserving accuracy is a popular powerful technique Nonetheless, previous studies have shown that quantization level is limited as the accuracy of the network decreases afterward We propose Residue-Net, a multiplication-free accelerator for neural networks that uses Residue Number System (RNS) to achieve substantial energy reduction RNS breaks down the operations to several smaller operations that are simpler to implement Moreover, Residue-Net replaces the copious of costly multiplications with non-complex, energy-efficient shift and add operations to further simplify the computational complexity of neural networks To evaluate the efficiency of our proposed accelerator, we compared the performance of Residue-Net with a baseline FPGA implementation of four widely-used networks, viz, LeNet, AlexNet, VGG16, and ResNet-50 When delivering the same performance as the baseline, Residue-Net reduces the area and power (hence energy) respectively by 36% and 23%, on average with no accuracy loss Leveraging the saved area to accelerate the quantized RNS network through parallelism, Residue-Net improves its throughput by 28x and energy by 27x

FPGA Implementation of high speed-low energy RNS based Reconfigurable-FIR Filter for Cognitive Radio Applications

Abstract: The Finite impulse response (FIR) filter is prominently employed in many digital signal processing (DSP) systems for various applications. In this paper, we present a high-performance RNS based FIR filter design for filtration in SDR applications. In general, the residue number system (RNS) gives significant metrics over FIR implementation with its inherent parallelism and data partitioning mechanism. But with increased bit width cause considerable performance trade-off due to both residue computation and reverse conversion. In this paper optimized Residue Number System (RNS) arithmetic is proposed which includes distributed arithmetic based residue computation during RNS multiplication followed by speculative delay optimized reverse computation to mitigate the FIR filter trade-off characteristics with filter length. The proposed RNS design utilizes built-in RAMs block present in the devices of FPGA to accomplish the process of reverse conversion and to store pre-computational values. A distinctive feature of the proposed FIR filter implementation with core optimized RNS is to minimize hardware complexity overhead with the improved operating speed. Initially, fetal audio signal detection is carried out to validate the functionality of FIR filter core and FPGA hardware synthesis is carried out for various input word size and FIR length. From the experimental, it is proved that the trade-off exists in conventional RNS FIR over filter length is narrow down along with considerable complexity reduction with our proposed optimized RNS system.

Generating Residue Number System Bases

Abstract: Residue number systems provide efficient techniques for speeding up calculations and/or protecting against side channel attacks when used in the context of cryptographic engineering. One of the interests of such systems is their scalability, as the existence of large bases for some specialized systems is often an open question. In this paper, we present highly optimized methods for generating large bases for residue number systems and, in some cases, the largest possible bases. We show their efficiency by demonstrating their improvement over the state-of-the-art bases reported in the literature. This work make it possible to address the problem of the scalability issue of finding new bases for a specific system that arises whenever a parameter changes, and possibly open new application avenues.

Efficient Incorporation of the RNS Datapath in Reverse Converter

Abstract: The class of moduli sets in the form of $\{2^{k}, 2^{n}-1, 2^{n}+1, m_{4}\}$ with $m_{4}\in \{2^{r}+1, 2^{r}-1\}$ has earned significant popularity in the implementation of the Residue Number System (RNS)-based computational systems, mainly thanks to the efficient arithmetic unit and a high degree of parallelism. However, its complicated inter-modulo computation leads to a high overhead associated with the complex reverse converter. This overhead is the main barrier for energy-efficient implementation of RNS-based devices, particularly for edge computing applications. This brief presents a new approach that embeds the reverse converter into the arithmetic unit of the RNS processor for the aforesaid well-known class of moduli sets. The effective hardware reuse in the proposed approach leads to an area and energy-efficient RNS realization for this class of moduli set. The experimental results based on 65 nm CMOS technology indicate the superiority of RNS realization by employing the proposed design methodology. The proposed architecture for a given RNS provides a substantial 17.4% area-saving and 13.32% less power-consumption on average compared to the traditional design approach, with the negligible penalty in delay.

AN-Coded Redundant Residue Number System for Reliable Neural Networks

Abstract: Residue Number Systems (RNS) can simultaneously improve computing acceleration, area reduction and power saving. For high-reliability applications like automotive electronics, partition-ability empowers the redundant RNS fault tolerance. However the parallel multiple modular redundancy will take a huge number of converters. This is the first paper to incorporate AN codes to the RRNS applied in high-reliable neural networks. From experimental results, the k-modulus redundancy can be reduced from 2 paths to only one, and the residue-to-binary converters can be saved from (k+2)(k+1) to only k+1 for the external-coding structure, and even to only one for the internal-coding structure in the single residue arithmetic-weight error correcting. From BLER simulations, about 130 times of reliability can be achieved for a 16-bit 47N-coded MAC.

Towards Optimizing Cloud Computing Using Residue Number System

Abstract: In the work methods for building systems of distributed data storage based on the system of residual classes are considered. The use of direct conversion of data from the positional system of calculation to the residue number system will have a large computational complexity, the use of modules of a particular type allows you to solve this problem. The operation of scaling and expansion of the base system, which is necessary to restore the number of stored parts in case of failure of one or more cloud servers, is considered.

High Performance Deterministic Stochastic Computing Using Residue Number System

Abstract: Stochastic Computing (SC) is a re-emerging computing paradigm with a great potential to surpass conventional binary implementations in term of hardware cost. The inaccuracy of computations is an important challenge with conventional SC designs. Recently, some deterministic approaches to SC were proposed. These methods are able to produce completely accurate results. However, they take a long processing time to produce exact results which directly translates to very high energy consumption. This work proposes a design methodology based on the Residue Number System (RNS) to mitigate the long processing time of the deterministic methods of SC. Leveraging RNS, the length of bit-streams decreases exponentially as high bit-width operands are replaced with low bit-width residues. Compared to the state-of-the-art deterministic methods, the proposed approach delivers more than 2400× and 3200× reduction in processing time and energy consumption, respectively, for 8-bit multiplication operation. Synthesis results further show that for a processing element (PE) in DNN accelerators, the proposed design occupies 84%, 52% and 30% less area compared to the conventional binary, RNS, and deterministic designs of SC, respectively.

High Precision Multiplier for RNS {2n−1,2n,2n+1}

Abstract: The Residue Number System (RNS) is a non-weighted number system. Benefiting from its inherent parallelism, RNS has been widely studied and used in Digital Signal Processing (DSP) systems and cryptography. However, since the dynamic range in RNS has been fixed by its moduli set, it is hard to solve the overflow problem, which can be easily solved in Two’s Complement System (TCS) by expanding the bit-width of it. For the multiplication in RNS, the traditional way to deal with overflow is to scale down the inputs so that the result can fall in its dynamic range. However, it leads to a loss of precision. In this paper, we propose a high-precision RNS multiplier for three-moduli set 2n−1,2n,2n+1, which is the most used moduli set. The proposed multiplier effectively improves the calculation precision by adding several compensatory items to the result. The compensatory items can be obtained directly from preceding scalers with little extra effort. To the best of our knowledge, we are the first one to propose a high-precision RNS multiplier for the moduli set 2n−1,2n,2n+1. Simulation results show that the proposed RNS multiplier can get almost the same calculation precision as the TCS multiplier with respect to Mean Square Error (MSE) and Signal-to-Noise Ratio(SNR), which outperforms the basic scaling RNS multiplier about 2.6–3 times with respect to SNR.

Enhanced image security using residue number system and new Arnold transform

Abstract: This paper aims to improve the image scrambling and encryption effect in traditional two-dimensional discrete Arnold transform by introducing a new Residue number system (RNS) with three moduli and the New Arnold Transform. The study focuses on improving the classical discrete Arnold transform with quasi-affine properties, applying image scrambling and encryption research. The design of the method is explicit to three moduli set {2n, 2n+1+1, 2n+1-1}. These moduli set includes equalized and shapely moduli leading to the effective execution of the residue to binary converter. The study employs two methods: Arithmetic residue to the binary converter and an improved Arnold transformation algorithm. The encryption process uses MATLAB to accept a digital image input and subsequently convert the image into an RNS representation. The images are connected as a group. The resulting encrypted image uses the Arnold transformation algorithm. The encrypted image is used as input at decryption using the anti-Arnold (Reverse Arnold) transformation algorithm to convert the picture to the original RNS (original pixel value). Then the RNS was used to retransform the original RNS to its binary form. The study performed security analysis tests to test the strength of the proposed hybrid scheme. Security tests like histogram analysis, keyspace, key sensitivity, and correlation coefficient analysis were administered on the encrypted image. Results show that the hybrid system has used the improved Arnold transform algorithm with better security and no constraint as to image width and size.

A new sign detection design for the residue number system based on quantum-dot cellular automata

Abstract: Sign detection has a wide application in digital fixed-point signal processing; however, it seems hard to conduct it in residue number systems (RNSs) based on complementary metal oxide semiconductor (CMOS). Also, quantum-dot cellular automata (QCA), as a useful substitution for CMOS technologies, provide many benefits such as low energy utilization and high velocity. However, up to now, there is not any paper that investigated the design of the QCA-based sign detection system. Therefore, here, we will introduce a method for RNS sign detection in the three-moduli set {2n+1 − 1, 2n − 1, 2n}. In the suggested design, we offer a new QCA-based design in one layer for sign detection of three-moduli set {2n+1 − 1, 2n − 1, 2n}. It is not only used for arithmetic units of RNS but also applied for cost and performance improvement of the total system. We simulate and analyze the proposed detection method using the QCADesigner simulator. We also compare the cell count, delay, and occupied area. Experimental results showed that the proposed architecture requires 5.60 µm2 of the circuit area, and the delay is decreased.

Modelling of Parallel Unsigned 2n-1 Modular Arithmetic Multiplier for RNS

Abstract: Modular Multiplication operations are widely used in Digital crypto processors. Modulo multipliers is an essential block for Residue Number System (RNS) computation. Pointing to increase the performance of the RNS computation, the parallel unsigned modulo multiplier for 2n-1 moduli is designed. A mathematical modelling, VLSI architecture and real-time verification are done in this work. Further, the modulo multipliers are described usingVerilog HDL, and the synthesize results for both FPGA and ASIC technologies are presented. Comparison is made based on the parameters such as Area, Power, Delay, PDP& ADP using Cadence RTL Compiler with 180 nm, 90 nm and 45 nm TSMC CMOS Technologies.From the analysis indicate that the proposed multiplier provides a 16% area reduction and 40% speed improvement with a better PDP and ADP performance compared tothe existing modulo multipliers. Finally, the usefulness of 2n-1 modulo multiplier in RNS environment is discussed.

The Study of Monotonic Core Functions and Their Use to Build RNS Number Comparators

Abstract: A non-positional residue number system (RNS) enjoys particularly efficient implementation of addition and multiplication, but non-modular arithmetic operations in RNS-like number comparison are known to be difficult. In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on using the core function for which it was shown that it must be monotonic to allow for RNS number comparison. The conditions of the monotonicity of the core function were formulated, which also ensured the minimal range of the core function (essential to obtain the best characteristics of the comparator). The best choice is a core function in which only one coefficient corresponding to the largest modulus is set to 1 whereas all other coefficients are set to 0. It is also shown that the already known diagonal function is nothing else but the special case of the core function with all coefficients set to 1. Performance evaluation suggests that the new comparator uses less hardware and in some cases also introduces smaller delay than its counterparts based on diagonal function. The potential applications of the new comparator include some recently developed homomorphic encryption algorithms implemented using RNS.

Computationally Efficient Approach to Implementation of the Chinese Remainder Theorem Algorithm in Minimally Redundant Residue Number System

Abstract: In this paper, we deal with the critical problem of performing non-modular operations in the Residue Number System (RNS). The Chinese Remainder Theorem (CRT) is widely used in many modern computer applications. Throughout the article, an efficient approach for implementing the CRT algorithm is described. The structure of the rank of an RNS number, a principal positional characteristic of the residue code, is investigated. It is shown that the rank of a number can be represented by a sum of an inexact rank and a two-valued correction to it. We propose a new variant of minimally redundant RNS, which provides low computational complexity for the rank calculation, and its effectiveness analyzed concerning conventional non-redundant RNS. Owing to the extension of the residue code, by adding the excess residue modulo 2, the complexity of the rank calculation goes down from $O\left (k^{2}\right )$ to $O\left (k\right )$ with respect to required modular addition operations and lookup tables, where k equals the number of non-redundant RNS moduli.

Evaluation of Mixed-Radix Digit Computation Techniques for the Three Moduli RNS {2 n −1, 2 n , 2 n +1 −1}

Abstract: In this brief, we evaluate two techniques for obtaining mixed-radix digits using mixed-radix conversion technique, for the residue number system (RNS) moduli set $\{2^{n}-1, 2^{n}, 2^{n+1}-1\}$ . These are needed for comparison of two numbers in residue form, base extension to modulus $2^{n+e}$ and reverse conversion. The complete architectures are derived to estimate the hardware resource requirement and computation time for deriving the mixed-radix digits. The proposed techniques are also compared with designs based on other techniques available in literature. The trade-offs regarding hardware resource requirement, computation time and power dissipation are brought out.

Generation of Hardware Modules for Comparison in Residue Numeral Systems

Abstract: The residue numeral system (RNS) is one of the alternative number representation systems which has a strong potential for using it in computing systems. One of the known problems of the RNS is the complexity of the implementation of some basic arithmetic operations, including comparison and division operations. The paper considers the problem of implementing the comparator for the residue number system with one of the popular moduli set {2n-1, 2n, 2n+1}. Description of two existing methods and its properties are provided. After that, an experimental evaluation of the described methods using modern EDA tools and analysis of results are presented.

Design of Efficient Reverse Converters for Residue Number System

Abstract: The main factors that affect the performance of residue number system (RNS) are speed and hardware complexity of the residue-to-binary converter. In this paper, two efficient reverse converters are...

Modular Adder Designs Based On Thermometer Coding And One-Hot Coding

Abstract: Modular adders are used in various applications of computer systems. Modular addition is commonly used in residue number system processors. It is used mainly in the residue arithmetic unit and also in both the forward and reverse converters. Residue number system is highly efficient when compared with positional number system, because it provides high speed computation as well as less area requirement. In order to improve the computation speed, efficient modular adders are required. Modular adders based on thermometer code residue and one hot code residue are used for this purpose. This results in less latency and area. This approach reduces the area and delay of modular adders since there is no carry bit propagation during modular addition operation. It also simplifies the structure of modular adders compared to conventional binary based modular adders. All the proposed modular adders are described in verilog HDL and verified using Xilinx ISE.

Design of Reconfigurable Signed Dual Modulo Multiplier Function (DMMF) for RNS

Abstract: Residue Number System (RNS) is an alternative number representation of a Binary weighted system to process the data at a higher rate with lower hardware. Modular Multiplication operations are extensively utilized in RNS Processors. To increase the processor's performance, a new configurable signed dual modulo $2^{\mathrm{n}}\pm 1$ multiplication that uses array architecture is proposed in this work. The multiplier could be used to perform successive modulo multiplications on the same hardware. Mathematical modelling, VLSI architecture and real-time verification are done in this work. Proposed DMMF saves the area by 40%, reduces the power consumption by 37%, and increases the operation speed by 33% compared to the architecture operated separately.

A New High-Speed, Low-Area Residue-to-Binary Converter For the Moduli Set $$\{ 2^{4n} ,2^{2n} + 1,2^{n} + 1,2^{n} - 1\}$$ Based on CRT-1

Abstract: The implementation of reverse converter is one of the most important elements influencing the performance of a residue number system. In this research, we propose an efficient high-speed and low-area reverse converter for moduli set $$\{ 2^{4n} ,2^{2n} + 1,2^{n} + 1,2^{n} - 1\}$$ . Due to the form of the moduli set, we have implemented the proposed reverse converter using Chinese remainder theorem and dynamic range division technique, which have resulted in a simpler design, lower area consumption and higher conversion speed compared to previous studies. To have a fair comparison between the proposed reverse converter and the recently presented converters with similar moduli sets, we used Xilinx ISE 13.1 FPGA simulator to derive area and delay, which are measured to cover the various dynamic ranges up to 256 bit. The experimental results show that the proposed reverse converter achieves an average 20% area time saving compared to the recently presented converters for similar moduli set.

Data Hiding in Digital Image for Efficient Information Safety Based on Residue Number System

Abstract: The mass dispersal of digital communication requires the special measures of safety. The need for safe communication is greater than ever before, with computer networks now managing almost all of our business and personal affairs. Information security has become a major concern in our digital lives. The creation of new transmission technologies forces a specific protection mechanisms strategy particularly in data communication state. We proposed a steganography method in this paper, which reads the message, converting it into its Residue Number System equivalent using the Chinese Remainder Theorem (CRT), encrypting it using the Rivest Shamir Adleman (RSA) algorithm before embedding it in a digital image using the Least Significant Bit algorithm of steganography and then transmitting it through to the appropriate destination and from which the information required to reconstruct the original message is extracted. These techniques will enhance the ability to hide data and the hiding of ciphers in steganographic image and the implementation of CRT will make the device more efficient and stronger. It reduces complexity problems and improved execution speed and reduced the time taken for processing the encryption and embedding competencies. Original Research Article Eseyin and Gbolagade; AJRCOS, 8(4): 35-44, 2021; Article no.AJRCOS.68473 36

Accelerating Smith Waterman Algorithm for Optimizing Gene Sequences Alignment Using Parallel Residue Number System Arithmetic Based Architecture

Abstract: The understanding of evolutionary relationships among biological entities enabled computer scientist’s researchers to developing various arithmetic number bases systems with remarkable genetic sequence alignment technique, where weaker analyses in homologous sequence are acceleratory detected and implemented. Using SWA for continuous improvement in the sensitivity of genes and proteins regulatory sequence alignment, three moduli sets are presented for DNA sequence alignment with residue of each modulus independently of each other, concurrently by parallel ALUs without carry propagation among them. Finally, we developed a reconfigurable RNS-SWA based arithmetic architecture with design support tool characterized in addition (ADD), subtraction (SUB), multiplication (MUX) using RNS conversion technique properties on a multi ALU system which provide structural VHDL simulation descriptions summary for the RNS-SWA Based DNA sequences; improving low Power, high speed linear processing acceleration required in genetic sequences computing. Our proposed design work when implemented in PLD-RNS-SWA based high profile acceleration comparator, exhibits a greater significant percentage speed when compare with the non RNS state of art profiler in real time processing design supporting a very high speed integrated Circuits.