Showing papers on "Snapback published in 1992"
Patent•
17 Dec 1992TL;DR: In this paper, an ESD protection circuit and a structure for integrated circuit devices uses a lateral NPN transistor to provide a low resistance discharge path for ESD transient voltages.
Abstract: An ESD protection circuit and structure for integrated circuit devices uses a lateral NPN transistor to provide a low resistance discharge path for ESD transient voltages. A preferred structure also includes a modification to an N-channel output drive transistor to eliminate the parasitic bipolar transistor that induces snapback.
52 citations
06 Oct 1992
20 citations
TL;DR: In this paper, an analytical model was developed for predicting the observed output characteristics taking into account both the bipolar and the MOS mechanisms, and it was shown that, with continuing scaling of device geometries and improvement in SOI materials, the bipolar-induced snapback will become dominant in the future.
Abstract: The snapback effect is usually observed in the output characteristics of an n-channel SOI MOSFET with zero gate voltage in which the drain-to-source breakdown voltage is less than the drain-to-body avalanche voltage. It can be attributed to parasitic lateral bipolar actions as well as the MOS feedback mode of operation-a point often overlooked in the literature. An analytical model is developed for predicting the observed output characteristics taking into account both the bipolar and the MOS mechanisms. Results obtained from this model agree well with the experimental I-V curves, and show that, with continuing scaling of device geometries and improvement in SOI materials, the bipolar-induced snapback will become dominant in the future. >
18 citations
TL;DR: In this paper, a non-local model of impact ionisation was used to model bipolar snapback in thin film SOI transistors. Butts et al. used a two-dimensional device simulator to obtain accurate prediction of bipolar holding voltage with submicron gate lengths.
Abstract: To model bipolar snapback in thin film SOI transistors accurately, it is necessary to employ a non-local model of impact ionisation. Such a model, based on the “Lucky electron” theory, has been incorporated in a two-dimensional device simulator. Accurate prediction of bipolar holding voltage has been obtained for SOI transistors with sub-micron gate lengths. The model has been applied to analyse separately the effects of both lightly doped source and lightly doped drain in maximising the holding voltage. The advantage of using ultra thin highly doped SOI films in conjunction with a lightly doped drain is discussed.
7 citations
CNET1
TL;DR: In this article, the authors analyzed the phenomenon of snapback in MOSFETs and showed that the expansion of the base of the parasitic bipolar transistor with drain bias provides the necessary basis for the understanding of the snapback mechanism.
Abstract: The paper analyzes the phenomenon of snapback (negative resistance region of the output characteristic) in MOSFETs. It shows that the expansion of the base of the parasitic bipolar transistor with drain bias provides the necessary basis for the understanding of the snapback mechanism. The R sub bottoming-out, resulting from the expansion, and the association of this phenomenon with the triggering of snapback is shown to be here a key point. This result may have some important practical implications since it not only provides simple criteria for the snapback triggering and sustaining (lacking to date) but also hints on how to shift the snapback towards higher drain bias.
6 citations
TL;DR: In this paper, the authors used a simplified model to determine the width dependence of the MOSFET substrate resistance and found that the normalized substrate current required for source turn-on predicted by this model is increased by an order of magnitude for wide-channel width transistors in agreement with measured data.
Abstract: Wide-channel MOSFETs have typically 10 to 30% lower breakdown voltages than narrow-width (W approximately=L) transistors and are less likely to exhibit clear snapback characteristics. These observations can be explained using a simplified model to determine the width dependence of the MOSFET substrate resistance. The normalized substrate current I/sub sub//W required for source turn-on predicted by this model is found to decrease by an order of magnitude for wide-channel-width transistors in agreement with measured data. This results in the observed decrease in breakdown voltage for wide-channel MOSFETs. >
6 citations
01 Mar 1992
TL;DR: In this article, a photon-counting imaging method has been employed to acquire the extremely weak pulse electroluminescence from a thick-field-oxide electrostatic discharge (ESD) protection device during very short pulse stressing.
Abstract: A photon-counting imaging method has been effectively employed to acquire the extremely weak pulse electroluminescence from a thick-field-oxide electrostatic discharge (ESD) protection device during very short pulse stressing. From this, its dynamic spatial conduction patterns with respect to different currents, pulse widths, and repetition rates could then be directly visualized and assessed. The authors have applied such an imaging method successfully in the acquisition of a full series of spatial pulsed emission patterns on circuitry during ESD simulation. This could offer a means for direct, simultaneous observation of emerging failure on such a device. The exact sequential turning-on nature of bipolar NPN snapback, on each ladder-channel and its non-uniformity in spread during different levels and widths of pulsation could also be resolved directly. The authors report on the accurate determination of the site of the resistive short on failed samples by this technique. >
1 citations