Showing papers on "Spice published in 1987"
TL;DR: In this article, a GaAs FET model suitable for SPICE circuit simulations is developed, where the dc equations are accurate to about 1 percent of the maximum drain current, and a simple interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square root law for larger values of the drain current.
Abstract: We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.
520 citations
TL;DR: In this article, an analysis of metastable operation in CMOS RS flip-flops is presented using Shichman-Hodges model for NMOS and PMOS transistors.
Abstract: An analysis of metastable operation in CMOS RS flip-flops is presented. An analytical formula for the flip-flop resolving time constant was derived using Shichman-Hodges model for NMOS and PMOS transistors. This formula, as related to the transistor dimensions, fabrication process parameters, and parasitic capacitance, uses proper transistor sizing to attain minimum flip-flop failure rate due to metastable operation. CMOS n-well, p-well, and twin-well flip-flop performance predicted analytically is also approved by SPICE level one simulation of transistor models. Real-time oscilloscope displays of metastable operation for two different CMOS RS flip-flop circuits are demonstrated.
66 citations
Book•
01 Jan 1987
TL;DR: This book has three key objectives: to describe device models for diodes, bipolar junction transistors and field-effect transistors; to apply these device models in a wide variety of realistic examples; and to integrate the use of SPICE throughout as a powerful design tool for circuit analysis.
Abstract: The basic concepts of electronics and circuit analysis are introduced in this work. Among the selection of realistic examples offered by the book is SPICE, a circuit simulation software program used widely in EE departments. In simple terms, SPICE is used as an analysis tool to test electronic devices and their performance in circuits. The book has three key objectives: to describe device models for diodes, bipolar junction transistors and field-effect transistors; to apply these device models in a wide variety of realistic examples; and to integrate the use of SPICE throughout as a powerful design tool for circuit analysis.
42 citations
TL;DR: Quantitative estimates of expected SER improvements are presented after various parameters in the cell model were changed in order to investigate the effects on the alpha-particle sensitivity, and the results suggest a mechanism by which the mechanism could most economically be improved.
Abstract: Alpha-particle-induced soft error rates (SERs) in RAMs were measured by exposing commercial chips, with lid and protective coating removed, to an Americium-241 alpha source. These measurements have shown that, under normal operating conditions, resistive load SRAMs can be as sensitive as DRAMs. Measurements of variations of SER with cycle time and supply voltage were in broad agreement with a model previously suggested by other workers, and explanations are proposed for the different regions of operation. The effect of an alpha-particle hit on SRAM cell is simulated using SPICE with typical process parameters. A simple analysis of the model highlights the features that determine the critical charge. The behavior predicted by this model is different in a small but significant way from that predicted by previous workers: it was confirmed by SPICE simulation. Various parameters in the cell model were changed in order to investigate the effects on the alpha-particle sensitivity, and the results of these simulations suggest a mechanism by which the sensitivity could most economically be improved. By combining the result of the simulations and experiments, quantitative estimates of expected SER improvements are presented.
42 citations
TL;DR: In this paper, a semi-empirical model for the threshold voltage of a small geometry double implanted enhancement type MOSFET, especially useful in a circuit simulation program like SPICE, has been developed.
Abstract: A simple and accurate semi-empirical model for the threshold voltage of a small geometry double implanted enhancement type MOSFET, especially useful in a circuit simulation program like SPICE, has been developed. The effect of short channel length and narrow width on the threshold voltage has been taken into account through a geometrical approximation, which involves parameters whose values can be determined from the curve fitting experimental data. A model for the temperature dependence of the threshold voltage for the implanted devices has also been presented. The temperature coefficient of the threshold voltage was found to change with decreasing channel length and width. Experimental results from various device sizes, both short and narrow, show very good agreement with the model. The model has been implemented in SPICE as a part of the complete d.c. model.
39 citations
TL;DR: DEL is determined using an extraction algorithm which systematically extracts MOS3 parameters and characterizes the extent of mobility degradation in the transistor's triode region, thereby permitting SPICE users to accurately simulate both triode and saturation regions of p- and n-channel transistors.
Abstract: Unrealistic parameter values and poor experimental agreement are two problems often encountered using the MOS3 model in SPICE2. The source of the discrepancy is attributed to MOS3's simplified treatment of the mobility degradation phenomenon, which generally results in an artifically exaggerated value for the carrier velocity. Practically, this discrepancy can be eliminated by introducing a new empirical factor (DEL) into the mobility model, thereby permitting SPICE users to accurately simulate both triode and saturation regions of p- and n-channel transistors. DEL is determined using an extraction algorithm which systematically extracts MOS3 parameters and characterizes the extent of mobility degradation in the transistor's triode region.
20 citations
TL;DR: In this article, the capacitance model proposed in the above paper is implemented in a circuit simulation program and some of the difficulties associated with this implementation are addressed and illustrated with the help of a circuit example.
Abstract: The capacitance model proposed in the above paper [1] is implemented in a circuit simulation program. Some of the difficulties associated with this implementation are addressed and illustrated with the help of a circuit example.
19 citations
02 Mar 1987
TL;DR: In this article, a small-signal equivalent circuit which models the frequency-domain behavior of magneticamplifier-controlled switched-mode converters operating in the continuous-mmf mode is presented.
Abstract: A small-signal equivalent circuit which models the frequency-domain behavior of magneticamplifier- controlled switched-mode converters operating in the continuous-mmf mode is presented. The equivalent circuit, which is based upon stateaveraging techniques, can be used with a circuitanalysis program such as SPICE to evaluate the frequency-domain behavior of a magneticamplifier- controlled converter prior to circuit implementation. Two high-frequency switched-mode converters which employ magnetic amplifiers as output-voltage regulators are discussed. To show the validity of the derived equivalent circuit, measurement results of the small-signal frequencydomain behavior of the two switched-mode converters are compared with results produced by simulations employing the equivalent circuit.
16 citations
Patent•
02 Sep 1987
TL;DR: In this article, the authors present a closed-closable spice dispenser with an articulately connected closure lid for each chamber, where the spice when the spice chamber is open can be introduced into the latter and when the closure lid is closed can be dispensed through at least one sprinkling opening, to obtain economical production and simple handling.
Abstract: In a spice dispenser arrangement comprising a housing having at least one closable spice chamber and an articulately connected closure lid for each spice chamber wherein the spice when the spice chamber is open can be introduced into the latter and when the closure lid is open can be dispensed through at least one sprinkling opening, to obtain economical production and simple handling each spice chamber comprises a closure lid integrally formed thereon. The closure lid permits in a preferred embodiment arresting in various open positions and thus dispensing spices in differently proportioned amounts.
15 citations
01 Jan 1987
TL;DR: In this article, a substrate current model and a quasi-static hot-electron-induced MOSFET degradation model have been implemented in the Substrate Current and Lifetime Evaluator (SCALE).
Abstract: A substrate current model and a quasi-static hot-electron-induced MOSFET degradation model have been implemented in the Substrate Current and Lifetime Evaluator (SCALE). It is shown that quasi-static simulation is valid for a class of waveforms including those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and post- processors fashion to form an independent simulator. The pre-processor interprets the input deck, and requests SPICE to output the transient node voltages of the user-selected devices. The post-processor then calculates the transient substrate current and makes lifetime prediction.
15 citations
01 Dec 1987
TL;DR: An analytic non-quasistatic (NQS) MOSFET model has been derived and implemented in SPICE as discussed by the authors, which is based on an approximate solution to the non-linear transient current continuity equation in the channel.
Abstract: An analytic non-quasistatic(NQS) MOSFET model has been derived and implemented in SPICE It is based on an approximate solution to the non-linear transient current continuity equation in the channel The model includes the large signal transient and the small signal frequency response analyses Comparisons have been made between this model and the 1-D numerical solution to the current continuity equation, 2-D device simulation(PISCES) and the quasistatic(QS) results The channel charge partitioning scheme in the charge based model is shown to be inadequate for the fast transient and the high frequency AC analysis This model does not use a charge partitioning scheme and the currents are dependent on the history of the terminal voltages, not just the instantaneous voltages and their derivatives
TL;DR: In this paper, a subcircuit has been implemented in the SPICE network simulation program for simulating laser diode modules, in addition to the properties of the laser chip and electrical package parasitics, incoherent optical reflections from the end of the fiber pigtail are included.
Abstract: For simulating laser diode modules, a subcircuit has been implemented in the SPICE network simulation program. In addition to the properties of the laser chip and electrical package parasitics, incoherent optical reflections from the end of the fibre pigtail are included. Numerical results are compared to measurements on DFB and FP lasers.
02 Mar 1987
TL;DR: The SPICE PLUS simulation program as discussed by the authors offers circuit designers full capability for simulating magnetic cores used in power supplies and in other power design circuits, and it can be used to simulate magnetic cores with gaps.
Abstract: The SPICE PLUS simulation program offers circuit designers full capability for simulating magnetic cores used in power supplies and in other power design circuits. This paper is an overview of the model, its capabilities, and application. The magnetic model defines both major and minor hysteresis loops, which are derived from the dynamic relationship between magnetic flux density and magnetic field strength in cores. A model for cores with gaps has been implemented and its effects on the magnetization curves is explained. Finally an example of accurate simulation is given that shows the importance of modeling the core's nonlinear effects.
TL;DR: A method to predict the small-signal linear gain and level of harmonic distortion in analog MOS circuits is presented and can be easily extended to include capacitive effects and a prediction of intermodulation distortion.
Abstract: A method to predict the small-signal linear gain and level of harmonic distortion in analog MOS circuits is presented. This method, based on a generalized nonlinear transfer function approach, lends itself to implementation in the AC small-signal analysis routine of the circuit simulation program SPICE. A low-frequency nonlinear distortion model based on the CSIM simulator MOSFET model is applied to three simple MOSFET circuits. Results presented emphasize the need to consider small-signal quantities in the development of MOSFET models and in the determination of device parameters. The method can be easily extended to include capacitive effects and a prediction of intermodulation distortion.
19 Oct 1987
TL;DR: A computer-aided design of a high-performance driving circuit for floating power Mosfet switch with very fast switching and large duty cycle ratios is presented.
Abstract: A computer-aided design of a high-performance driving circuit for floating power Mosfet switch is presented. Very fast switching and large duty cycle ratios are achieved. Design methodology and optimization procedures using computer circuit simulator SPICE 2 are given.
TL;DR: In this article, a physically based MESFET model for device modeling and circuit simulation has been developed, which takes into account velocity saturation as well as the impurity profile as integral parts of the dc and ac models.
Abstract: A physically based MESFET model for device modeling and circuit simulation has been developed. The model directly couples the dc and ac models and takes into account velocity saturation as well as the impurity profile as integral parts of the dc and ac models. The model, verified for implanted self-aligned MESFET's, has been implemented in SPICE and used to simulate circuits.
01 Oct 1987
TL;DR: An improved GaAs-MESFET, curvefitting model has been developed and implemented into the source code of SPICE 2G6 as mentioned in this paper, which is suitable for simulation of high speed analog and digital GaAs integrated circuits.
Abstract: An improved GaAs-MESFET, curve-fitting model has been developed and implemented into the source code of SPICE 2G6 The advantages of our model compared to the well known Curtice model are shown We describe our sequential procedure to find the fit functions and to extract the model parameters The model presented here is suitable for simulation of high speed analog and digital GaAs integrated circuits
14 Jun 1987
TL;DR: In this article, a buck-type converter is modeled for continuos conduction mode, simulated, analysed and measured with emphasis on loop gain to be able to design for stability, and a new SPICE2 model for current-mode programming plus a useful formula for control voltage to output voltage transfer function has been derived.
Abstract: A buck-type converter is modeled for continuos conduction mode, simulated, analysed and measured with emphasis on loop gain to be able to design for stability. As a result of this "Structured Analog Design" process, a new SPICE2 model for current-mode programming plus a useful formula for control voltage to output voltage transfer function has been derived. The theoretical background is based on Dr. R. D. Middlebrooks papers on the subject, (2,3). In a case study, both prediction and measurement show a second pole, in loop gain, at a surprisingly low frequency. This implies that the current-mode control, although it seems to be the best method for regulation, must be properly understood for avoiding oscillating units.
Proceedings Article•
01 Sep 1987
TL;DR: In this paper, a high-resolution direct on-wafer off-chip C-V capacimeter is described, which allows for the validation of the SPICE intrinsic gate capacitance model by the observation of the differences in capacitances when the geometries are reduced or when the transistors are not conventionnal (LOD, DOD...).
Abstract: The difficulties of making accurate measurements of intrinsic capacitances on small geometries MOSFETs renders the modelization of these components unreli'able. Recently an onchip technique has been developped for these measurements (1). This method, however, is not versatile because it need special on-chip circuitry. This paper describes a high resolution direct on-wafer off-chip C-V capacimeter. This apparatus allows for the validation of the SPICE intrinsic gate capacitance model by the observation of the differences in capacitances when the geometries are reduced or when the transistors are not conventionnal (ieLOD, DOD...). It also permits the measurement of the effect of charges variation in the oxide or at the SI02 interface on the Cgd and Cgs capacitance after hot carrier aging. In this presentation, measurements have been carried out on long and short transistors in order to test the validity of SPICE. Measurements have also been carried out before and after hot carrier stressing, and it will be shown that the capacitance characteristics are strongly affected by this stressing. The detailed signal path is shown in figure (A). The measurement system is composed of an L.I.A and three bias sources under the control of an Apple IIE microcomputer. An I-V converter transforms the ac current signal into an amplified ac voltage. The frequency of the input signal is 10 KHZ and the amplitude is 10 mv rms. The resolution of the system is in the atto farad (1E-18 farad) range. The accuracy is less than four percent for the range 5 femtoFarad (5E-15 Farad).
TL;DR: Two-region saturation at high injection levels and at low frequencies may be conveniently approximated using a graphical model which introduces the concept of quasi-saturation resistance R/SUB QS.
Abstract: Two-region saturation at high injection levels and at low frequencies may be conveniently approximated using a graphical model which introduces the concept of quasi-saturation resistance R/SUB QS/. It is shown how this graphical model may be implemented in the modeling program SPICE with the aid of a distributed equivalent circuit.
Proceedings Article•
01 Jan 1987TL;DR: It is shown l that accurate SPICE parameters can be extracted from process control chips with on-chip switching and made via the switching transistors.
Abstract: This paper investigates the feasibility of using on-chip switching for the instrumentation used to measure transistor characteristics. The effect of the switching transistors on the measurements are evaluated by comparing the SPICE parameters extracted from measurements made via the switching transistors with those derived directly. It is shown lthat accurate SPICE parameters can be extracted from process control chips with on-chip switching.
TL;DR: In this article, the operation of dual-gate GaAs MESFET's in gigabit-per-second switching applications for high-speed fiber-optic systems is investigated, and a full nonlinear modeling procedure is presented for general switching simulations.
Abstract: The operation of dual-gate GaAs MESFET's in gigabit-per-second switching applications for high-speed fiber-optic systems is investigated, and a full nonlinear modeling procedure is presented for general switching simulations. The model is characterized via a new and efficient technique which only requires two-port s -parameter measurements to determine the nonlinear element variations. Circuit simulations implemented on program SPICE 2 have been applied to evaluate the transient switching response of dual-gate MESFET's in several circuits involving 1-Gbit/s pulse conversion and synchronization, pulse-width reduction and 2-Gbit/s multiplexing, and results show good agreement between predicted and experimental switching waveforms.
TL;DR: In this article, a CMOS flip-flop cell which can be used in counters is designed, which is used to initialize the count of a flip-Flop cell.
Abstract: A CMOS flip-flop cell which can be used in counters is designed. SPICE model, the transient response and the CMOS layout are presented. When used in counters, the flip-flop can be loaded to initialize the count.
01 Jan 1987
23 Sep 1987
TL;DR: This report presents some novel circuit design techniques used in the datapath of the SPUR floating-point unit which include a fast adder, a leading one detector and a shifter.
Abstract: This report presents some novel circuit design techniques used in the datapath of the SPUR floating-point unit. Three most interesting circuit blocks are discussed which include a fast adder, a leading one detector and a shifter. Mixed logic with static and dynamic circuits are used. The chip is implemented in a 1.6 micron, N-well, double-metal CMOS process (HP CMO5-10). The timing and area of the above three modules are as follows: 66 bit adder *Delay--Crystal 36 ns, SPICE 33 ns *Size--4757x553 Lambda, which is 3806 x 442um 67 bit Leading one detector *Delay--Crystal 20.8 ns, SPICE 18 ns *Size--4901 x 463 lambda, which is 3920 x 320 um 67 bit shifter with Sticky Logic *Delay--Shifting 15 ns, Sticky bit (latched mic output latch) 25 ns *Size--The whole module with decoder is 5359 x 1414 lambda, which is 4287 x 1131 um. c C
TL;DR: In this article, an empirical formula for the currentvoltage characteristics of the metal oxide semiconductor field effect transistor (MOSFET) has been presented and the three parameters of the formula can be calculated easily from separate regions in the device DC characteristics without recourse to special electrical measurements or global curvefitting techniques.
Abstract: An empirical formula is presented for the current-voltage characteristics of the metal oxide semiconductor field effect transistor (MOSFET). The three parameters of the formula can be calculated easily from separate regions in the device DC characteristics without recourse to special electrical measurements or global curve-fitting techniques. By using this formula, the implementation of a new MOSFET model into the source code of Spice is feasible.
TL;DR: In this article, the results of computer simulation of commercial units using an adaptation of SPICE are given and comparison made with practical waveforms with respect to the results obtained using real waveforms.
Abstract: High frequency induction heating power supplies using power MOSFETs are now commercially available. The results of computer simulation of commercial units using an adaptation of SPICE are given and comparison made with practical waveforms.
Proceedings Article•
01 Sep 1987TL;DR: In this paper, an isolated vertical npn transistor fabricated in an n-well CMOS process is described, and an equivalent circuit is presented to model the structure as a 4-terminal device, which can be implemented without modification to the SPICE BJT model.
Abstract: an isolated vertical npn transistor fabricated in an n-well CMOS process is described. Characterisitic features of the transistor are examined, particularly in relation to the absence of a buried layer and low well doping. An equivalent circuit is presented to model the structure as a 4-terminal device, which can be implemented in SPICE without modification to the SPICE BJT model. A parameter extraction sequence for the model is detailed and the results of a parameter optimisation for a real device are presented.