Showing papers on "Static induction transistor published in 1989"

Evaluation of modern power semiconductor devices and future trends of converters

Abstract: A review of the modern power semiconductor devices that appeared in the 1980s, ie, the insulated gate bipolar transistor (IGBT), the static induction transistor (SIT), the static induction thyristor (SITH), and the MOS-controlled thyristor (MCT) is presented The characteristics of these devices are discussed and compared from the viewpoint of power electronics applications Although the IGBT is well known, the power electronics community is somewhat unfamiliar with the latter three devices For completeness, a brief review of other power devices, such as the thyristor, the triac, the gate turnoff thyristor (GTO), the bipolar junction transistor (BJT), and the power MOSFET, is also incorporated Finally, future converter trends are outlined >

CMOS digital level shifter circuit

Abstract: The apparatus of the present invention is a CMOS digital level shifter circuit which includes an inverter connected to a voltage generator. The voltage generator comprises an NMOS source follower connected to a directional switching element and a voltage regulating capacitor. The level shifter further includes a latch energized by the same voltage supply energizing the voltage generator. Each branch of the latch has a complementary MOS transistor pair with common gates connected to the output of the inverter and to the input signal respectively. Each complementary transistor pair is connected to the voltage supply by a latch transistor whose gate is cross-connected to the complementary transistor pair of the other branch. Whenever the one transistor in each complementary pair which is connected to ground is on, the latch transistor is latched off by the complementary transistor pair in the other branch after each voltage transition by the input signal, thereby reducing or eliminating DC power consumption, while requiring only a single voltage supply.

Low-voltage CMOS output buffer

Abstract: A CMOS push-pull output buffer is powered by a low-voltage (e.g., +3.3 V) supply, but is able to withstand elevation of its output node to higher voltage without sinking large currents into the low-voltage supply. Thus, this buffer is able to operate tied to a bus that has various higher-voltage sources also operating on the bus. The P-channel pull-up transistor (11) of this buffer has another P-channel transistor (23) connecting its gate to the output node so that this gate will follow the voltage of the output node and thus keep the pull-up (11) transistor from conducting from the output node to the power supply (V DD3 ). The inverter (15) which drives this gate of the P-channel pull-up transistor (11) is also protected from reverse current into its low-voltage power supply by a series N-channel transistor (12) which will exhibit body effect and is sized to present a significant resistance.

Integrated bipolar-CMOS circuit isolation for providing different backgate and substrate bias

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

The current conveyor: history and progress

Abstract: To create a better voltage-to-current converter, it seemed natural to use another junction, that of a matched pnp transistor connected as a diode, to compensate for the V/sub EB/ of the current-source transistor. However, for this compensation to be effective it was necessary to arrange that the current in the additional pnp transistor track that in the current-source transistor, which was supposed to vary over a number of decades. A five-transistor circuit that provides a nice solution to the problem of creating a precise voltage-to-current converter is proposed. It was incorporated into the circuit for a controlled oscillator with good results. The circuit and its applications are described. >

Shared gate CMOS transistor

Abstract: A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.

MIS type static memory cell and memory and storage process

Abstract: A static memory cell of the metal-insulator-semiconductor type, which can be used in the microelectronics field for producing random access memories for storing binary information. This MIS type memory cell is a random access static memory cell known under the abbreviation SRAM. A bistable flip-flop is formed by a MIS transistor and a parasitic bipolar transistor. The source and drain of the MIS transistor respectively formed by constituting the emitter and collector of the bipolar transistor. The region of the channel of the MIS transistor located between the source and drain serves as the base for the bipolar transistor. The base is completely isolated from the outside of the memory cell. The gate electrode of the MIS transistor is electrically isolated from the region of the channel. There is an addressing circuit for the flip-flop for storing binary information in the form of the absence or presence of current.

Amorphous silicon thin film transistor with a depletion gate

Abstract: The present invention is a high speed thin film transistor with an accumulation gate and a depletion gate. When a positive voltage is applied to the accumulation gate, the electrons are accumulated in the channel region of the accumulation gate and the transistor is operated at the "on" state. If a negative voltage is applied to the depletion gate, the accumulated electrons are depleted, and the transistor is operated at the "off" state. The on-current of the thin film transistor is the same as that of conventional thin film transistors; however, a smaller off-current of the transistor is obtained.

Dual polarity floating gate MOS analog memory device

Abstract: A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.

Floating current source

Abstract: A floating current source comprising two identically sized field effect transistors, one defining a reference transistor and the other defining a floating output transistor. The reference transistor has its gate connected to a reference voltage and its source connected to receive an input current from an input current source and to generate a gate-to-source voltage which when applied as a gate-to-source voltage of the floating output transistor will generate an output current in the output transistor equal to the input current. Circuit means are included for applying between the gate and source of the output transistor a voltage equal to the gate-to-source drain voltage of the reference transistor.

Synapse cell employing dual gate transistor structure

Abstract: A synapse cell for providing a weighted connection between an input voltage line and an output summing line having an associated capacitance. Connection between input and output lines in the associative network is made using a dual-gate transistor. The transistor has a floating gate member for storing electrical charge, a pair of control gates coupled to a pair of input lines, and a drain coupled to an output summing line. The floating gate of the transistor is used for storing a charge which corresponds to the strength or weight of the neural connection. When a binary voltage pulse having a certain duration is applied to either one or both of the control gates of the transistor, a current is generated. This current acts to discharge the capacitance associated with the output summing line. Furthermore, by employing a dual-gate structure, programming disturbance of neighboring devices in the network is practically eliminated.

Simulation of the amorphous silicon static induction transistor

Abstract: The I – V characteristics of the hydrogenated amorphous silicon Static Induction Transistor are obtained by performing a simulation in two dimensions considering electrons and holes together for the first time. The results show that the device has basically four modes of operation that we identify and interpret physically: saturation, channel opening, ohmic and drain current inversion. The study of the influence of the electron concentration at the ohmic contacts, the channel width and the deep level density of states on the switching properties of the device is undertaken. Besides, we show that the on-current is controlled by the electron concentration at the ohmic contacts whereas the off-current is controlled by the electron concentration at the Schottky contact. Finally, we show that the turn-off voltage increases when the channel width or the deep level density of states increase.

CMOS voltage multiplier

Abstract: A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

Compensated current sensing circuit

Abstract: A current sensing circuit includes a first reference resistor (Rp) connected in series with the source-drain path of a current mirroring transistor (T2) across the source-drain path of a power transistor (T1) which is N times the size of the current mirroring transistor. Due to the first reference resistor (Rp), the current in the mirroring transistor is less than 1/N the current in the power transistor. To sense the current in the power transistor more accurately, the current sensing circuitry includes a reference circuit (22) in which the source-drain path of a compensating transistor (T3), of like size as the current mirroring transistor (T2), is connected in parallel with a second reference resistor (RR) to produce a reference current (IR) which is approximately equal to 1/N the current flowing in the power transistor (T1).

Circuit technique for cancelling non-linear capacitor-induced harmonic distortion

Abstract: Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor. The second transistor produces a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the input voltage. A current mirror receives a collector current of the second transistor. The current mirror produces in the second conductor a correction signal substantially equal and opposite to the first non-linear current.

Inductance and capacitance charge pump circuit for driving power mos transistor bridges

Abstract: The circuit comprises a tank capacitance and a charge circuit supplied with the same voltage as the bridge and comprising an inductance and a control transistor. There is also provided a control circuit, which comprises an oscillator controlling the periodic switching of control transistor and a comparator which controls the momentary clamping of control transistor in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance and the power supply voltage exceeds a preset maximum value and the unclamping of the same transistor when such difference falls below a preset minimum value. A further comparator similarly clamps control transistor if there is an excess current in the transistor itself.

CMOS output circuit using a low threshold device

Abstract: A CMOS output driver includes an n-channel low threshold device in series between a p-channel transistor and an output terminal. Under normal driver operation, the low threshold transistor drops essentially zero volts and is imperceptible in the circuit. However, under special mode conditions when high voltage is applied to the output terminal, the low threshold transistor stops conducting when the output terminal approaches Vcc, so that any further increase in the voltage at the output terminal cannot be applied to the drain of the p-channel transistor which can cause its failure.

Three transistor EEPROM cell

Abstract: An EEPROM cell suitable for use in programmable logic devices contains three transistors. A floating gate transistor is used to retain a programmed value using charge storage on the floating gate. A read transistor is connected between the floating gate transistor and an output signal line, and used to access the value stored in the floating gate transistor. A write transistor is connected to the floating gate transistor opposite the read transistor, and is used when programming the floating gate transistor. The write transistor and its associated control circuitry are fabricated to handle the higher programming voltages required by the floating gate device. The read transistor and associated drive circuitry are not required to handle the higher programming voltages, and can be fabricated using smaller, faster devices.

Control circuit for an inductive load

Abstract: The circuit according to the invention controls the supply to an inductive load by a power transistor of the N-channel MOS type, placed on the side of the positive terminal of a supply source delivering a voltage +Vbat. The conduction of the transistor is maintained by means of a gate voltage Vs>+Vbat supplied by a voltage multiplier. On cutting off this voltage, there is blocking of the transistor and discharge of the load, which rapidly develops a high negative voltage. An interconnecting transistor than prevents the return to conduction of the power transistor while, according to the invention, a transistor of the P-channel MOS type isolates the gate of the interconnecting transistor to authorize the application to said gate of the negative voltage developed by the inductive load. The invention has application to the control of actuators for the automobile industry.

Semiconductor transmission gate with capacitance compensation

Abstract: A transmission gate employs a pair of capacitors ahead of and a pair of capacitors behind a transistor. One capacitor of each pair is supplied with a control voltage pulse that leads and the other with a control voltage pulse that lags the complement of a control voltage pulse supplied to the gate of the transistor. The capacitors are typically each a MOS transistor with the gate serving as one terminal and the drain and source shorted together and serving as the other terminal. Moreover, each of the capacitors has a capacitance equal to one half the capacitance of the gate to source and gate to drain capacitance of the transistor. This circuitry makes possible charge compensation to avoid the build up of trapped charge in the transistor. The capacitance of the pair of capacitors ahead of the transistor is approximately equal to the gate-to-drain parasitic of the transistor and the capacitance of the pair of capacitors behind the transistor is equal to the parasitic capacitance of the gate-to-source of the transistor.

Tunnel EEPROM with overerase protection

Abstract: The present invention provides protection against the effects of overerasure while essentially maintaining a single transistor per memory cell through the use of an additional transistor for each row of memory cells. The added transistor is a positive voltage threshold device which is coupled between the connected sources of the floating gate transistors and a read input line to limit the threshold voltage. For programming, a second transistor with a negative voltage threshold is coupled in the same manner, but is coupled to a program input line. The positive threshold transistor prevents an unselected transistor from turning on during a read operation.

Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator

Abstract: There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.

Self-oscillation type converter

Abstract: A self-oscillation type converter comprises a transformer and a switching transistor. The switching transistor is connected in series to a primary winding of the transformer. A start current is applied from a power supply line to the switching transistor through a start resistor, so that the switching transistor is rendered conductive. A positive feedback is performed through an application of a constant current from a constant current circuit to a base of the switching transistor in response to a voltage generated from a feedback winding, whereby the switching transistor is turned on rapidly. A CR time constant circuit is connected to an output of the constant current circuit. An output of the CR time constant circuit is applied to the base of the transistor, a transistor Q2 is turned on after a lapse of time determined by a time constant of the time constant circuit, so that the switching transistor is forcibly turned off. A voltage outputted to a secondary winding is detected by a voltage comparing circuit. If the outputted voltage becomes higher than a reference voltage, a resistance value of the CR time constant circuit is decreased by a photocoupler, maintaining a turning-on time period of the switching transistor to be constant.

Data output buffer circuit for byte-wide memory

Abstract: An output buffer circuit for a byte-wide memory is described. The circuit has a circuit (Mdep1, Mdep3) to delay the rising or falling time of the gate voltage of a pull-up transistor (Mpu3, Mpu4) of an output driver (OD). The circuit (Mdep1, Mdep3) is arranged between a p-channel transistor (M9, M13) and an n-channel transistor (M10, M14) of the pull-up inverter (I1, I3). The circuit has another circuit to delay the rising time of the gate voltage of a pull-down transistor (Mpd3, Mpd4) of the output driver. This is arranged between a p-channel transistor (M11, M15) and an n-channel transistor (M12, M16) of the pull-down inverter (I2, I4). The described delay circuits may include a depletion transistor (Mdep1, Mdep3, Mdep2, Mdep4), the gate and source of which are connected to each other. By providing such delay mechanisms, generation of noise on both voltage and earth lines can be reduced.

Method of making asymmetrically optimized CMOS field effect transistors

Abstract: A process for forming an asymmetrically structured pair of CMOS field effect transistors having feature refinements matched to the individual idiosyncrasies of the p-channel and n-channel transistors. Complementary transistors are formed using a single photolithographic mask and a fabrication sequence which begins with the p-channel transistor source/drain formation. Thereafter, the p-channel transistor source/drain regions are metalized, the n-channel transistor lightly doped drain regions are formed, and the sidewall dielectric spaced n-channel transistor source/drain regions are formed using the p-channel metalization as a mask. The p-channel transistor source/drain metalization suppresses the effects of the relatively greater p-type source/drain resistivity, while the LDD structure of the n-channel transistor reduces performance degradation attributable to hot electron trapping. The structural asymmetry attributable to the process materially offsets performance limitations common to the individual CMOS transistor types.

Power-up pulse generator circuit

Abstract: In one embodiment, the pulse-generating circuit includes a triggering field-effect device having a source-drain path connected between a voltage supply and an internal node and having a gate connected to a source of reference potential, a capacitor connected between the voltage supply and the output node, and a detector field-effect device having a source-drain path connected between the output node and the source of reference potential and having a gate connected to the internal node An optional load device, an optional pull-down device, an optional second capacitor, an optional string of diode-connected devices, and an optional feedback device may be included Device channel lengths are specified for proper operation In one embodiment, the circuit includes only a detector field-effect transistor and a load field-effect transistor, the detector transistor having a channel length substantially longer than the channel length of the load transistor The circuit described and claimed herein is immune to the unpredictable behavior of static logic gates during the initial part of the power-on transient when the supply voltage is less than the threshold voltage of the integrated circuit transistors In particular, the circuit does not have a node connected to both a static pull-up path and a static pull-down path, both of which are on at the same time, forming a linear circuit

Method of making an MOS transistor having improved transconductance and short channel characteristics

Abstract: A transistor is described having reduced series resistance and a reduced peak lateral electric field. The peak lateral field is reduced by forming an image charge in the surface of the substrate underlying the edges of the transistor gate electrode. The image charge is created by impregnating portions of an oxide layer overlying the source and drain regions with an impurity having the same conductivity as that of the underlying substrate. The depletion region formed in the substrate by the image charge provides a graduated electric filed in the channel preventing hot carrier injection into the gate oxide and increasing the breakdown voltage. The image charge is of an opposite conductivity to that of the substrate and is thus composed of minority carriers. The high concentration of majority carriers near the surface of the substrate lower the series resistance of the transistor thereby increasing the drive current.

EEPROM device including read, write, and erase voltage switching circuits

Abstract: An electrically erasable nonvolatile semiconductor device of a high density of integration includes a memory matrix array formed of a plurality of MOS memory transistors. In an erasing operation, a voltage to turn off one selected MOS memory transistor is applied to the control gate electrode of the selected MOS memory transistor. At the same time, a voltage near the breakdown voltage of the selected MOS memory transistor is applied to the first electrode (e.g.--source electrode) of the selected MOS memory transistor and a predetermined voltage is applied to the second electrode (e.g.--drain electrode) of the same MOS memory transistor.

Gate drive for insulated gate device

Abstract: A circuit providing improved noise immunity for a first transistor including power terminals and a gate, the power terminals being connected to a power supply and to a load, and the gate being connected to receive control pulses from a pulse source for turning the first transistor on and off. A second transistor has power terminals connected across the gate and one power terminal of the first transistor, and a gate connected to a varying voltage circuit. This varying voltage circuit provides a voltage on the gate of the second transistor which varies in proportion to the spacing between the control pulses and turns on the second transistor when the spacing is greater than a preset value. The pulse source charges the varying voltage circuit during normal operation and the charge turns off the second transistor. During inactivity of the pulse source for a preset time period, the varying voltage circuit changes to the level where the second transistor turns on and shunts the first transistor, thereby preventing the first transistor from being turned on by noise signals.

Microwave multiple-state resonant tunneling bipolar transistors

Abstract: Fabrication and microwave performance of a multiple-state resonant-tunneling bipolar transistor (RTBT) are presented. This transistor exhibits a maximum DC current gain of 60 at room temperature and a cutoff frequency of 24 GHz. Frequency multiplication by a factor of five has been demonstrated with a single transistor. >