Showing papers on "Strained silicon published in 1985"

Formation and planarization of silicon-on-insulator structures

Abstract: A process for fabricating silicon-on-insulator structures on semiconductor wafers and planarizing the topology of the patterns formed from the silicon. In the composite, the process provides for the formation of monocrystalline silicon islands electrically isolated by dielectric in substantially coplanar arrangement with surrounding dielectric. According to one practice of the process, substrate silicon islands are initially formed and capped, and thereafter used as masks to direct the anisotropic etch of the silicon substrate to regions between the islands. During the oxidation which follows, the capped and effectively elevated silicon islands are electrically isolated from the substrate by lateral oxidation through the silicon walls exposed during the preceding etch step. The capped regions, however, remain substantially unaffected during the oxidation. With the electrically isolated silicon island in place, a silicon dioxide layer and a planarizing polymer layer are deposited over the wafer. Processing is concluded with a pair of etching operations, the first removing polymer and silicon dioxide at substantially identical rates, and the second removing silicon dioxide and monocrystalline silicon at substantially identical rates.

Silicon/carbon protection of metallic magnetic structures

Abstract: A superior wear-resistant coating is provided for metallic magnetic recording layers, where the improved coating is a hard carbon layer that is strongly bound to the underlying metallic magnetic recording layer by an intermediate layer of silicon. The silicon layer can be very thin, with a minimum thickness of a few atomic layers, and provides strong adhesion between the hard carbon protective layer and the metallic magnetic recording layer. A preferred technique for depositing both the intermediate silicon layer and the hard carbon layer is plasma deposition, since both of these depositions can be performed in the same reactor without breaking vacuum.

Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers

Abstract: Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.

Dielectric isolation of silicon by anodic bonding

Abstract: Dielectrically isolated silicon was produced by anodically bonding together a pair of silicon wafers whose surfaces were covered with an electrically nonconductive micron layer of thermally grown oxide. Although anodic bonding normally requires a conductive oxide, anodic bonding works with nonconductive silicon oxide if the total layer of silicon oxide is less than ten microns thick. The time needed for the anodic bonding process decreases monotonically with temperature because the increase in the deformability of silicon oxide overcomes the decrease in the maximum permissible anodic bonding voltage with temperature. However, factors such as silicon degradation and electrode reactions at very high temperatures indicate that a compromise temperature range of 850–950 °C is best for the anodic bonding of silicon oxide. Bonding voltages of 30–50 V for times of about an hour produced the best bonding yields at these temperatures. Anodically bonded silicon wafers were examined with infrared and ultrasonic transmission microscopy for bond quality. Small scattered nonbonded zones comprising on the average 5% of the total wafer area were found in all wafers. These nonbonded zones were the result of dust particles, entrapped gas, and dimensional mismatches between multiple bonding fronts.

Non-linear device for driving liquid crystal display

Abstract: A non-linear device used for driving a liquid crystal display is disclosed. This non-linear device comprises a first amorphous silicon layer, an insulator film deposited on the first silicon layer and a second amorphous silicon layer deposited on said insulator film. The insulator film may be made of silicon oxide or silicon nitride. The non-linear device thus has an SIS structure.

Controlled boron doping of silicon

Abstract: A technique for doping a silicon body (10) with boron. The surface to be doped is typically a trench sidewall, to be used as a storage capacitor or for isolation. By providing a silicon dioxide diffusion control layer, (20) and a polysilicon source layer (30) that incorporates the boron, well-controlled boron doping over a wide concentration range can be obtained. Control of the doping transfer can be obtained by the choice of ambients, either dry or steam. Furthermore, removal of the silicon dioxide and polysilicon layers following the doping process is facilitated due to the etch selectivity possible between SiO2 and Si. If desired, the layers may remain on the silicon body.

Silicon carbide film for X-ray masks and vacuum windows

Abstract: A layered structure for use in an X-ray membrane (pellicle) mask or a vacuum window is provided in which an intermediate amorphous layer such as silicon dioxide is grown on a silicon substrate which provides a stress relief medium and surface properties which enhance and improve subsequent process layers by breaking the epitaxial nature of these later deposited layers. Upon subsequent deposition of an inorganic overcoat, such as SiC, on the intermediate amorphous layer, the overcoat produces a nearly defect-free layer with a substantially reduced stress of suitable quality for X-ray lithography mask fabrication. Furthermore, additional alternating layers of a silicon carbide film and an intermediate inorganic layer, such as silicon nitride, can be deposited to obtain an even smoother silicon carbide surface and stronger structure.

Method of making silicon diaphragm pressure sensor

Abstract: A method of making a silicon diaphragm pressure sensor Includes forming an oxide film (10) on one surface of a monocrystalline silicon substrate (9). A polycrystalline silicon layer (11) is formed on the oxide film. The oxide film may be partly removed before the formation of the polycrystalline silicon layer. The polycrystalline silicon layer is heated and melt to recrystallize the same, thereby converting the polycrystalline silicon layer into a monocrystalline silicon layer. On the monocrystalline silicon layer may be epitaxially grown an additional monocrystalline silicon layer. By using the oxide film as an etching stopper, a predetermined portion of the substrate is etched over a range from the other surface of the substrate to the oxide film, thereby providing a diaphragm (12) of the pressure sensor.

Semiconductor integrated circuit structure with insulative partitions

Abstract: Grooves are formed in a single crystal silicon wafer in a pattern to encircle surface areas. Silicon dioxide is placed in the grooves and on the surface and then removed from certain of the areas. Layers of silicon are epitaxially grown only on these areas and their surfaces are oxidized. Polycrystalline silicon is deposited to a thickness greater than that of the epitaxial layers. Both sides of the wafer are ground and polished to produce flat, planar, opposite surfaces; one surface exposing surface areas of the epitaxial layers, the other surface exposing the silicon dioxide in the grooves. The resulting substrate has two types of silicon sections, each of which is electrically isolated from the other by silicon dioxide partitions. One type of section is of silicon of the original wafer, has a surface area in only one surface, and is suitable for the fabrication of low voltage, low power devices therein. The other type of section has two zones, one of silicon of the original wafer at one surface and the other of epitaxial silicon at the other surface. This type of section is suitable for the fabrication of high voltage, high power devices therein.

Method of fabricating a junction field effect transistor utilizing epitaxial overgrowth and vertical junction formation

Abstract: Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions. Each gate region has portions extending laterally between the adjacent barriers and the underlying strip to form a gate junction between each portion and the N-type silicon of the second epitaxial layer. N-type conductivity imparting material is ion implanted into the intervening zones to form source regions. Metal contacts are applied to the gate regions, the source regions, and the substrate.

Electron and ion beam degradation effects in AES analysis of silicon nitride thin films

Abstract: Silicon nitride films are currently investigated by AES combined with ion profiling techniques for their stoichiometry and oxygen content. During this analysis, ion beam and primary electron effects were observed. The effect of argon ion bombardment is the preferential sputtering of nitrogen, forming “covalent” silicon at the surface layer (AES peak at 91 eV). The electron beam irradiation results in a decrease of the covalent silicon peak, either by an electron beam annealing effect in the bulk of the silicon nitride film, or by an ionization enhanced surface diffusion process of the silicon (electromigration). By the electron beam annealing, nitrogen species are liberated in the bulk of the silicon nitride film and migrate towards the surface where they react with the covalent silicon. The ionization enhanced diffusion originates from local charging of the surface, induced by the electron beam.

A study of silicon MBE on porous silicon substrates

Abstract: The defect structure of Si MBE layers grown on porous silicon substrates depends critically on the technique for cleaning the substrate surface. Cross‐sectional TEM studies demonstrate that a combined sputter‐clean and thermal cycle markedly reduces the density of microtwins and dislocations in the epitaxial layer when compared with simple thermal cleaning. X‐ray diffraction studies show the porous silicon layer to be lattice‐matched to the underlying (100) bulk silicon substrate in the plane of the wafer so that misfit dislocations are not expected in the epitaxial layer. However, both the lattice parameter of the porous layer in the direction normal to the wafer and the thermal stability of the porous layer in vacuum, depend upon the resistivity of the starting wafer. The photoluminescence of a 4‐μm MBE layer grown on a sputter‐cleaned, high resistivity substrate is still dominated by recombination at dislocations.

Process for forming isolated silicon regions and field-effect devices on a silicon substrate

Abstract: Improved processing for MOS and CMOS transistors formed in an epitaxial-like layer. Field oxide regions are formed followed by the deposition of a polycrystalline or amorphous silicon layer which contacts the substrate at "seed windows" formed between the field oxide regions. The silicon layer is recrystallized from the substrate through the seed windows. The transistors are fabricated within the recrystallized silicon layer.

Analysis of defects in thin SiO 2 thermally grown on Si substrate

Abstract: Origin of defects in silicon dioxide thermally grown on silicon substrates has been studied. Breakdown characteristics of MOS capacitors with different gate areas were measured to examine the oxide defects. They strongly depend on the nature of silicon substrate, especially carbon and oxygen concentration in CZ silicon substrate. It is found that when the oxide is slightly etched by HF solution, an oxide defect becomes a pinhole defect. Assuming that oxygen precipitates in silicon substrate cause oxide defects, their density and size are estimated at 5-10×106/cm3and 140-320 A respectively. This model can explain the oxide dependence of breakdown failures and TDDB characteristic.

Germanium hardened silicon substrate

Abstract: Disclosed is a substitutionally strengthened silicon semiconductor material. A high concentration of germanium atoms is added to a silicon melt to thereby substitutionally displace various silicon atoms throughout the crystalline structure. The germanium atoms, being larger than the silicon atoms, block crystalline dislocations and thus localize such dislocations so that a fault line does not spread throughout the crystalline structure. In heavily boron doped P+ silicon substrates, the larger germanium atoms offset the crystalline shrinkage caused by the boron atoms, thereby equilibrating the silicon crystal size.

Method of making junction field effect transistor of static induction type

Abstract: Junction field effect transistor, specifically a static induction transistor, and method of fabricating. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. A layer of silicon nitride is applied and then removed except from the side walls of the grooves. Exposed silicon at the bottoms of the grooves is converted to silicon dioxide to build up layers of silicon dioxide in the grooves. The remaining silicon nitride is removed. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves. N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges. Metal contacts are applied to the gate ridges, the source ridges, and the substrate.

Method of making stabilized silicon-on-insulator field-effect transistors having 100 oriented side and top surfaces

Abstract: A MOS/SOI field-effect transistor is made by applying a layer of a photoresist over the surface of a single-crystalline silicon layer which is on a substrate of an insulating material, such as sapphire. The surface of the silicon layer is along a (100) crystallographic plane. The photoresist layer is defined to provide an area of the photoresist layer over the area of the silicon layer where the transistor is to be formed with the edges of the photoresist area being along the edges of (100) crystallographic planes which are perpendicular to the surface of the silicon layer. The portion of the silicon layer around the photoresist layer is etched with an anisotropic plasma etch which etches the silicon layer along the (100) crystallographic planes which are perpendicular to the surface of the silicon layer to form an island of the silicon. The etching is achieved by a two step process in which the first step etches part way through the silicon layer and the second step etches completely through with an overetch. This forms the silicon island with sides which extend along (100) crystallographic planes substantially perpendicular to the top surface and which are smooth, undamaged and have rounded edges with the top surface. After removing the photoresist, a MOS field-effect transistor is formed on the island.

The effect of mechanical stress on amorphous silicon transistors

Abstract: Amorphous silicon transistors have been mechanically stressed, and the shift in transistor characteristics as a function of applied stress observed. This effect could be a problem for large area active matrix arrays for A4 liquid crystal display panels. Plasma deposited amorphous silicon always displays compressive stress, whereas the plasma grown silicon nitride can be deposited with tensile or compressive stress, depending on the gaseous precursors and reactor parameters 1 . With careful selection of these parameters it is possible to grow a silicon/silicon nitride interface with a predetermined degree of stress. This stress can be selected to have a minimum effect on the transistor characteristics after further mechanical stress.

Integrated circuit load device

Abstract: One embodiment of the present invention provides a polycrystalline silicon loading device occupying a minimum of surface area in an integrated circuit. A very thin layer of silicon nitride is formed on the surface of a heavily doped contact point in the integrated circuit. An undoped layer of polycrystalline silicon is then formed on the surface of this thin layer of silicon nitride. A thin layer of silicon nitride is then formed on the surface of the undoped polycrystalline silicon layer. Finally a heavily doped polycrystalline silicon layer for making contact to the loading device is formed on the surface of the second thin silicon nitride layer. Because the two thin silicon nitride layers are very thin, tunneling current through the silicon nitride layers begins at a fairly low threshold level. After tunneling occurs, the main resistance element of the load device is the undoped polycrystalline silicon. The silicon nitride layers prevent the diffusion of dopants into the undoped polycrystalline silicon layer thereby maintaining the integrity of the resistive characteristics of the undoped polycrystalline silicon. Using this technique a load approximately 1 micron squared using present lithographic techniques may be fabricated.

Formation of silicon semiconductor layer

Abstract: PURPOSE: To obtain a silicon semiconductor layer having good electric characteristics in a low temperature process by annealing the layer on a substrate at low temperature to grow particle diameter, and then annealing it at melting point or lower of the layer to reduce grain boundary trap density of the layer CONSTITUTION: An SiO 2 film 2 on an insulating substrate is coated with a polycrystalline silicon layer 3, silicon ions Si + 4 are implanted to form an amorphous silicon, thereby forming a amophous silicon layer 5 It is crystalline grown by low temperature heat treatment of 700°C or lower to form a polycrystalline silicon layer 6 having large crystal grains Then, a superthin film silicon layer 6 is formed by etching with phosphoric acid, a laser 7 of short wave is emitted with energy of the degree not melting the layer 6 to be quasi-high temperature heat treated, to form the polycrystalline silicon layer 6 At this time the heat treatment is executed at 1,000°C or higher and melting point or lower This laser heat treatment reduces the grain boundary trap density, however, does not vary the grain diameter but instead, maintains as they are COPYRIGHT: (C)1987,JPO&Japio

Semiconductor temperature sensor

Abstract: A temperature sensor in the form of a temperature-dependent semiconductor resistor operating according to the current-spreading principle includes a semiconductor body of one conductivity type of silicon, which is provided on its lower side with a conductive layer and is provided on its upper side with at least one contact zone of the one conductivity type. The upper side is coated with a silicon oxide layer or a silicon nitride layer. In order for the given resistance value to be maintained more accurately and the temperature coefficient to have only a small spread, the semiconductor body is provided at its surface adjacent the silicon oxide layer or silicon nitride layer with a surface zone of the opposite conductivity type. Thus, it is possible to limit to a minimum value or to completely compensate for the influence of charges at the silicon oxide layer or silicon nitride layer.

Precision high-value mos capacitors

Abstract: A method for producing an improved capacitor in MOS technology utilizing a thin layer oxide dielectric to improve the active/parasitic capacitance ratio while maintaining a high breakdown voltage and a low leakage current A polycrystalline silicon layer is formed over a silicon dioxide field region on a wafer of semi-conductor silicon Phosphorus ions are implanted in the polycrystalline silicon layer at an implant energy between approximately 80 and 100 keV The surface of the polycrystalline silicon layer is oxidized to form an interpoly oxide, utilizing an oxidation temperature which, for the implant dosage of phosphorus ions used, is sufficient to make the interpoly oxide layer approximately 770 Angstroms thick The structure is then annealed at a temperature of approximately 1100°C in oxygen and HC1 A second polycrystalline silicon layer is formed over the interpoly oxide layer, and the process completed in the conventional manner

Solid-state photo sensor device

Abstract: A solid-state photo sensor device includes a first electrode layer for allowing light to pass therethrough, a first amorphous silicon layer of one conductivity type formed below the first electrode layer, a second amorphous silicon layer of a conductivity type, other than the one conductivity type, disposed below the first amorphous silicon layer, and an output circuit for delivering in the form of an electric current photocarriers excited at least in the second amorphous silicon layer. The first and second amorphous silicon layers each contain inpurity elements whose concentration ranges from about 0 molPPM to 200 molPPM. The output circuit delivers as an electric current also photocarriers excited in the first amorphous silicon layer.

Planar And Channel Optical Waveguides Utilizing Silicon Technology

Abstract: Planar and channel optical waveguide structures formed on silicon substrates using the fabricationtechniques of sputtering, thermal oxidation, and chemical vapor deposition are discussed. Losses in thevarious waveguide structures are reported. The use of polycrystalline silicon deposited by chemical vapordeposition onto any waveguide substrate to form integrated photodetector arrays is discussed. Laser recrystallization of the deposited silicon is used to allow fabrication of high quality devices. Measured values of photodiode reverse current of less than 10-12 amp and breakdown voltages of 40 volts are respectable values for small photodiodes incorporated into a dense array.Introduction In this paper we review a variety of optical guided wave structures formed utilizing silicon, concentrating on our recent achievements. Both structures formed on silicon substrates and those usingdeposited silicon will be discussed. Silicon as a substrate is of interest because it provides an excellentsurface for formation of a variety of waveguide structures, pattern processing technology for silicon iswell established and continues to be developed, and it is available in wafer substrates having diameters upto 200 mm. The excellent surface for waveguide formation is illustrated by the fact that the lowest valuesof loss reported for any planar optical wayeguide were for ZnO and Corning 7059 glass deposited on Si02 /Sisubstrates and subsequently laser annealed l"

Evidence for metastable defects in amorphous silicon thin film transistors

Abstract: When a positive gate voltage is applied to an amorphous silicon thin film transistor, electrons become trapped in states close to the silicon/dielectric interface. The density of these states rises continuously during the gate field application period. Various characteristics of the phenomenon are identified and a model is proposed in which metastable silicon dangling bonds are generated as a consequence of field effect induced band bending.

Method for producing high quality germanium-germanium nitride interfaces for germanium semiconductors and device produced thereby

Abstract: The present invention relates to the production of a stable insulator of a germanium and a device produced thereby. A germanium substrate is provided with a layer of silicon nitride deposited on one of the outer surfaces. Ionized nitrogen is implanted by an ion beam into the silicon nitride layer. An electric field is applied across the substrate and layer. In one embodiment the substrate and layer are annealed while maintaining the electric field, the electric field is removed, and a second annealing step grows the germanium nitride insulator layer subcutaneously. In another embodiment the subcutaneous germanium nitride insulator layer is grown during a single annealing step by continued application of the electric field to the substrate and the layer.

Epitaxial growth induced by phosphorus tribromide doping of polycrystalline silicon films on silicon

Abstract: The doping of polycrystalline silicon films is known to structurally change the material, producing larger grains after annealing. The grain growth is especially enhanced during high‐temperature doping using a PBr3 or POCl3 dopant source. In this paper, we report our observation of the PBr3‐doping induced epitaxial growth in polycrystalline silicon films deposited on silicon substrates and on the silicon in windows etched in the oxide. Epitaxial films contained twins induced by the microcrystals at the substrate‐film interface. Models are proposed to explain possible mechanisms for grain growth of undoped and PBr3‐doped polysilicon films. Also proposed are possible explanations for the observed microcrystalline growth at the epitaxy‐substrate interface and in the epitaxial film itself.

Use of optical emission spectroscopy to study hexafluoroethane reactive ion beam etching of silicon in the presence of oxygen

Abstract: By studying the light emission arising from the bombardment of silicon with an ion beam generated from C2F6, we find that emission from excited silicon atoms ejected from the surface is only observed for CF+x ions with energies greater than a threshold value. This is consistent with fragmentation of the CF+x ions on impact and adsorption of the resulting carbon on the silicon surface, thereby preventing the sputtering of silicon atoms. We associated the threshold energy with the appearance of areas of silicon which are free from carbon passivation. Addition of oxygen assists in the removal of this passivating carbon and reduces the observed threshold energies.

Ohmic contacts for hydrogenated amorphous silicon

Abstract: A method of forming an ohmic contact between an amorphous silicon hydride semiconductor and a substrate which includes coating a film of palladium on the substrate and overcoating the palladium with a thin film of amorphous silicon hydride forming a thin palladium silicide layer. The amorphous silicon hydride is dehydrogenated by annealing forming a highly defective amorphous silicon layer and a thicker palladium silicide layer through which carriers can readily tunnel. The amorphous silicon hydride semiconductor is then coated over the amorphous silicon layer to the desired thickness.