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Showing papers on "Substrate (electronics) published in 1974"


Journal ArticleDOI
TL;DR: In this article, the effect of the mode of deformation on the value of thermal conductance of flat surfaces in contact has been investigated and explicit expressions for thermal contact conductance were derived for cases of: (1) pure plastic deformation (2) plastic deformations of the asperities and elastic deformation of the substrate, and (3) pure elastic deformations on the substrate.

519 citations


Journal ArticleDOI
TL;DR: In this paper, the deformation of the crystal lattice of layers of GaxIn1−xAs (0.5 < x < 1.0) grown onto GaAs substrates by a chemical vapor deposition process was investigated.
Abstract: Deformation of the crystal lattice of layers of GaxIn1−xAs (0.5 < x < 1.0) grown onto GaAs substrates by a chemical vapor deposition process was investigated. For this study, Ga and In were transported as chlorides with HCl and AsH3 was the source of As. It was observed that the lattice constant along the direction of the film thickness was larger than that along the surface. This fact indicates that the crystal lattice of GaxIn1−xAs is compressed along the substrate surface as a result of lattice mismatch. The influence of both the composition of the epitaxial layers and the crystal plane of the substrate surface on the degree of this deformation was investigated. It was also found that the epitaxial orientation grew inclined to the substrate crystal when the crystal surface of the substrate was {100} or {110}.

289 citations


Patent
19 Jun 1974
TL;DR: In this paper, a new and improved microminiature field emission electron source and method of manufacturing using a single crystal semiconductor substrate is described using a new method for manufacturing a field emitter electron source.
Abstract: A new and improved microminiature field emission electron source and method of manufacturing is described using a single crystal semiconductor substrate. The substrate is processed in accordance with known integrated microelectronic circuit techniques to form a plurality of integral, single crystal semiconductor raised field emitter tips at desired field emission cathode sites on the surface of the substrate in a manner such that the field emitter tips are integral with the single crystal semiconductor substrate. An insulating layer and overlying conductive layer may be formed in the order named over the semiconductor substrate and provided with openings at the field emission site locations to form micro-anode structures for each field emitter tip. By initially appropriately doping the semiconductor substrate to provide opposite conductivity-type regions at each of the field emission sites, and appropriately forming the conductive layer, electrical isolation between the several field emission sites can be obtained.

209 citations


Journal ArticleDOI
TL;DR: In this paper, the authors used low energy diffraction to study monolayers of lead deposited in ultrahigh vacuum on to (111) and (110) faces of gold and made a comparison with a previous study of the (100) substrate.
Abstract: Auger electron spectroscopy and low energy diffraction have been used to study monolayers of lead deposited in ultrahigh vacuum on to (111) and (110) faces of gold. Comparison is made with a previous study of the (100) substrate. The succession of structure is similar on all three faces: low density arrangements followed by a compact hexagonal monolayer followed by another hexagonal arrangement which is interpreted as the intermetallic compound AuPb2. (A previous interpretation in terms of AuPb3, based on observations on the (100) face, is corrected.) The completion of the first monolayer is marked by sharp knees in the plots of the Auger signals as a function of evaporation time. Essentially the same alloy structure is found on all three faces. There are only slight differences due to differences in the substrate symmetry and structure.

141 citations


Patent
Shigeo Fukase1, Ushio Kawabe1
20 Mar 1974
TL;DR: In this paper, a method of manufacturing a thin-film field-emission electron source which is of a sandwich structure of a substrate - metallic film-insulating film - was proposed, which has at least one minute cavity and a conical shape within the cavity.
Abstract: A method of manufacturing a thin-film field-emission electron source which is of a sandwich structure of a substrate - metallic film-insulating film - metallic film and which has at least one minute cavity and a field-emitter of, for example, a conical shape within the cavity, comprises the steps of (i) forming on a substrate a first layer of metallic film pattern for current supply, (ii) depositing a second layer film made of an electron emissive material onto the entire area of the substrate provided with the first layer, and thereafter subjecting the second layer film to a mesa etch by a photoetching process, to form a conical emitter on the first layer film, (iii) forming a third layer made of an insulating material, the third layer having a height substantially equal to the level of a tip portion of the emitter, (iv) forming a fourth layer of metallic film pattern as an accelerating electrode, and (v) etching the third layer, so as to expose the extremity of the emitter. According to the manufacturing method, a thin-film field-emission electron source can be readily produced merely by the combination between the standard evaporation techniques and etching techniques.

129 citations


Patent
18 Dec 1974
TL;DR: A thin film polarographic oxygen sensor as discussed by the authors is a type of sensor where a number of thin film microcathodes are placed in holes in a thin film layer of silicon dioxide formed on a silicon substrate.
Abstract: A thin film polarographic oxygen sensor, in which a number of thin film microcathodes are deposited in holes in a thin film layer of silicon dioxide formed on a silicon substrate. A single thin film anode layer is deposited on the insulating layer and is insulated thereby from the cathodes. Preferably the microcathodes and the anode are located in a well in the thin film insulating layer, the well being filled flush to its surface with electrolyte, and having a thin film polymer filter membrane deposited thereover. Contacts to the anode and cathodes may be punched through a thin film insulating layer on the back of the wafer, the cathode contact being thereby connected to the substrate, and the anode contact being insulated from the substrate by an encircling thin film layer of silicon dioxide and extending through to the anode metallization layer. With appropriate choice of electrode, electrolyte and membrane materials, the cell may also be used as a pH sensor, a CO 2 sensor, a specific ion sensor, or to detect or sense other substances in solution. Single electrode units may also be formed by depositing thin film electrode materials on appropriate substrates.

108 citations


Journal ArticleDOI
TL;DR: In this paper, the composition of anodically and thermally grown silicon oxide layers was determined by backscattering and channeling measurements with 2.0 −MeV 4He+ ions.
Abstract: The composition of anodically and thermally grown silicon oxide layers was determined by backscattering and channeling measurements with 2.0‐MeV 4He+ ions. The oxide thickness was determined by ellipsometry and, for anodic films, the silicon removal rate was also determined by layer removal measurements. The surface layer consists of stoichiometric silicon dioxide plus a silicon‐rich transition layer between the substrate and the silicon dioxide. The number of silicon atoms in this layer was found to be 6 × 1015 atoms/cm2 (about three atomic layers).

98 citations


Journal ArticleDOI
TL;DR: In this article, a high speed diode element consisting of a metal metaloxide metal electron tunneling junction is formed by thin films deposited on a substrate, which couple the junction to incident radiation.
Abstract: A high‐speed diode element consisting of a metal‐metal‐oxide‐metal electron‐tunneling junction is formed by thin films deposited on a substrate. These junctions are integrated with deposited narrow resonant antenna structures which couple the junction to incident radiation. Broad‐band characteristics from radio and microwave frequencies to the infrared region are shown. Frequency mixing and the possibility of utilizing large numbers of elements simultaneously are also demonstrated.

95 citations


Patent
21 Jun 1974
TL;DR: In this paper, an insulated-gate thin film transistor is provided with low leakage drain current, and a second semiconductor layer makes contact with the source electrode and forms the channel of the transistor at least between the source and drain electrodes.
Abstract: An insulated-gate thin film transistor is provided with low leakage drain current. A second semiconductor layer makes contact with the source electrode and the semiconductor layer forming the channel of the transistor at least between the source and drain electrodes. The second semiconductor layer is of opposite type conductivity from the channel semiconductor layer and preferably forms a PN heterojunction with the channel semiconductor layer. Alternatively, a metal layer may be used in place of the second semiconductor to form a Schottky-barrier junction with the channel semiconductor layer instead of a PN junction. Preferably, the channel semiconductor layer and the second semiconductor layer or the metal layer are sequentially evaporation deposited through the same deposition mask onto a substrate from evaporant sources spaced substantially different distances from the substrate so that the sequential layers are deposited on first and second overlapping areas of the substrate.

84 citations


Patent
16 Aug 1974
TL;DR: In this paper, a doped oxide layer is formed on a semiconductor substrate utilizing reactive plasma deposition, where impurity doped thin film oxide deposits are formed by reacting suitable source gases in an RF plasma at low pressures and temperatures.
Abstract: A doped oxide layer is formed on a semiconductor substrate utilizing reactive plasma deposition. Impurity doped thin film oxide deposits are formed by reacting suitable source gases in an RF plasma at low pressures and temperatures. Passing an dopant compound in vapor form with a suitable carrier gas, in combination with a flow of silicon hydride and an oxide vapor flow, provides a solid film of doped silicon dioxide on a surface when the gases are subjected to an RF discharge. The method features low temperature processing which is particularly advantageously utilized in providing a doped oxide layer as a diffusion source for a Group III-V substrate.

80 citations


Journal ArticleDOI
TL;DR: In this paper, the analysis of low coverage deposits is accomplished by extrapolation of nucleus density and mean size data from higher coverage deposits, and from counts on zinc-amplified nuclei at low coverage.

Journal ArticleDOI
TL;DR: In this paper, it was shown that MOS-LSI devices can be satisfactorily metallized with tungsten thin films using the rf-diode sputtering technique.
Abstract: It is shown that MOS–LSI devices can be satisfactorily metallized with tungsten thin films using the rf-diode sputtering technique. The apparatus used consisted of a roots-blower and a Vacion pumped belljar system equipped with an 8-in. diam CVD W-cathode and a W-substrate table (anode) to which a dc bias could be applied. The control substrates were oxidized silicon wafers in which the back-oxide was removed to facilitate proper application of the bias. The effect of sputtering power (200–400 W) and of substrate bias (−200−+250 V) was studied on the deposition rate, substrate temperature, and various properties of the film such as electrical resistivity, stress, impurity concentration, constitution, and microstructure. The present process of W-film depostition has been found to offer several advantages. Low-power and low-voltage operation results in high quality MOS-compatible W-films. Substrate heating during the sputter deposition is kept to a minimum, thereby eliminating any undesirable metallurgical ...

Patent
04 Jan 1974
TL;DR: The technique for forming on a substrate an abrasion-resistant layer having super-hydrophobic properties is described in this article, which is applied to the face of the substrate which has an inherently hydrophobic micro-pile formation.
Abstract: The technique for forming on a substrate an abrasion-resistant layer having super-hydrophobic properties. Applied to the face of the substrate which has an inherently hydrophobic micro-pile formation are hydrophobic fumed silicon dioxide particles dispersed in a hydrophobic solvent. Dissolved in the solvent is a resinous binder in a small but effective amount which, by weight, is substantially less than one half the amount of the particles in the dispersion. Upon volatilization of the solvent, the resultant layer is composed primarily of fumed silicon dioxide particles strongly bonded to the face of the substrate.

Patent
11 Mar 1974
TL;DR: A transducer assembly for measuring absolute pressure utilizing a glass substrate and a thin silicon diaphragm upon which is diffused a piezoresistive bridge circuit is described in this paper.
Abstract: A transducer assembly for measuring absolute pressure utilizing a glass substrate and a thin silicon diaphragm upon which is diffused a piezoresistive bridge circuit. Bridge circuit components are properly oriented and connected to bonding pads formed on the silicon. The glass substrate has a circular well formed therein having a diameter at least as large as the diameter of the diaphragm. Conducting leads are deposited on the glass substrate in a pattern matching that of the bonding pads on the silicon. The silicon is bonded to the glass substrate with the silicon diaphragm overlying the well in the glass and the bonding pads overlying the conducting leads deposited on the glass. The bond provides a hermetic seal around the well, trapping a predetermined pressure therein which serves as a reference pressure. Ambient pressure variations cause stress variation in the diaphragm, resulting in unbalance of the bridge which can be sensed with associated circuits to give an indication of the ambient pressure.

Patent
27 Nov 1974
TL;DR: A dielectrically isolated, pressure responsive silicon diaphragm includes a single crystal substrate bonded to a single-crystal strain gage component with an intermediate insulating layer and glass bonding layer.
Abstract: A dielectrically isolated, pressure responsive silicon diaphragm includes a single crystal substrate bonded to a single crystal strain gage component with an intermediate insulating layer and glass bonding layer. The boric oxide enriched glass has a lower softening temperature than the insulating layer and semiconductor and a matching expansion coefficient. Illustratory products are integral silicon diaphragms, integrated circuits, and power devices for high temperature applications where junction isolation is useless. In the method of fabrication the composite is bonded at elevated temperature under pressure and the temporary substrate is removed mechanically and by a final preferential etch. Active components with thinner semi-conductor layers of uniform thickness can be produced.

Journal ArticleDOI
TL;DR: In this paper, a tipping technique has been employed for the growth of high purity epitaxial layers in liquid phase epitaxy by conventional tipping technique, and the binding energy of the main acceptor is determined to.
Abstract: Liquid phase epitaxy by conventional tipping technique has been employed for the growth of high purity epitaxial layers. The layers were grown at 720°‐560°C on (100) and (111) oriented InP substrates. Characteristic surface structures for the substrate orientations as a function of the growth temperature were observed. The layers were characterized by Hall data and photoluminescence measurements at low temperatures. The simultaneous observation of the band‐acceptor and donor‐acceptor pair transition due to the main acceptor in our LPE‐layers is reported. The binding energy of this acceptor is determined to .

Patent
18 Nov 1974
TL;DR: In this paper, a very thin high quality active layer of a III-V material such as GaAs is formed on a temporary substrate on which an etch-resistant stopping layer of AlGaAs has been previously formed.
Abstract: A very thin high quality active layer of a III-V material such as GaAs is formed on a temporary substrate on which an etch-resistant stopping layer of a material such as AlGaAs has been previously formed. Passivating layers are formed on the active layer, and the active layer is interfaced with a material which forms a permanent substrate. The temporary substrate is etched away with an etchant which is stopped by the stopping layer, following which the stopping layer is removed by etching with HF. The material in the active layer acts as a chemical stop for the HF, and consequently the etching process stops automaticaly at the boundary of the active layer, leaving that layer in the thin high-quality form in which it is grown. The etching rate of the stopping layer can be controlled by the proportion of Al in that layer.

Journal ArticleDOI
TL;DR: In this article, the work function difference of the AlSiO 2 ǫSi-system was measured by the MOS-capacitance-voltage technique for n - and p -type silicon as substrate and was compared to the results obtained by different authors applying the photoemission technique.
Abstract: The work function difference of the AlSiO 2 Si-system was measured by the MOS-capacitance-voltage technique for n - and p -type silicon as substrate and was compared to the results obtained by different authors applying the photoemission technique. It could be seen that the work function differences measured in this work differ largely from the values measured by the photoemission technique. On the basis of the results obtained the work function differences of the p + polySiSiO 2  nSi - and n + polySiSiO 2  p Si-system were defined by comparative measurements. From this it was evident that the location of the Fermi level in heavily doped polycrystalline silicon is identical to the location of the Fermi level in monocrystalline silicon of the same impurity concentration.

Journal ArticleDOI
TL;DR: In this article, a high resistivity ZnO film highly oriented with the c axis perpendicular to a metal substrate surface can be used as a low-frequency piezoelectric transducer which generates and detects compressional strain or stress perpendicular to the c-axis, i.e., perpendicular to film thickness through the piezolectric tensor component e311 or d311.
Abstract: It is revealed that a high‐resistivity ZnO film highly oriented with the c axis perpendicular to a metal substrate surface can be used as a low‐frequency piezoelectric transducer which generates and detects compressional strain or stress perpendicular to the c axis, ie, perpendicular to the film thickness through the piezoelectric tensor component e311 or d311 For example, tuning‐bar filters and a flat tuning‐fork filter are successfully composed of ZnO films and Elinvar‐alloy substrates whose resonant outputs are obtained even at frequencies lower than 100 kHz, and a piezoelectric microphone is composed of a ZnO film and a Ti membrane substrate

Journal ArticleDOI
TL;DR: In this paper, the growth procedure, crystal properties, and the photoluminescence and carrier lifetime behavior of n- and p-type In 1− x Ga x P epitaxial layers grown on (100) surfaces of GaAs (and GaAs 1− y P y, x = 0.48 y + 0.52) by a constant-temperature liquid-phase-epitaxial (CT-LPE) process are described.

Patent
Doris W. Flatley1
02 Aug 1974
TL;DR: In this article, a semiconductor structure from which various types of active semiconductor devices can be formed is made of an electrically insulating layer of a protective material, such as silicon dioxide, which extends onto and covers the sides of the semiconductor island.
Abstract: A semiconductor structure from which various types of active semiconductor devices can be formed is made of a semiconductor island on a transparent substrate, having thereon an electrically insulating layer of a protective material, such as silicon dioxide, which extends onto and covers the sides of the semiconductor island. The protective layer can either cover only the sides of the semiconductor island or extend over the top edge of the island. The protective layer is made by etching through a photoresist mask made of a negatively reacting photoresist which is formed by exposure to irradiation from beneath the uncovered surface of the substrate, whereby the thickness of the silicon island and the flux density of the irradiation are selected so that for a particular duration, the irradiation is completely attenuated by the semiconductor island.

Patent
28 Aug 1974
TL;DR: In this paper, a molecular beam technique for fabricating semiconductor devices from Group III(a)-V(a) compounds is described, in which an amorphous insulative layer is formed on selected portions of a monocrystalline substrate of the Group III-V-a material which is at least semi-insulating.
Abstract: Described is a molecular beam technique for fabricating semiconductor devices from Group III(a)-V(a) compounds. To form planar isolated devices, an amorphous insulative layer is formed on selected portions of a monocrystalline substrate of the Group III(a)-V(a) material which is at least semi-insulating. The amorphous layer may be formed by deposition of an oxide (e.g., SiO2), anodization of an oxide (e.g., native oxides) or by conversion of a surface layer of the substrate (e.g., by grit blasting). When a molecular beam containing Group III(a) and Group V(a) elements is directed at the surface, which is preheated to a temperature in the range of 450* to 675* C, monocrystalline Group III(a)-V(a) material grows on the exposed substrate whereas polycrystalline Group III(a)-V(a) material is simultaneously formed on the amorphous layer. The polycrystalline and monocrystalline surfaces are substantially coplanar. The polycrystalline material has a resistivity high enough to provide electrical isolation between active devices formed in the monocrystalline material. Examples of such active devices, which are also described, include beam-leaded Schottky barrier mixer diodes which have reduced parasitic capacitance and sealedjunction Schottky barrier IMPATT diodes. To form devices in which isolation is not required, the same procedure is followed except that neither the amorphous layer nor the substrate need be made of high resistivity material.

Journal ArticleDOI
TL;DR: In this article, CdS layers were epitaxially grown on GaAs in an atmosphere of hydrogen gas by the close-spaced technique, and the thermodynamics of the reaction, the morphology, and electrical properties of the CcS epitaxial films were studied.
Abstract: CdS layers were epitaxially grown on GaAs in an atmosphere of hydrogen gas by the close‐spaced technique. Then the thermodynamics of the reaction, the morphology, and electrical properties of the CdS epitaxial films were studied. Examinations of the temperature dependence of the evaporation rate of source CdS powder, of film growth rates, and of surface morphology demonstrated that the growth kinetics are between the mass‐transfer control case and the surface‐reaction control case, but closer to the former. The electrical properties of the films were greatly influenced by growth conditions, especially by substrate temperature. Film resistivity increased from 10−3 to 1 Ω cm as a function of substrate temperature, and the carrier concentration in the film increased exponentially as the temperature of the substrate was raised: Carrier concentration = 1.31×1029 exp (−1.98/kTsub) cm−3. The dominant donor species in CdS films was shown to originate from the autodoping of Ga by the GaAs substrate. Electron mobil...

Patent
29 Oct 1974
TL;DR: In this paper, a structure for providing arrays or individual hemispherical diodes and methods of producing the Diodes is presented. Butler et al. proposed a diode array is to be part of a configuration utilizing a substrate, the substrate is selected to have radiation transparency, a lower refractive index, and lattice constant lattice structure similar to that of a crystal layer grown in hemispheres formed in the substrate.
Abstract: A structure for providing arrays or individual hemispherical diodes and methods of producing the diodes. When the diode array is to be part of a configuration utilizing a substrate, the substrate is selected to have radiation transparency, a lower refractive index, and lattice constant and lattice structure similar to that of a crystal layer grown in hemispheres formed in the substrate. When the diode array is to be removed from the substrate, a material that can be preferentially etched is grown between the hemispheres formed in the substrate and the grown crystal layer that is to have light emitting areas.

Journal ArticleDOI
TL;DR: In this article, a monolithic acoustic surface wave parametric signal processor, fabricated with sputtered zinc oxide on an oxidized epitaxial n-on-n+ silicon substrate, is demonstrated and the dependence of the output signal strength on applied gate bias is analyzed.
Abstract: A monolithic acoustic surface wave parametric signal processor, fabricated with sputtered zinc oxide on an oxidized epitaxial n ‐on‐n+ silicon substrate, is demonstrated The dependence of the convolution output signal strength on applied gate bias is analyzed, and it is found that the maximum output occurs just before the semiconductor surface inverts, at which time the high‐frequency capacitance‐voltage characteristic has its maximum slope

Journal ArticleDOI
TL;DR: In this paper, the mobility distribution in a semiconducting epitaxial film on insulating substrate is derived from transmission line analysis of Q-V data combined with the C-V method for obtaining impurity distribution.
Abstract: The mobility distribution in a semiconducting epitaxial film on insulating substrate is derived from transmission line analysis of Q‐V data combined with the C‐V method for obtaining impurity distribution. The mobility thus obtained is found to agree with that obtained by Hall effect measurements for an n‐type epitaxial GaAs layer on semi‐insulating Cr‐doped GaAs substrate.

Journal ArticleDOI
TL;DR: In this article, an epitaxial growth of a semiconductor film from solid solution by dissolution and transport of an evaporated semiconductor layer through a metal film has been demonstrated.
Abstract: Epitaxial growth of a semiconductor film from solid solution by dissolution and transport of an evaporated semiconductor layer through a metal film has been demonstrated. A Ge growth layer of 4800 A has been obtained by heating the system bulk‐Ge/Al/evaporated‐Ge at 300 °C. Electrical measurements indicate that the layers are heavily doped p type. A silicon growth of 2000 A has been obtained by heating the system bulk‐Si/Pd/evaporated‐Si at 600 °C. Channeling measurements show that the Ge and Si layers are well ordered and epitaxial with the underlying substrate.

Journal ArticleDOI
TL;DR: The initial growth of Cu on (111) Ag surfaces was examined in situ by RHEED and later by TEM and TED as discussed by the authors, which revealed a very low density of dislocations and only an extremely rare irregular network.
Abstract: The initial growth of Cu on (111) Ag surfaces was examined in situ by RHEED and later by TEM and TED. The substrates were very smooth (111) Ag films, single positioning oriented, evaporated on NaCl/mica in UHV just prior to Cu growth. The Cu overgrowths were double positioning oriented and contained microtwins. The mode of Cu growth depended on the substrate temperature. Cu deposited at 210 °C formed island-type overgrowths. At 25 °C, Cu formed a very smooth overgrowth up to about two monolayers. Thereafter island growth occured. From the smooth Cu–Ag bilayers, anomalous RHEED patterns were obtained similar to those observed by Gradmann and Krause on Ag–Cu bilayers. These authors interpreted their diffraction patterns in terms of a postulated regular network of interfacial dislocations. However, high-resolution TEM of Cu–Ag bilayers in the present work revealed a very low density of dislocations and only an extremely rare irregular network.

Patent
23 Jan 1974
TL;DR: In this article, the authors describe transparent, electroconductive articles produced by cathode sputtering on refractory substrates, a metal from the group of elements having an atomic number from 48 to 51 and mixtures thereof, and preferably a controlled proportion of tin to indium, in a low pressure atmosphere containing a controlled amount of oxygen at a controlled substrate temperature within a temperature range of 400° F.
Abstract: Transparent, electroconductive articles produced by cathode sputtering on refractory substrates, a metal from the group of elements having an atomic number from 48 to 51 and mixtures thereof, and preferably a controlled proportion of tin to indium, in a low pressure atmosphere containing a controlled amount of oxygen at a controlled substrate temperature within a temperature range of 400° F. to a temperature at which the substrate becomes distorted or detrimentally affected, usually at or above 600° F.

Journal ArticleDOI
TL;DR: In this paper, a glass-coated bismuth film was deposited onto a glass substrate at room temperature and their Hall coefficients and electrical resistivities were measured between 77 and 300°K.
Abstract: Glass‐coated bismuth films were deposited onto a glass substrate at room temperature and their Hall coefficients and electrical resistivities were measured between 77 and 300°K. Scanning electron micrographs revealed that the films prepared in this way were more polycrystalline than those deposited onto a heated mica substrate. Interesting features were found in the temperature dependence of the Hall coefficient: the thinner films with thickness t 500 A were always n type over the temperature ranges studied. Hall mobility and magnetoresistance data are also presented here and the experimental results are discussed qualitatively.