Showing papers on "System bus published in 2005"

Service and diagnostic tool for hvac systems

Abstract: An HVAC system includes a portable controller unit which communicates with an indoor HVAC component and an outdoor HVAC component over a digital communication bus. A multiple of docking stations each in communication with the data bus are located at a multiple of locations throughout the system such that the portable controller unit may be selectively connected to any of the ports and moved therebetween. By moving the portable controller unit, the technician is then physically present at the HVAC component while exercising the system to obtain additional information and measurements directly from the HVAC component.

Serial communicating hvac system

Abstract: An HVAC system is provided with control communication over a serial data bus. In this manner, the hard wired controls of the prior art are eliminated. A thermostat includes a central control microprocessor that communicates control signals to and from a microprocessor at an indoor unit. The indoor unit may be a furnace or a fan/heater combination. The microprocessor on the indoor unit is operable to receive signals from the central control microprocessor and control the indoor unit accordingly. Moreover, the microprocessor at the indoor unit is operable to pass control signals on to an outdoor unit such as an air conditioner or heat pump. Most preferably, this outdoor unit is provided with its own microprocessor. Further, other peripheral units may be incorporated to be controlled over the same data bus from the thermostat. Installation and updating of HVAC systems is greatly simplified by this control arrangement.

Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology

Abstract: A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of “data slices” or a plurality of portions of the memory module data bus that is coupled to the respective integrated circuit buffer devices. Each integrated circuit buffer device is also coupled to a bus that provides control information that specifies an access to at least one integrated circuit memory devices. According to an embodiment, a SPD device stores information regarding configuration information of the memory module. In embodiments, at least one integrated circuit buffer devices access information stored in the SPD device. In a package embodiment, a package houses an integrated circuit buffer die and a plurality of integrated circuit memory dies.

Highly compact non-volatile memory and method therefor with internal serial buses

Abstract: A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits are organized into a bank of similar stacks of components. Redundant circuits among each stack are factored out. In one aspect, a serial bus allows communication between components in each stack, thereby reducing the number of connections in a stack to a minimum. A bus controller sends control and timing signals to control the operation of the components and their interactions through the serial bus. In a preferred embodiment, the bus transactions of corresponding components in all the similar stacks are controlled simultaneously.

Computing device with flexibly configurable expansion slots, and method of operation

Abstract: A computing device that allows for a flexible allocation of bandwidth among peripheral devices using a peripheral bus is disclosed. The computing device includes a peripheral bus and at least two slots. The computing device may be used with a single peripheral card or multiple peripheral cards. In a multi-card configuration the invention allows the bandwidth on the peripheral bus to be shared by all the cards. In a single-card configuration, the computing device allows available bandwidth on the peripheral bus to be used by a single card. The device is particularly useful with PCI express compliant expansion cards, such as graphics adapters.

Liquid crystal display device with improved viewing angle characteristics

Abstract: A liquid crystal display device, in which the liquid crystal molecules are aligned vertically when no voltage is applied, includes pixels each having plural sub-pixel electrodes, a data bus drive circuit for applying drive signals to the sub-pixel electrodes via a data bus line and a switching element, and alignment regulation structure for regulating the direction of alignment of liquid crystal molecules. The first and second sub-pixel electrodes have different areas. The data bus drive circuit applies a first drive signal, which causes luminance to change from minimum to maximum for an increase of input grayscale of image signal, to the first sub-pixel electrode, and a second drive signal, which causes the luminance to be lower than the first drive signal, to the second sub-pixel electrode.

Scalable DMA remapping on a computer bus

Abstract: A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus controller over a bus are addressable via a memory mapped address within the address space. An address translation table is stored on at least one of the plurality of bus components. The bus translation table stores a translation between a virtual address and a real address.

Electrical energy management system on a more electric vehicle

Abstract: An electrical energy management system (100) for a more electrical vehicle is provided The electrical energy management system (100) includes a vehicle operation system (120) for controlling operation of the more electrical vehicle; an electrical system (140) for controlling electrical power generation, conversion, distribution and aero system utilities of the more electrical vehicle; a first controller (102); and a second controller (104) redundant to the first controller (102) The second controller (104) is coupled to the first controller (102) via an inter-controller data bus (106) Each of the first and second controllers (102, 104) is coupled to the vehicle operation system (120) via a vehicle data bus (108) Each of the first and second controllers (102, 104) is coupled to the electrical system (140) via a local data bus (110) The first and second controllers (102, 104) process same data in a first operation mode and process different data in a second operation mode

Apparatus and method for enabling digital and analog data communication over a data bus

Abstract: An electronic apparatus (100) such as an audio apparatus enables both digital and analog data to be communicated over a data bus such as a universal serial bus (USB) with a single low-cost connector such as a USB connector. According to an exemplary embodiment, the electronic apparatus (100) includes a connector (60) operative to couple the electronic apparatus (100) to one of a digital device (200) and an analog device (300). A controller (10) is operative to determine whether the connector (60) is coupled to the digital device (200) or the analog device (300). A switch (50) is operative to couple the connector (60) to one of a digital element and an analog element responsive to the determination.

Carrier module for adapting non-standard instrument cards to test systems

Abstract: A carrier module that is able to adapt non-standard instrument cards to the architecture of a test system is disclosed. Instrument cards based on non-standard architectures may be combined on a single carrier module. The carrier module is then plugged into the test head of the test system. The carrier module provides circuitry, contained on a plug-in sub-module called an Application Interface Adapter (AIA), to interface between the instrument cards and the test head interface connector. Additionally, the AIA may also provide access from the instrument cards to ATE system calibration circuitry. The carrier module uses the standard data bus of the test system for housekeeping and control functions. A second bus provides the bus for the non-standard instrument cards. Software drivers provided with the instrument cards are encapsulated with an appropriate wrapper so that the cards run seamlessly in the software environment of the test system.

High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder

Abstract: In this paper, we proposed parallel and pipeline architecture for the sub-pixel interpolation filter in H.264/AVC conformed HDTV decoder. To efficiently use the bus bandwidth, we bring forward three memory access optimization strategies to avoid redundant data transfer and improve data bus utilization. To improve the processing throughput, we use parallel and multi-stage pipeline architecture for conducting data transmission and interpolation filtering in parallel. Moreover, to balance the tradeoff between memory accessing scheme and sub-pixel interpolation processing granularity we devise a dedicated buffer organization to convert tree-structured block size reading to fixable and sequential processing. As compared to the traditional designs, our scheme offers 60% reduced memory data transfer. While clocking at 66 MHz, our design can support 1280 /spl times/ 720 @30 Hz processing throughput. The proposed design is suitable for low cost and real-time applications. Moreover, it can easily be applied in system-on-chip design.

Blade server system with a management bus and method for managing the same

Abstract: A blade server system with a management bus and method for managing the same. The blade server system includes a connection board and a management module. The connection board is used for modular interconnection, including communication paths for conducting signals including a management bus signal group and a first bus signal group. The management module is used for management of the blade server system using signals including the management bus signal group and the first bus signal group. If a module is detected, the management module selects the detected module through the management bus and acquires module configuration information of the detected module through the first bus signal group. Distribution of power from a power source to the blade server system is determined according to system configuration information including the module configuration information of the module so that the power source is prevented from being overloaded.

Liquid crystal display device and method of preventing image sticking thereon

Abstract: A sub picture element electrode directly connected to a thin film transistor is disposed between a floating sub picture element electrode capacitively coupled to a control electrode and a gate bus line in order to prevent injection of electric charges from the gate bus line to the floating sub picture element electrode. Moreover, a shield pattern electrically connected to an auxiliary capacitance bus line is formed between the floating sub picture element electrode and a data bus line. This shield pattern avoids injection of electric charges from the data bus line to the floating sub picture element electrode.

Systems and methods for correcting errors in I2C bus communications

Abstract: Systems, methods and media for clearing a hung I2C bus are disclosed. In one embodiment, a monitor monitors the I2C bus data and clock lines and detects if a hung bus occurs. The monitor times packet transactions on the bus to determine if a maximum transaction time has elapsed while the lines are in a hung state. The monitor allows selective reset of individual slave devices and bus masters to clear a hung bus.

Bus arbitration apparatus and bus arbitration method

Abstract: The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs the arbitration with priority in response to properties of bus masters. It sequentially arbitrates a first hierarchy bus master of which requests are urgent, a second hierarchy bus master that requests data processing in real time, and a third hierarchy bus master that is neither a first hierarchy bus master nor a second hierarchy bus master sequentially.

Hardware Engines for Bus Encryption: A Survey of Existing Techniques

Abstract: The widening spectrum of applications and services provided by portable and embedded devices bring a new dimension of concerns in security. Most of those embedded systems (pay-TV, PDAs, mobile phones, etc...) make use of external memory. As a result, the main problem is that data and instructions are constantly exchanged between memory (RAM) and CPU in clear form on the bus. This memory may contain confidential data like commercial software or private contents, which either the end-user or the content provider is willing to protect. The goal of this paper is to clearly describe the problem of processor-memory bus communications in this regard and the existing techniques applied to secure the communication channel through encryption - Performance overheads implied by those solutions will be extensively discussed in this paper.

Memory hub architecture having programmable lane widths

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Apparatus, system, and method for bus link width optimization of a graphics system

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Motion compensation memory access optimization strategies for H.264/AVC decoder

Abstract: H.264/AVC is the latest standard for video coding drafted jointly by the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group. H.264/AVC provides up to 50% gain in compression efficiency over a wide range of bit rates and video resolutions compared to previous standards. On the other hand, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 visual simple profile. In VLSI implementations of the H.264/AVC decoder, off-chip memory access is the main time and power consuming operation, and the motion compensation module is the main memory access bottleneck. This paper proposes four optimization strategies to reduce memory access data cycles and improve memory data bus utilization. Experimental results show that about 60% data cycle reduction can be achieved and more than 20% memory data bus utilization can be improved by these strategies over typical test sequences.

Method for the fast exploration of bus-based communication architectures at the cycle-count-accurate-at-transaction-boundaries (CCATB) abstraction

Abstract: A computer system simulation method starts with algorithmically implementing a specification model independently of hardware architecture. High level functional blocks representing hardware components are connected together using a bus architecture-independent generic channel. The bus architecture-independent generic channel is annotated with timing and protocol details to define an interface between the bus architecture-independent generic channel and functional blocks representing hardware components. The interface is refined to obtain a CCATB for communication space. The read( ) and write( ) interface calls are decomposed into several method calls which correspond to bus pins to obtain observable cycle accuracy for system debugging and validation and to obtain a cycle accurate model. The method calls are replaced by signals, and the functional blocks representing hardware components are further refined to obtain pin/cycle-accurate models which can be manually or automatically mapped to RTL, or be used to co-simulate with existing RTL components.

Solid-state image pickup apparatus and control method thereof

Abstract: An arithmetic circuit, which is retained by each pixel in a conventional image sensor, is shared by each column. Signal processing circuits of different configurations are provided on signal transmission paths in an upward direction and a downward direction of a vertical signal line for extracting an image signal from each pixel, whereby image output processing and arithmetic processing are performed completely separately by the different circuit blocks. Thus, image quality of an actual image is improved and optimum design for arithmetic processing is made possible. Specifically, an I-V converter circuit unit, a CDS circuit unit and the like are provided on the image output side. A current mirror circuit unit, an analog memory array unit, a comparator unit, a bias circuit unit, a data latch unit, an output data bus unit and the like are provided on the arithmetic processing side.

Serial bus system

Abstract: A serial bus system for data communication between devices according to a master-slave protocol has a data bus connecting master and slave devices and a shared clock system arranged to provide a shared-clock signal to the master and slave devices. The master and slave devices are arranged to derive device-individual clock signals which are synchronized with data received on the data bus, from the shared-clock signal and a data-timing indication on the data bus.

Distributed direct memory access for systems on chip

Abstract: A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory.

Semiconductor memory circuit

Abstract: The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

Object-based storage device with low process load and control method thereof

Abstract: An object-based storage device with a low process load and a control method thereof are provided. The object-based storage device includes: a storage unit; a temporary storage unit; a transmission unit; a first control unit; and a second control unit. Particularly, the temporary storage unit and the transmission unit are provided separate from the main storage unit and the system bus, and these separately provided temporary storage unit and transmission unit allow a direct data transmission, which attributes to a reduction in a process load and a burden on the system bus.

Computer assisted hidden tooth abnormal correction system

Abstract: A computer aided hidden tooth deformity correcting system is composed of a data acquisition subsystem, an intelligent tooth sleeve modelling subsystem, transparent tooth sleeve manufacture subsystem and data bus.

System for controlling and monitoring an array of point-of-load regulators by a host

Abstract: A power control system comprises a plurality of POL regulators, at least one serial data bus operatively connecting the plurality of POL regulators, and a system controller connected to the serial data bus and adapted to send and receive digital data to and from the plurality of POL regulators. The serial data bus further comprises a first data bus carrying programming and control information between the system controller and the plurality of POL regulators. The serial data bus may also include a second data bus carrying fault management information between the system controller and the plurality of POL regulators. The power control may also include a front-end regulator providing an intermediate voltage to the plurality of POL regulators on an intermediate voltage bus.

Method for data transmission

Abstract: A method for data transmission between participants communicating by means of a data bus, in which as high a transmission likelihood for additional data as possible is to be assured by providing that in the exchange of data telegrams between the participants within the cycle time 13 a predetermined for one transmission cycle 13, at least one first and at least one second time slot 11, 12 are used, and the first time slot 11 serves to forward process data and the second time slot 12 serves to forward additional data, and the length of the data telegrams representing the additional data is predeterminable within the length of the corresponding time slot 12.

Method and communications system for transmitting information in a motor vehicle

Abstract: A communications system for a motor vehicle, including a plurality of electrical components, a data bus structure to which the components are connected in order to transmit information among the components, and a power line structure to which the components are connected in order to be supplied with power. The information is transmitted in successive cycles over the data bus structure, each cycle including at least one time window for transmitting information at specific points in time and at least one event window for transmitting information in response to specific events. The communications system includes an arrangement for redundantly transmitting information which merely transmits the information transmitted in the at least one time window over the data bus structure at least partially over the power line structure as well.

Bus system with multiple modes of operation

Abstract: An apparatus and a computer-implemented method for processing data in a bus system component. The bus system component is configured to operate in one of an endpoint mode and a root complex mode. Responsive to configuring the bus system component to operate in endpoint mode, the data is processed through the bus system component according to an endpoint process. Responsive to configuring the bus system component to operate in root complex mode, the data is transferred through the bus system component according to a root complex mode. In an illustrative example, the bus system component is a peripheral control interconnect express component.