Showing papers on "Transimpedance amplifier published in 2022"

A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS

Abstract: We review the design trade-offs that exist in CMOS inverter-based shunt-feedback transimpedance amplifier (SF-TIA) when optimizing for energy efficiency. We analyze the performance of series and shunt inductive peaking techniques for bandwidth enhancement and identify the most effective one for low-power CMOS TIAs. As a design example, we present a 128-Gb/s single-ended linear transimpedance amplifier (TIA) intended for use in receivers for 400-G Ethernet optical modules and co-packaged optics. The inverter-based SF-TIA is implemented in a 22-nm fin field-effect transistor (FinFET) CMOS technology, supporting a data rate of 128-Gb/s PAM4 with a dc transimpedance gain of $59.3~{\mathrm{ dB}}{\cdot }\Omega $ while dissipating only 11.2 mW of power from a 0.8-V supply. It achieves a 3-dB transimpedance bandwidth of 45.5 GHz with a total integrated input referred noise current of $2.7~\mu \text{A}_{\text{rms}}$ . These results improve upon the state-of-the-art BiCMOS/CMOS linear TIAs, demonstrating the potential for building highly integrated, low-cost, high-sensitivity 100+G CMOS optical receivers using FinFET CMOS process technology.

0.5 V Current-Mode Low-Pass Filter Based on Voltage Second Generation Current Conveyor for Bio-Sensor Applications

Abstract: This paper presents a low-voltage low-power current-mode third-order low-pass filter (LPF) based on voltage second generation current conveyor (VCII). The VCII utilizes the bulk-driven MOS transistor technique to achieve a wide input voltage range at low supply voltage of 0.5 V. Also, the VCII operates in the subthreshold region to achieve nano-power consumption of 390 nW. A third-order low-pass filter that is presented as an application of the VCII can operate as both current- and transimpedance-mode filters. The filter consumes 2.73 $\mu \text{W}$ and the total harmonic distortion (THD) is below 1 % for sine-wave input signal below 350 nA _pp @ 10 Hz. The post-layout simulation results based on TSMC 0.18 $\mu \text{m}$ CMOS process are presented and confirms the futures of the filter.

1.2 V Differential Difference Transconductance Amplifier and Its Application in Mixed-Mode Universal Filter

Abstract: This paper presents a new mixed-mode universal filter based on a differential difference transconductance amplifier (DDTA). Unlike the conventional transconductance amplifier (TA), this DDTA has both advantages of the TA and the differential difference amplifier (DDA). The proposed filter can offer four-mode operations of second-order transfer functions into a single topology, namely, voltage-mode (VM), current-mode (CM), transadmittance-mode (TAM), and transimpedance-mode (TIM) transfer functions. Each operation mode offers five standard filtering responses; therefore, at least twenty filtering transfer functions can be obtained. For the filtering transfer functions, the matching conditions for the input and passive component are absent. The natural frequency and the quality factor can be set orthogonally and electronically controlled. The performance of the proposed topology was evaluated by PSPICE simulator using the 0.18 µm CMOS technology from the Taiwan Semiconductor Manufacturing Company (TSMC). The voltage supply was 1.2 V and the power dissipation of the DDTA was 66 µW. The workability of the filter was confirmed through experimental test by DDTA-based LM13600 discrete-component integrated circuits.

A 50-GBaud QPSK Optical Receiver With a Phase/Frequency Detector for Energy-Efficient Intra-Data Center Interconnects

Abstract: This paper describes the energy-efficient realization of a QPSK optical receiver (CoRX) for short-reach intra-datacenter interconnects based on analog coherent detection. The CoRX comprises inphase and quadrature channels for each polarization and a high-speed phase-frequency detector (PFD) that provides feedback to stabilize an optical local oscillator (LO) and maintain coherence with the received optical signal. Each receive (RX) channel consists of a transimpedance amplifier (TIA) based on a Cherry-Hooper emitter follower (CHEF). The electronic RX is implemented in a 130-nm SiGe HBT technology ( $f_{T} = 300$ GHz), consumes 534 mW of DC power for a total electrical RX energy efficiency of 5.34 pJ/bit, and occupies 2.8 $mm^{2}$ . Electrical characterization of the CoRX on an FR-4 PCB assembly demonstrates operation up to 60 GBaud with a bit error rate (BER) of less than 10⁻¹². A co-packaged optical/electrical CoRX assembly with a silicon photonic receiver is characterized using a commercial-off-the-shelf quadrature phase-shift keying (QPSK) transmitter for constellations up to 50 GBaud (100 Gbps) at BER below KP4-FEC ( $2.2\times 10^{-4}$ ).

112 Gb/s PAM-4 Silicon Photonics Receiver Integrated With SiGe-BiCMOS Linear TIA

Abstract: We have developed a silicon photonics receiver integrated with a SiGe-BiCMOS linear transimpedance amplifier (TIA) using the flip-chip bonding technology to assist in resolving the I/O bottleneck problem in inter-chip data communication. The proposed device demonstrated optical 112 Gb/s four-level pulse amplitude modulation (PAM-4) operations and clear eye openings without any equalization for the pseudorandom binary sequence $2^{\mathbf {15}}$ – 1 signal. The 3 dB bandwidth and transimpedance gain were designed to be 37.1 GHz and 60.1 dB $\boldsymbol {\Omega } $ , respectively, at a supply voltage of 3.3 V. The consumption current of the linear TIA was 95.1 mA, and it resulted in a power consumption of 314 mW (2.8 pJ/bit). A linear TIA circuit is a key technology for PAM-4 operation; therefore, we discussed the linearity of our receiver response through eye diagrams and simulation. The measured eye diagrams agreed with the simulation results, and the proposed device maintained a linear response for up to 450 $\boldsymbol {\mu }\text{A}_{\mathbf {p-p}}$ input current. In addition, its operation rate of 112 Gb/s is the highest operation rate reported for a silicon photonics PAM-4 receiver based on flip-chip 3D integration with a germanium photodetector and a SiGe-BiCMOS linear TIA.

Silicon Photonic Based Stacked Die Assembly Toward 4×200-Gbit/s Short-Reach Transmission

Abstract: We presenta silicon photonic based stacked die assembly (SDA) compatible with the commercial complementary metal-oxide-semiconductor process. The SDA consists of a driver die and a transimpedance amplifier die, both populated onto a photonic integrated circuit die with a dimension of 5 mm×9 mm. The SDA is designed to be an O-band optical engine for a 4×200-Gbit/s parallel single-mode fiber short-reach transmission system. Performance of several pulse amplitude modulation (PAM) formats are evaluated and compared for the feasibility of 200-Gbit/s transmission. Aided by a Volterra nonlinear equalizer, the system experiment demonstrated that PAM-8 is a promising candidate for single lane 200-Gbit/s transmission with achieved bit error rate (BER) floor of 1.4×10 ⁻³ . Instead of using costly optical amplifier, the system relies on the transimpedance amplifier on the SDA to boost up receiver sensitivity, which is shown to be −2.6 dBm and −2.0 dBm for 2-km and 10.5-km fiber transmissions respectively. The system impairments and noise sources are quantitatively discussed to facilitate further hardware improvement. We believe this is the first demonstration of net 200-Gbit/s transmission over 10 km without optical amplification, accomplished with silicon photonic integrated circuit and offline processing.

Evaluation of a Transimpedance Matrix Algorithm to Detect Anomalous Cochlear Implant Electrode Position

Abstract: Introduction: Transimpedance measurements from cochlear implant electrodes have the potential to identify anomalous electrode array placement, such as tip fold-over (TFO) or fold-back, basal electrode kinking, or buckling. Analysing transimpedance may thus replace intraoperative or post-operative radiological imaging to detect any potential misplacements. A transimpedance algorithm was previously developed to detect deviations from a normal electrode position with the aim of intraoperatively detecting TFO. The algorithm had been calibrated on 35 forced, tip folded electrode arrays in six temporal bones to determine the threshold criterion required to achieve a sensitivity of 100%. Our primary objective here was to estimate the specificity of this TFO algorithm in patients, in a prospective study, for a series of electrode arrays shown to be normally inserted by post-operative imaging. Methods: Intracochlear voltages were intraoperatively recorded for 157 ears, using Cochlear’s Custom Sound™ EP 5 electrophysiological software (Cochlear Ltd., Sydney, NSW, Australia), for both Nucleus® CI512 and CI532 electrode arrays. The algorithm analysed the recorded 22 × 22 transimpedance matrix (TIM) and results were displayed as a heatmap intraoperatively, only visible to the technician in the operating theatre. After all clinical data were collected, the algorithm was evaluated on the bench. The algorithm measures the transimpedance gradients and corresponding phase angles (θ) throughout the TIM and calculates the gradient phase range. If this was greater than the predetermined threshold, the algorithm classified the electrode array insertion as having a TFO. Results: Five ears had no intraoperative TIM and four anomalous matrices were identified from heatmaps and removed from the specificity analysis. Using the 148 remaining data sets (n = 103 CI532 and n = 45 CI512), the algorithm had an average specificity of 98.6% (95.80%–99.75%). Conclusion: The algorithm was found to be an effective screening tool for the identification of TFOs. Its specificity was within acceptable levels and resulted in a positive predictive value of 76%, with an estimated incidence of fold-over of 4% in perimodiolar arrays. This would mean 3 out of 4 cases flagged as a fold-over would be correctly identified by the algorithm, with the other being a false positive. The measurements were applied easily in theatre allowing it to be used as a routine clinical tool for confirming correct electrode placement.

Free-Space Optical Data Receivers with Avalanche Detectors for Satellite Downlinks Regarding Background Light

Abstract: Data receiving frontends using avalanche photodiodes are used in optical free-space communications for their effective sensitivity, large detection area, and uncomplex operation. Precise control of the high voltage necessary to trigger the avalanche effect inside the photodiode depends on the semiconductor’s excess noise factor, temperature, received signal power, background light, and also the subsequent thermal noise behavior of the transimpedance amplifier. Several prerequisites must be regarded and are explained in this document. We focus on the application of using avalanche photodiodes as data receivers for the on/off-keying of modulated bit streams with a 50% duty cycle. Also, experimental verification of the performance of the receiver with background light is demonstrated.

A 1.8 V Low-Power Low-Noise High Tunable Gain TIA for CMOS Integrated Optoelectronic Biomedical Applications

Abstract: This paper reports on a novel solution for a transimpedance amplifier (TIA) specifically designed as an analog conditioning circuit for low-voltage, low-power, wearable, portable and implantable optoelectronic integrated sensor systems in biomedical applications. The growing use of sensors in all fields of industry, biomedicine, agriculture, environment analysis, workplace security and safety, needs the development of small sensors with a reduced number of electronic components to be easily integrated in the standard CMOS technology. Especially in biomedicine applications, reduced size sensor systems with small power consumption are of paramount importance to make them non-invasive, comfortable tools for patients to be continuously monitored even with personalized therapeutics and/or that can find autonomous level of life using prosthetics. The proposed new TIA architecture has been designed at transistor level in TSMC 0.18 μm standard CMOS technology with the aim to operate with nanoampere input pulsed currents that can be generated, for example, by Si photodiodes in optical sensor systems. The designed solution operates at 1.8 V single supply voltage with a maximum power consumption of about 36.1 μW and provides a high variable gain up to about 124 dBΩ (with fine- and coarse-tuning capabilities) showing wide bandwidth up to about 1.15 MHz and low-noise characteristics with a minimum noise floor level down to about 0.39 pA/Hz. The overall circuit is described in detail, and its main characteristics and performances have been analyzed by performing accurate post-layout simulations.

Analog Front End of 50-Gb/s SiGe BiCMOS Opto-Electrical Receiver in 3-D-Integrated Silicon Photonics Technology

Abstract: This work presents a 3-D-integrated opto-electrical receiver (RX) analog front end (AFE) operating up to 50 Gb/s. The electronic integrated circuit (EIC) is fabricated in ST SiGe BiCMOS-55-nm technology and flipped and mounted on top of the ST photonic integrated circuits (PICs) die through copper pillars (Cu-Pi). In the RX chain, a low-power fully differential shunt-feedback trans-impedance amplifier (FD SF-TIA) is exploited to reduce the input-referred noise. Following the TIA, a postamplifier (PA) based on a novel active feedback circuit topology extends the bandwidth (BW) and a buffer delivers the output electrical signal to the 100- $\Omega $ differential off-chip load. An automatic offset cancellation loop is included to protect the RX from any offset source at the input. The RX AFE consumes 56 mW from 1.8-V supply voltage and provides a trans-impedance (TI) gain of $78.7~\Omega $ with 27-GHz BW. By exploiting the FD SF-TIA with low parasitic capacitance of the germanium photodiodes (Ge-PD) in the photonic die as well as BW recovery by the PA, the RX achieves the sensitivity of −7.5-dBm OMA at Ge-PD and −2.3-dBm OMA at the single-mode fiber (SMF) optical output with bit error rate (BER) of <10 ⁻¹² and PRBS-7. To the author’s best knowledge, among published state-of-the-art 50-Gb/s TIAs and RX exploiting SiGe BiCMOS technologies, this work proves the best energy efficiency ((pJ/bit)) and figure of merit (FoM) ( $({\text {Gbps}}/{\mu \text {A.mW}})$ ) in terms of sensitivity and power consumption.

Overcome the Transimpedance Limit

Abstract: Noise probably the single most important performance metric of the high-speed transimpedance amplifier (TIA), which directly sets the sensitivity of optical receiver. The transimpedance limit which dictates the maximum achievable transimpedance gain of the TIA also turns out to fundamentally limit the TIA noise performance. In this tutorial, we analyze and explore two circuit design approaches to overcome the transimpedance limit. The first approach (Type I) realizes a divide-and-conquer methodology to separate the noise-bandwidth problem and solve them individually. The second approach (Type II) employs a multi-stage stagger-tuned amplifier. Both approaches can overcome the transimpedance limit, forming an effective toolkit for the design of low-noise high-speed TIA for high-sensitivity CMOS optical receivers in current and future applications.

A 58-dBΩ 20-Gb/s inverter-based cascode transimpedance amplifier for optical communications

Abstract: This work presents a high-gain broadband inverter-based cascode transimpedance amplifier fabricated in a 65-nm CMOS process. Multiple bandwidth enhancement techniques, including input bonding wire, input series on-chip inductive peaking and negative capacitance compensation, are adopted to overcome the large off-chip photodiode capacitive loading and the miller capacitance of the input device, achieving an overall bandwidth enhancement ratio of 8.5. The electrical measurement shows TIA achieves 58 dBΩ up to 12.7 GHz with a 180-fF off-chip photodetector. The optical measurement demonstrates a clear open eye of 20 Gb/s. The TIA dissipates 4 mW from a 1.2-V supply voltage.

Chlorophyll Fluorometer for Intelligent Water Sampling by a Small Uncrewed Aircraft System (sUAS)

Abstract: We describe a waterproof, lightweight (1.3 kg), low-power (∼1.1 W average power) fluorometer operating on 5 V direct current deployed on a small uncrewed aircraft system (sUAS) to measure chlorophyll and used for triggering environmental water sampling by the sUAS. The fluorometer uses a 450 nm laser modulated at 10 Hz for excitation and a standard photodiode and transimpedance amplifier for the detection of fluorescence. Additional detectors are available for measuring laser intensity and light scattering. Control of the fluorometer and communication between the fluorometer and the Raspberry Pi 4B computer controlling the sampler were provided by an Arduino microcontroller using the robot operating system (ROS). Calibrations were based on standards of dissolved chlorophyll extracted from Chlorella powder (a widely available dietary supplement). The detection limit for chlorophyll from these calibrations was found to be 0.2 μg per liter of water for a single 0.1 s differential measurement. The detection limit decreases with the square root of the integration time as expected. Detection limits increase by a factor of two to three when mounted in the sUAS due to electrical noise; sUAS acoustic noise and vibration do not appear to contribute significantly. Graphical Abstract

80 dB tuning range transimpedance amplifier exploiting the Switched-Resistor approach

Abstract: This paper presents the design of a low-noise, low-power transimpedance amplifier (TIA) for biomedical applications. The proposed TIA exploits for the first time in the literature a Switched–Resistor (SR) as the feedback element in order to achieve a digitally tunable transimpedance gain with an extremely large tuning range (higher than 80 dB) and a maximum value as high as 10 GΩ. Another important feature which comes with the adoption of the SR technique is that the output voltage is already sampled with the SR clock signal and this simplifies the design of the following digitizer block. The circuit has been designed in a commercial 130 nm CMOS technology and simulation results show a minimum IRCSN (input-referred current spectrum noise) of 1.67 fA/√Hz and a total power consumption of 0.9 μW with a 0.6 V supply voltage. Extensive parametric and Monte Carlo simulations have confirmed a good robustness against PVT and mismatch variations.

Photoplethysmography technology

Abstract: This chapter defines the essential optical and electronic building blocks of a Photoplethysmography (PPG) system and describes their high- and low-level design architecture along with their theory of operation. It starts by presenting the design elements and implementation of a single wavelength PPG system followed by a multiwavelength PPG system. The theoretical considerations and key parameters for optimization of various subcircuits such as the emitter driver, transimpedance amplifier, and sample and hold amplifier are outlined in this chapter. The chapter also provides methods and design flow suggestions to reduce signal artifacts and distortions and increase the PPG signal quality. Finally, the chapter provides a review of the state-of-the-art PPG technology and offers a perspective on the future directions.

A 4 × 4 Biosensor Array With a 42-<i>μ</i>W/Channel Multiplexed Current Sensitive Front-End Featuring 137-dB DR and Zeptomolar Sensitivity

Abstract: This paper presents a multiplexed current sensitive readout for label-free zeptomolar-sensitive detectors realized with large area Electrolyte Gated Organic Thin Film Transistors (EGOFETs). These highly capacitive biosensors are multiplexed using an OTFT line driver and OTFT switches, and interfaced to a 65-nm Si CMOS, low power, pA-sensitive front-end. The Si chip performs analogue-to-digital conversion and data transmission to a microcontroller too. A current domain interface is used to transmit the signals coming from multiple biosensors to the 1.2 V-supply CMOS Si-IC via the 30V-supply OTFT electronics. Exploiting an analogue module implemented in the Si-IC, the EGOFETs are precisely biased, even in presence of a large OTFT multiplexer resistance. The CMOS current sensitive front-end achieves a dynamic range (DR) of 137 dB and a power consumption of 42 lW per channel reaching a state-of-the-art DR-power-bandwidth FOM of 208 dB. The front-end has been designed with a first stage programmable-gain, active-feedback transimpedance amplifier topology that, contrary to common current-sensitive front-end solutions, is not affected by the sensor capacitance. The system has been validated with different concentrations of human IgG and IgM proteins using both a single sensor and a 4x4 array of EGOFETs. Thanks to the multiplexing strategy and the low-costs of its modules, the system here presented has the potential to enable widespread use of precision diagnostic with extreme sensitivity even in point-of-care and low-resource settings.

An Auto Adjustable Transimpedance Readout System for Wearable Healthcare Devices

Abstract: : The objective of this work was to design a versatile readout circuit for patch-type wearable devices consisting of a Transimpedance Amplifier (TIA). The TIA performs Current to Voltage (I–V) conversion, the most widely used technique for amperometry and impedance measurement for various types of electrochemical sensors. The proposed readout circuit employs a digitally controllable feedback resistor ( R f ) technique in the TIA to improve accuracy, which can be utilized in a variety of electrochemical sensors within a current range of 0.1 µ A–100 µ A. It is designed to accommodate multiple sensors simultaneously to track multiple target analytes for high accuracy and versatile usage. The readout circuit consists of low power operational amplifier (op–amp) and digital circuit blocks, is designed and fabricated with Magna 0.18 µ m Complementary Metal Oxide Semiconductor (CMOS) technology, which provides low power consumption and a high degree of integration. The design has a small size of 0.282 mm 2 and low power consumption of 0.38 mW with a 3.3 V power supply, which are desirable factors in wearable device applications.

Threshold Uniformity Improvement in 1b Quanta Image Sensor Readout Circuit

Abstract: A new readout architecture for single-bit quanta image sensor (QIS) consisting of a capacitive transimpedance amplifier (CTIA) before a 1-bit quantizer to improve the threshold uniformity of the readout cluster is proposed in this paper. The 1-bit quantizer in the previous single-bit QIS had significant threshold non-uniformity likely caused by the fluctuation of the common-mode voltage of the jot output. To guarantee the stability of the common-mode voltage of input signals fed to the 1-bit quantizer, the CTIA is added before the 1-bit quantizer. A pipeline operation mode is also proposed so the CTIA and 1-bit ADC can work at the same time, thereby reducing the CTIA power consumption. A 2048 × 1024 high-speed test chip was implemented with 45 nm/65 nm stacked backside illuminated (BSI) CMOS image sensor (CIS) process and tested. According to the measured D-log-H results, a good threshold uniformity in the range of 0.3 to 0.8 e− for all readout clusters is demonstrated at 500 frame per second (fps) equivalent timing with 68 mW power consumption.

A Current Re-Use Quadrature RF Receiver Front-End for Low Power Applications: Blixator Circuit

Abstract: This article presents the theory and implementation of a quadrature and differential RF front-end receiver. Combining balun, low-noise amplifier (LNA), mixer, and oscillator in a single stage, the proposed circuit, named the Blixator, is well suited for low-power applications. The baseband’s transimpedance amplifier (TIA) also shares part of its dc current with the Blixator cell, resulting in sub-milliwatt power consumption. To avoid additional power and area by quadrature LO generation, the I/Q signals are generated at RF, employing the inductors already required for providing the dc current path of the LNA transistors. The expressions for gain, noise figure (NF), and phase noise of the voltage-controlled oscillator (VCO) are derived, and the behavior of the circuit is thoroughly investigated. The prototype of the Blixator receiver is implemented in a 0.18- $\mu \text{m}$ CMOS technology. The experimental results show a NF of 10.5 dB, an IIP3 of −15.5 dBm, at the maximum gain, and an image rejection of 23 dB, which meets the requirements for the Bluetooth Low Energy (BLE) standard. The circuit consumes only 340- $\mu \text{W}$ , from a 0.8-V supply, and its die area is 0.75 mm ² .

High-Density Electrical and Optical Assembly for Subminiature VCSEL-Based Optical Engine

Abstract: In this article, we propose a subminiature (10.9 mm $\times56.6$ mm) vertical cavity surface-emitting laser (VCSEL)-based optical engine with a low crosstalk penalty for onboard applications. When applying optical engines to onboard interconnects, ICs [laser drivers and transimpedance amplifiers (TIAs)] and active optical devices (light sources and photodetectors) must be mounted densely to make the footprint as small as possible. It is a concern that such a high-density integration could increase the crosstalk between transmitter (Tx) and receiver (Rx) devices, which could be caused by the supply current difference between the circuit from laser drivers to light source and the circuit from photodetectors to TIAs. In this article, by inserting a gap in the ground electrode, a compact optical engine (less than half of the footprint of quad small form-factor pluggable-double density (QSFP-DD) compliant engines) enabling a 25.78-Gb/s error-free optical transmission is successfully fabricated. We optimize the gap width to decrease the crosstalk while maintaining efficient heat dissipation via the electrode. We compare the characteristics of the fabricated optical engine to the engine with the gap-less ground electrode structure formed in the same compact size. Then, we both theoretically and experimentally confirm a link power budget savings of about 1.8 dB, which is sustained even under high-temperature ( $T_{c} = 70\,\,^{\circ }\text{C}$ ) operation. In addition, to realize further high-density assembly, we also represent a lens-less optical coupling by inserting a 90 ^o -bent graded-index (GI) core polymer waveguide between the optical transmitter and multimode fiber. The transmission performance of the 90 ^o -bent GI-core waveguide is preliminarily evaluated, and we successfully transmit 53.125-Gb/s PAM4 optical signals experimentally.

A Low-Noise High-Gain Broadband Transformer-Based Inverter-Based Transimpedance Amplifier

Abstract: In this paper, a transformer-based bandwidth (BW) extension technique is employed to improve the BW, noise, and silicon area of inverter-based transimpedance amplifiers (TIAs) even when they use inductive peaking. A TIA based on the proposed technique, designed and laid out in a 16-nm FinFET process, demonstrates a 36% increased in BW, a 19% reduction in input-referred noise, and a 57% reduction in silicon area compared to the conventional TIA with inductive peaking. In the proposed TIA architecture, inclusion of a transformer in the forward path compensates partially for the parasitic capacitances of the inverter and relaxes the transimpedance limit of the conventional TIA. The proposed technique also lowers the input-referred current noise spectrum of the TIA. Post-layout in companion with electromagnetic (EM) simulations and statistical analysis are employed to verify the effectiveness of the proposed architecture. Simulation results show that the TIA achieves a transimpedance gain of 58 dB $\Omega $ , a BW of 17.4 GHz, an input-referred noise of 17.4 pA/sqrt (Hz), and an eye-opening of 20 mV at a data-rate of 64 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole TIA chain is expected to consume 19 mW and occupies an active area of 0.023 mm2.

Harnessing the Unique Features of FDSOI CMOS Technology in Fibreoptic, Millimetre-Wave, and Quantum Computing Circuits From 2 K to 400 K

Abstract: Starting with the full characterization of the n- and p-MOSFETs in a 22-nm FDSOI CMOS process from DC and S-parameter measurements over temperature in the 2 K to 400 K range, we develop circuit design guidelines and design methodologies for digital, analog mixed-signal and mm-wave circuit building blocks that take advantage of the unique features of FDSOI transistors enabled by the presence of the back gate and buried oxide. A constant-current–density-to-backgate-voltage-conversion bias circuit, operating across the entire temperature range is demonstrated to optimally bias CMOS inverters in a variety of digital, analog-mixed-signal and mm-wave circuits for different use scenarios that optimize noise, gain, linearity, and/or bandwidth. Measurement data and constant current density design methodologies are used to illustrate the design of transimpedance amplifiers for qubit readout and fibreoptic receivers, broadband switches, mm-wave time-interleaved ADC samplers, large-swing DACs, and power amplifiers.

Ultraviolet-C Photoresponsivity Using Fabricated TiO2 Thin Films and Transimpedance-Amplifier-Based Test Setup

Abstract: We report on fabricated titanium dioxide (TiO2) thin films along with a transimpedance amplifier (TIA) test setup as a photoconductivity detector (sensor) in the ultraviolet-C (UV-C) wavelength region, particularly at 260 nm. TiO2 thin films deposited on high-resistivity undoped silicon-substrate at thicknesses of 100, 500, and 1000 nm exhibited photoresponsivities of 81.6, 55.6, and 19.6 mA/W, respectively, at 30 V bias voltage. Despite improvements in the crystallinity of the thicker films, the decrease in photocurrent, photoconductivity, photoconductance, and photoresponsivity in thicker films is attributed to an increased number of defects. Varying the thickness of the film can, however, be leveraged to control the wavelength response of the detector. Future development of a chip-based portable UV-C detector using TiO2 thin films will open new opportunities for a wide range of applications.

Transceiver circuits for high-baudrate optical interconnects

Abstract: New circuit architectures and technologies for high-speed electronic and photonic integrated circuits are essential to realize optical interconnects with higher symbol rate. As a consequence of the increasing speeds, close integration and co-design of photonic and electronic chips have become a necessity to realize high-performance transceivers with novel packaging approaches. Extensive co-design also enables the design of new electro-optic architectures to create and process optical signals more efficiently. This paper and presentation will illustrate a number of recent developments of application-specific high-speed electro-optic transceiver circuits including e.g. broadband driver amplifiers, transimpedance amplifiers, analog equalizers and multiplexer circuits for signal generation and reception at 100 Gbaud and beyond. The basic concepts and architectures, technological aspects, design challenges and trade-offs will be discussed.

Analysis and Design of Inductorless Transimpedance Amplifier Employing Nested Feedforward Noise-Canceling Amplifiers

Abstract: In this article, we propose a nested feedforward noise canceling (NFF-NC) technique for transimpedance amplifier (TIA) in optical link communication. The proposed technique minimizes the noise voltages due to both the first and second stages of the TIA, which provides substantial improvement in its noise performance over conventional noise canceling (NC) topology. Comprehensive analysis and comparison are performed between two techniques. While not degrading other key performance parameters (e.g., bandwidth, gain, and power consumption), our proposed scheme presents 30% noise reduction compared to conventional scheme. The proposed NC architecture provides the improved stability since NFF-NC scheme inherently presents an additional left half-plane (LHP) zero due to the FF-stage. The loop stability performance is verified over several process corners, temperatures, and voltage variations confirming the detailed analysis in its loop gain and loop parameters. The proposed NFF-NC TIA was implemented in a 65-nm CMOS technology. The implemented TIA consumes 10.1 mW of power from a 1.3-V supply and occupies 0.037 mm ² of core area. The measurement results show that the proposed TIA presents dc transimpedance gain of 56.3 dB $\Omega $ and bandwidth (−3 dB) of 6.5 GHz. An average input-referred noise current density, $\overline {i_{n,\text {in},\text {avg}}}$ , is 15.1 pA/(Hz) ^1/2 over the bandwidth. Eye diagram is also measured with a pseudorandom binary sequence (PRBS) of 2 ⁷ – 1 with the data rate at 8.5 Gb/s.

A 17-mW 0.5–1.5-GHz Bandwidth TIA Based on an Inductor-Stabilized OTA With 35–42-dBm In-Band IIP3

Abstract: A transimpedance amplifier (TIA) is presented for 5G and future mobile standards. The bandwidth of the TIA can be programmed from 500 MHz to 1.5 GHz. The operational transconductance amplifier (OTA) is designed combining feedforward compensation and inductive peaking, to ensure loop stability and obtain high loop gain with low-power dissipation. TSMC 28-nm HPC technology was used to implement a test chip. With a power dissipation of 17 mW, the TIA achieves an in-band IIP3 ranging from 35 to 42 dBm and output integrated noise of 300 $\mu $ Vrms.

CMOS Multi-Frequency Lock-in Sensor for Impedance Spectroscopy in Microbiology Applications

Abstract: This paper presents the design of a CMOS lock-in amplifier (LIA) encapsulated with an impedance sensor for microbial monitoring applications. The custom integrated LIA is designed and fabricated in a 0.18-µm CMOS technology. It includes a fully differential switched-capacitor transimpedance amplifier as the main building block of the lock-in amplifier. In this design, chopper stabilization is used in the capacitive transimpedance amplifier to reduce the noise and improve the sensor's sensitivity. The proposed LIA contains a band-pass filter with 0.88 quality factor to pass signals at selectable center frequencies of 1, 2, 4, and 10 kHz; a programmable gain amplifier, a mixer, and a low-pass filter to extract impedance changes caused by microorganism growth at different frequencies. The transimpedance amplifier has a gain of 54.86 dB, and an input-referred noise of 58 pA/√Hz at 1 kHz. The whole sensor has a sensitivity of 240 mV/nA. It consumes a power of 817.56 µW from a 1.8V power supply and has a total harmonic distortion of -72.7 dB.

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology

Abstract: The Quad transimpedance and limiting amplifier (QTIA) is a 4-channel array optical receiver ASIC, developed using a 65 nm CMOS process. It is configurable between the bit rate of 2.56 Gbps and 10 Gbps per channel. QTIA offers careful matching to both GaAs and InGaAs photodiodes. At this R&D stage, each channel has a different biasing scheme to the photodiode for optimal coupling. A charge pump is implemented in one channel to provide a higher reverse bias voltage, which is especially important to mitigate radiation effects on the photodiodes. The circuit functions of QTIA successfully passed the lab tests with GaAs photodiodes.

Front End Electronics for Radiation Detectors Based on SiC: Application to High Dose per Pulse Charged Particle Beam Current Measurement

Abstract: In high dose per pulse charged particle beams, all online detectors saturate due to ion recombination. It is therefore impossible to count detector pulses separately. Silicon carbide due to its high bandgap, high thermal conductivity, and high displacement energy, is seen as an alternative. Analyzing waveforms in real-time is challenging in terms of bandwidth, measurable energy range, sensor size, data rate. In this context, an Analog Front-End (AFE) was designed for radiation signal processing. It is based on a Transimpedance Amplifier (TIA) and Charge Sensitive Amplifier (CSA) respectively, to analyze the shape of the generated signal. The methodology used to characterize AFE for large detector capacitance is described. The results obtained from simulations, experiments, and measurements in a radiative environment are also presented.