Showing papers on "VHDL published in 1993"

Method and system for creating, deriving and validating structural description of electronic system from higher level, behavior-oriented description, including interactive schematic design and simulation

Abstract: A system for interactive design, synthesis and simulation of an electronic system allowing a user to design a system either by specification of a behavioral model in a high level language such as VHDL or by graphical entry. The user can view full or partial simulation and design results simultaneously, on a single display window. The synthesis process uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is generally a series of transformations operating upon various levels of design representations. At each level, the design can be simulated and reviewed in schematic diagram form. The simulation results can be displayed immediately adjacent to signal lines on the diagram to which they correspond. In one embodiment, design rule violations are processed by an expert system to suggest possible corrections or alterations to the design which will eliminate the design rule violations. Schematic diagram and simulation displays showing those portions of the electronic system and simulated signal patterns which are related to the design rule violations are used to help the user identify and appropriately correct problems in the design.

Automatic Functional Test Generation Using The Extended Finite State Machine Model

Abstract: We present a method of automatic generation of functional vectors for sequential circuits. A high-level description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms the high-level description, in VHDL or C, of a circuit into an extended finite state machine (EFSM) model using which functional vectors are generated. The EFSM model is a generalization of the traditional state machine model. It can be considered as a compact representation of the machine that preserves many nice properties of a traditional state machine. Theoretical background of the EFSM model will be addressed. Our method guarantees that the generated vectors cover every statement in the high-level description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated automatically in a few minutes of CPU time using our prototype system.

VHDL : Programming By Example

Abstract: Table of contents Foreword Preface Acknowledgments Chapter 1: Introduction to VHDL Chapter 2: Behavioral Modeling Chapter 3: Sequential Processing Chapter 4: Data Types Chapter 5: Subprograms and Packages Chapter 6: Predefined Attributes Chapter 7: Configurations Chapter 8: Advanced Topics Chapter 9: Synthesis Chapter 10: VHDL Systems Chapter 11: High Level Design Flow Chapter 12: Top-Level System Design Chapter 13: CPU: Synthesis Description Chapter 14: CPU: RTL Simulation Chapter 15: CPU Design: Synthesis Results Chapter 16: Place and Route Chapter 17: CPU: VITAL Simulation Chapter 18: At Speed Debugging Techniques Appendix A: Standard Logic Package Appendix B: VHDL Reference Tables Appendix C: Reading VHDL BNF Appendix D: VHDL93 Updates Index About the Author

PRISM-II compiler and architecture

Abstract: This paper discusses the architecture and compiler for a general-purpose metamorphic computing platform called PRISM-II. PRISM-II improves the performance of many computationally-intensive tasks by augmenting the functionality of the core processor with new instructions that match the characteristics of targeted applications. In essence, PRISM (processor reconfiguration through instruction set metamorphosis) is a general purpose hardware platform that behaves like an application-specific platform. Two methods for hardware synthesis, one using VHDL Designer and the other using X-BLOX, are presented and synthesis results are compared. >

An integrated multicomponent synthesis environment for MCMs

Abstract: The multicompact synthesis (MSS) integrated design environment for multichip modules (MCMs) is discussed. The MSS environment is centered in VHDL (very-high-speed integrated circuit hardware description language), WAVES (waveform and vector exchange specification), and PDL (performance description language). MSS provides four levels of automated synthesis support all the way from the behavioral level to MCM placement and routing, three levels of simulation support including behavioral, register, and switch levels, and tools for automated test-bench compilation and design validation for all synthesized designs. Three tutorial examples illustrate MSS algorithms and results. The primary example is the Find, which performs a bubble sort followed by binary search. It is used as the running example because it is small. Such small specifications, however, do not require MCMs. Two larger examples, the Move Machine and the Viper Microprocessor, are used to illustrate the results. >

GAUT: An architectural synthesis tool for dedicated signal processors

Abstract: This paper describes a pipeline architecture synthesis tool dedicated to signal processing applications. This approach relies on the use of a design strategy and of a generic architectural model, using optimized control of resources. GAUT takes a VHDL description of an application as input, and generates the optimal structural and functional VHDL description of a dedicated architecture. The results obtained by GAUT are intended for an application in acoustic echo cancellation. >

The Splash 2 processor and applications

Abstract: Splash 2 is an attached parallel processor in which the computing elements are user-programmable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems which exhibit at least modest amounts of temporal or data parallelism. Applications are developed by writing descriptions of algorithms in VHDL, which are then iteratively refined and debugged within a simulator. Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis. The gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module. A C language library and a symbolic debugger comprise the execution environment. The Splash 2 system has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing. >

The Splash 2 software environment

Abstract: Splash 2 is an attached special purpose parallel processor in which the computing elements are user programmable FPGA devices. The architecture of Splash 2 is designed to accelerate the solution of problems which exhibit at least modest amounts of temporal or data parallelism. Applications are developed by writing behavioral descriptions of algorithms in VHDL, which are then iteratively refined and debugged within the Splash 2 simulator. Once an application is determined to be functionally correct in simulation, it is compiled to a gate list and optimized by logic synthesis. The gate list is then mapped onto the FPGA architecture by automatic placement and routing tools to form a loadable FPGA object module. A C language library and a symbolic debugger comprise the execution environment. The Splash 2 system has been shown to be effective on a variety of applications, including text searching, sequence analysis, and image processing. >

Digital circuit design assist system for designing hardware units and software units in a desired digital circuit, and method thereof

Abstract: A digital circuit design assist system is directed to provide a system which independently verifies hardware divided into a plurality of units or the hardware and software, and reduces the design time. The system includes a functional model storage unit 1 for storing functional models in order to design hardware for a desired digital circuit including the hardware alone or the hardware and firmware, and functionally expressing the digital circuit by a hardware description language through a text editor 15 by coding input. Logic synthesis system 2 is provided for converting the functional model to a structural model, structurally expressed by the hardware description language. Structural model storage unit 3 is provided for storing the structural model, and a language model library storage unit 4 is provided for storing language models each expressing each of a plurality of components constituting the hardware by the hardware description language. Hardware description language simulation system 5 is provided for verifying correctness of the logic of the hardware from the functional model, the structural model and the language model.

The Siemens high-level synthesis system CALLAS

Abstract: In this paper we present the Siemens high-level synthesis system CALLAS and describe its design methodology and synthesis strategy It supports the synthesis of control-dominated applications and uses a VHDL subset for the algorithmic specification Its main feature can be characterized as "What you simulate is what you synthesize" This principle permits a validation of the synthesis results by simulation or even formal verification CALLAS has been successfully applied on real designs which were implemented in silicon These examples demonstrate that CALLAS fulfils the constraints and objectives of a hardware designer The circuits are comparable in quality to results achieved by synthesis starting at the register-transfer-level >

FPGA computing in a data parallel C

Abstract: The authors demonstrate a new technique for automatically synthesizing digital logic from a high level algorithmic description in a data parallel language. The methodology has been implemented using the Splash 2 reconfigurable logic arrays for programs written in Data-parallel Bit-serial C (dbC). The translator generates a VHDL description of a SIMD processor array with one or more processors per Xilinx 4010 FPGA. The instruction set of each processor is customized to the dbC program being processed. In addition to the usual arithmetic operations, nearest neighbor communication, host-to-processor communication, and global reductions are supported. >

Structured Logic Design With Vhdl

Abstract: 1. Structured Design Concepts 2. Design Tools 3. Basic Features of VHDL 4. Basic VHDL Modeling Techniques 5. Algorithmic Level Design 6. Data Flow Level Design 7. Detailed Gate Level Design 8. Multi-Level Design 9. Algorithmic Synthesis

AMICAL: An interactive high level synthesis environment

Abstract: The AMICAL architectural synthesis system starts with a behavioral specification given in VHDL, performs both scheduling and allocation, and generates a structural description that may feed existing silicon compilers acting at the logic and RT levels. All the synthesis algorithms are implemented as part of an interactive synthesis environment, where automatic and manual design may be mixed. Experiments have shown that the use of AMICAL leads to the best known solutions for most benchmarks. These solutions may be obtained by mixing automatic and manual design or by the use of an automatic exploration of the design space. The response time of AMICAL is reasonably short making it a genuine interactive system. >

Integrating SDL and VHDL for System-Level Hardware Design

Abstract: SDL is a CCITT standard for the specification of distributed software systems. It is widely used mainly in the telecommunication area. Although one goal during the development of SDL was to support the specification and description of communication systems consisting of both hardware and software, SDL is mainly used in the software design process today. One reason why SDL did not gain acceptance among hardware designers might be the big gap between specification and hardware implementation. In the software domain code generators for several programming languages, e.g., CHILL, C, C++, or PASCAL have been made available to close the gap between design and implementation. Similar tools for hardware are missing so far. This paper describes the application of SDL to system-level design of hardware. A translation of SDL descriptions into the standard hardware description language VHDL is presented. This translation allows one to implement SDL descriptions in hardware with state-of-the-art synthesis tools.

Insulin: An Instruction Set Simulation Environment

Abstract: We present Insulin, a new environment for the simulation of user-defined, application-specific programmable processors (ASPP). This environment is based on a reconfigurable VHDL model of a generic instruction set processor. The environment supports parallel instruction streams, cycle true simulation, arbitrary addressing modes, multi-cycle instructions, pipelining and user specified memory, register file and stack sizes. In our approach, the behavior of a user-defined instruction set (I/S) is expressed in terms of the generic instructions supported by the VHDL model. From this I/S definition, the tool automatically generates a cross-assembler which converts application-specific assembly code to the generic assembly code, which can be simulated. A graphic interface allows the user to interact with the model at the suitable level during the simulation. Insulin is part of an overall ASPP design environment at BNR which includes a retargetable code generator.

Using VHDL for HW/SW co-specification

Abstract: HW/SW (hardware/software) co-specification and co-design require a medium for HW/SW implementation independent description as well as for integration of hardware and software. Since not all design steps can be performed automatically, this medium must be capable of representing results of intermediate design steps from both CAD tools and human interaction. VHDL is widely accepted in HW design where it is mostly used at the RT level. VHDL implementations of abstract data and control structures which support clock independent communication and synchronization allow one to extend VHDL toward system level and HW/SW co-design. >

Fundamentals and standards in hardware description languages

Abstract: Part I: Fundamentals. Fundamentals of Hardware Description Languages and Declarative Languages R. Boute. CONLAN: Presentation of Basic Principles, Applications and Relation to VHDL D. Borrione, R. Piloty. Logic and Arithmetic in Hardware Description Languages A. Zamfirescu. System Level Design F.J. Rammig. Part II: Applications to Formal Proofs, High Level Synthesis, Multilevel Simulation and Hierarchical Testing. Formal Proofs from HDL Descriptions D. Borrione, H. Eveking, L. Pierre. High-Level Synthesis in a Production Environment: Methodology and Algorithms R.A. Bergamaschi. Synthesis Applications of VHDL E. Villar, P. Sanchez. HDL-Driven Digital Simulation A. Stanculescu. Analog and Mixed-Level Simulation with Implications to VHDL A. Vachoux, K. Nolan. Rapid Development and Testing of Behavioral Models J.R. Armstrong, A. Honcharik. Part III: Introduction to Hardware Description Languages Implemented in the '80s. VHDL P.J. Menchini. ELLA J.D. Morison, C.O. Newton. DACAPO III F.J. Rammig. CASCADE D. Borrione. REGLAN R. Piloty. KARL and ABL R. Hartenstein.

Hierarchical test generation for VHDL behavioral models

Abstract: In this method, the VHDL model to be tested is represented by its process model graph (PMG). Test sets for individual processes of the model are precomputed and stored in the design library. The Hierarchical Behavioral Test Generator (HBTG) algorithm accepts the PMG and the precomputed tests as inputs, from which it hierarchically constructs a test sequence that tests the functionality of the model. Such an automatic test generation process relieves the modeler of the time-consuming task of developing test-benches. The test sequence generated by HBTG is then used for simulation of the model. Experimental results indicate that the tests generated exercise the model thoroughly. >

Toward a formal semantics of IEEE Std. VHDL 1076

Abstract: The need for a formal interpretation of VHDL is addressed. The formal model used for this purpose is colored Petri nets because they can cover all aspects of VHDL. The authors start from the underlying executable model of VHDL based on communicating processes. The formal model of a VHDL description results from the specification in Petri net terms of the user-defined processes, the kernel process (VHDL simulator), and the communicating links between them. This approach can also be applied to other HDLs with the same underlying paradigm. >

One-hot state machine design for FPGAs

Abstract: One-hot state machines use one flop per state. They are particularly suited to today's register- rich FPGA architectures. This paper will discuss the advantages of one-hot state machines including ease of design, simple timing analysis, and high clock rates. An SBus master/slave interface will be used as a design example. VHDL and Verilog coding styles will be discussed.

A deinterlacer for IQTV receivers and multimedia applications

Abstract: A deinterlacer suitable for IQTV receivers and multimedia applications is presented. The processing is based on a hierarchical motion adaptive filtering. The proposed method effectively copes with the motion present in the scene: it performs a local interpolation using data lying along an estimated direction of motion. The algorithm is synthesized using VHDL (VHSIC Hardware Description Language) into FPGA (field-programmable gate array) components and in a single programmable ASIC (application-specific integrated circuit). >

Features supporting system-level specification in HDLs

Abstract: As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems. >

Soft-output Viterbi decoding: VLSI implementation issues

Abstract: The soft-output Viterbi algorithm (SOVA) is a decoding algorithm which uses soft quantized inputs and delivers soft decision outputs. Implementation parameter effects in SOVA decoding that are related to considerable variations in area consumption of VLSI implementations are considered, i.e., the quantization of the reliability values inside the survivor memory unit, the depth of reliability updating, and the effect of a simplified update rule on the reliability values. Results of extensive simulations are presented. Area estimates obtained by logic synthesis from VHSIC hardware description language (VHDL) descriptions are given to show how these parameters translate into the area consumption of VLSI implementations.

DLS: A scheduling algorithm for high-level synthesis in VHDL

Abstract: Dynamic loop scheduling, an algorithm that can efficiently schedule large, control-flow dominated designs, written in VHDL is presented. It compares favorably with results produced by other control-flow oriented approaches such as path-based scheduling, but avoids the path explosion problem. In addition, the VHDL accepted by the scheduler is quite comprehensive, including nested branches, loops (whose conditions can be compounded), loop exit statements and procedure calls. The algorithm forms an integral part of the AMICAL data-path compiler. >

A net-based semantics for VHDL

Abstract: The VHDL standard gives only an informal description of the semantics of VHDL. To apply formal verification techniques, a precise semantics definition is necessary. A formal semantics for VHDL based on interpreted Petri nets is defined. The presented semantics is compositional and provides a link to automatic verification methods for VHDL based designs. >

A reconfigurable and flexible parallel 3D vision system for a mobile robot

Abstract: The experiment results show that a high performance low cost system may be obtained by adapting algorithms and hardware to each other especially for the vision system. Thus configurable and flexible parallel architecture are the key concepts to design vision system. In addition the configurable and flexible parallel vision system provides a platform for developing application and experimenting with high level image processing algorithms. FPGA board permits one to explore low level image processing and high level image processing accelerator. With VHDL language, the system permits also to narrow the gap between software developer and hardware designer.

High-level modeling using extended timing diagrams - A formalism for the behavioral specification of digital hardware

Abstract: The principles of high level modeling of digital hardware circuits using the extended timing diagrams (ETD) formalism, which adds conditions, events, action expressions, and particular constraints to traditional timing diagrams, are described. Hierarchy and concurrency are also integrated so that a full top-down design becomes possible, enhancing at the same time the readability. While, for simulation purposes, the implementation of the formalism generates behavioral VHDL (VHSIC Hardware Description Language) models, a dedicated high-level translator generates VHDL code for synthesis. Both the ETD formalism and its implementation are part of MODES, a more complex modeling expert system including complementary editors. >

Teaching computer hardware design using commercial CAD tools

Abstract: A project currently being implemented that is aimed at significantly enhancing the computer hardware design experience provided to undergraduate students through the use of industrial-grade CAD tools is discussed. A set of tools has been carefully chosen that can be used in a sequence of courses. The tool set is versatile and flexible and enables a designer to use different tools for different portions of a system design and then integrate the various parts together and simulate the overall system. Besides teaching logic design using MSI TTL components, instructors are able to use CAD tools for designing with PLDs, describing modules in VHDL, developing microcode, and designing microprocessor-based systems. >