A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme achieves high-speed and low-power operation thanks to the reference-free technique that avoids the static power dissipation of an on-chip reference generator. Moreover, the use of a common-mode based charge recovery switching method reduces the switching energy and improves the conversion linearity. A variable self-timed loop optimizes the reset time of the preamplifier to improve the conversion speed. Measurement results on a 90 nm CMOS prototype operated at 1.2 V supply show 3 mW total power consumption with a peak SNDR of 56.6 dB and a FOM of 77 fJ/conv-step.

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A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115×225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step.

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A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$ W at 1 MS/s

Rapid growth in the demand for “Green-IT” or medical applications requires power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]. Split capacitor digital-to-analog converter (CDAC) is one of the best architectures for high resolution SAR ADC, but is very sensitive to the splitting capacitor because of its fractional value and parasitic. Conventional SAR ADC needs approximately 10 times faster external clock if it has no internal clock generator. However the internal SAR clock generation enables the external clock frequency to be the same as the sampling rate, but suffers from unstable operation caused by large PVT delay variation. This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The ADC is integrated in 65nm CMOS and achieved 10b at 50MS/s while consuming 820µW from a 1.0V supply.

A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm2 chip was fabricated in a standard 0.16 μm CMOS process.

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A 6.3 µW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 µV Offset

In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For pipelined operation, a novel time-register is proposed which is capable of storing, adding and subtracting time information with a clock signal. Together with a pulse-train time-amplifier, a 9-bit synchronous pipelined TDC is implemented, which consists of three 2.5 b/stage TDCs and a 3 b delay-line TDC. A prototype chip fabricated in 65 nm CMOS process achieves 1.12 ps of time resolution at 250 MS/s while consuming 15.4 mW. Compared to other high-resolution state-of-the-art TDCs, the proposed pipelined TDC achieves the best figure-of-merit (FoM) without any calibration.

A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register

The ADC-SAR is fabricated in a 0.18mum 2P5M CMOS process. This SAR-ADC converter achieves 56fJ/conversion-step FOM with 58dB SNDR. It uses a comparator, named time-domain comparator, that instead of operating in the voltage domain, transforms the input and the reference voltages into pulses and compares their duration.

/pdf/a-9-4-enob-1v-3-8mw-100ks-s-sar-adc-with-time-domain-3dv3etfcj7.pdf

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator

This paper presents an ultra-low power successive approximation analog-to-digital converter. An improved implementation of the binary weighted capacitors array and a novel comparator that operates in the time instead of the voltage domain are effective and power efficient. The circuit, fabricated in a conventional 0.18-μm CMOS technology, achieves a sampling rate of 100 kS/s and an effective number of bit of 9.4. Using a 1-V supply voltage, the achieved power consumption is 3.8 μW, leading to a Figure of Merit as low as 56 fJ/conversion-level.

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An ultra-low power successive approximation A/D converter with time---domain comparator

Design strategies for power effective medium/high resolution Successive-Approximation ADC are discussed. The study considers reducing the power of the capacitive array with suitable capacitive attenuators that do not need using non-unity capacitors. The design of minimum power comparators is analyzed and a novel comparator scheme, named time-domain comparator, is described. The proposed methodologies, verified with a test design, is capable to provide 12-bit with 50-kHz signal band and 1-V supply. The achieved FoM is 14 fj/conv-level, which is well below the state-of-the-art.

/pdf/design-of-an-ultra-low-power-sa-adc-with-medium-high-5osirvtrcx.pdf

Design of an ultra-low power SA-ADC with medium/high resolution and speed

This paper describes an incremental converter based on a second order ΣΔ modulator. The scheme uses a 3-bit DAC with inherent linearity, an optimal reset of integrators, and gives rise to an effective offset cancellation with a novel technique based on single or double chopping. The circuit, fabricated in a mixed 0.18-0.6 μm CMOS technology, obtains 1.5-μV residual offset with 2VPP fully differential range. The measured resolution is 19 bit obtained with 512 clock periods.

/pdf/high-resolution-multi-bit-second-order-incremental-converter-37j2gp0z1d.pdf

High-resolution multi-bit second-order incremental converter with 1.5-μV residual offset and 94-dB SFDR

In this brief, a theoretical analysis on the limits of conventional chopper stabilization technique is presented and a solution conceived to improve the amplifier performance is proposed. The expected replicas of the 1/f noise at the chopping frequency and its multiples are attenuated by a modified chopping control. Simulations done by using records of real 1/f noise outputs showed that, by following the proposed approach, the spectrum of the signal is not affected while the 1/f replicas are reduced by more than 40 dB with respect to conventional techniques. The required circuit for the generation of the chopping signal is also described. The resulting overhead with respect to conventional techniques is negligible and fully acceptable.

A. Agnes

Papers

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator

An ultra-low power successive approximation A/D converter with time---domain comparator

Design of an ultra-low power SA-ADC with medium/high resolution and speed

High-resolution multi-bit second-order incremental converter with 1.5-μV residual offset and 94-dB SFDR

Cancellation of Amplifier Offset and $1/{f}$ Noise: An Improved Chopper Stabilized Technique