Two-dimensional crystals are emerging materials for nanoelectronics. Development of the field requires candidate systems with both a high carrier mobility and, in contrast to graphene, a sufficiently large electronic bandgap. Here we present a detailed theoretical investigation of the atomic and electronic structure of few-layer black phosphorus (BP) to predict its electrical and optical properties. This system has a direct bandgap, tunable from 1.51 eV for a monolayer to 0.59 eV for a five-layer sample. We predict that the mobilities are hole-dominated, rather high and highly anisotropic. The monolayer is exceptional in having an extremely high hole mobility (of order 10,000 cm(2) V(-1) s(-1)) and anomalous elastic properties which reverse the anisotropy. Light absorption spectra indicate linear dichroism between perpendicular in-plane directions, which allows optical determination of the crystalline orientation and optical activation of the anisotropic transport properties. These results make few-layer BP a promising candidate for future electronics.

/pdf/high-mobility-transport-anisotropy-and-linear-dichroism-in-hvrytks3d2.pdf

High-mobility transport anisotropy and linear dichroism in few-layer black phosphorus

The scaling of complementary metal oxide semiconductor transistors has led to the silicon dioxide layer, used as a gate dielectric, being so thin (14?nm) that its leakage current is too large It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (?) or 'high K' gate oxides such as hafnium oxide and hafnium silicate These oxides had not been extensively studied like SiO2, and they were found to have inferior properties compared with SiO2, such as a tendency to crystallize and a high density of electronic defects Intensive research was needed to develop these oxides as high quality electronic materials This review covers both scientific and technological issues?the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure and reactions, their electronic structure, bonding, band offsets, electronic defects, charge trapping and conduction mechanisms, mobility degradation and flat band voltage shifts The oxygen vacancy is the dominant electron trap It is turning out that the oxides must be implemented in conjunction with metal gate electrodes, the development of which is further behind Issues about work function control in metal gate electrodes are discussed

https://iopscience.iop.org/article/10.1088/0034-4885/69/2/R02/pdf

High dielectric constant gate oxides for metal oxide Si transistors

The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin (1.4 nm) that its leakage current is too large. It is necessary to replace the SiO2 with a physically thicker layer of oxides of higher dielectric constant (κ) or 'high K' gate oxides such as hafnium oxide and hafnium silicate. Little was known about such oxides, and it was soon found that in many respects they have inferior electronic properties to SiO2 ,s uch as a tendency to crystallise and a high concentration of electronic defects. Intensive research is underway to develop these oxides into new high quality electronic materials. This review covers the choice of oxides, their structural and metallurgical behaviour, atomic diffusion, their deposition, interface structure and reactions, their electronic structure, bonding, band offsets, mobility degradation, flat band voltage shifts and electronic defects. The use of high K oxides in capacitors of dynamic random access memories is also covered.

/pdf/high-dielectric-constant-oxides-cotu2e70vd.pdf

High dielectric constant oxides

Newly fabricated few-layer black phosphorus and its monolayer structure, phosphorene, are expected to be promising for electronic and optical applications because of their finite direct band gaps and sizable but anisotropic electronic mobility. By first-principles simulations, we show that this unique anisotropic free-carrier mobility can be controlled by using simple strain conditions. With the appropriate biaxial or uniaxial strain (4–6%), we can rotate the preferred conducting direction by 90°. This will be useful for exploring unusual quantum Hall effects and exotic electronic and mechanical applications based on phosphorene.

Strain-Engineering the Anisotropic Electrical Conductance of Few-Layer Black Phosphorus

Defects usually play an important role in tailoring various properties of two-dimensional materials. Defects in two-dimensional monolayer molybdenum disulphide may be responsible for large variation of electric and optical properties. Here we present a comprehensive joint experiment–theory investigation of point defects in monolayer molybdenum disulphide prepared by mechanical exfoliation, physical and chemical vapour deposition. Defect species are systematically identified and their concentrations determined by aberration-corrected scanning transmission electron microscopy, and also studied by ab-initio calculation. Defect density up to 3.5 × 1013 cm−2 is found and the dominant category of defects changes from sulphur vacancy in mechanical exfoliation and chemical vapour deposition samples to molybdenum antisite in physical vapour deposition samples. Influence of defects on electronic structure and charge-carrier mobility are predicted by calculation and observed by electric transport measurement. In light of these results, the growth of ultra-high-quality monolayer molybdenum disulphide appears a primary task for the community pursuing high-performance electronic devices. Imperfections can greatly alter a material’s properties. Here, the authors investigate the influence of point defects on the electronic structure, charge-carrier mobility and optical absorption of molybdenum disulphide prepared by mechanical exfoliation, physical and chemical vapour deposition.

/pdf/exploring-atomic-defects-in-molybdenum-disulphide-monolayers-2eluwhglkk.pdf

Exploring atomic defects in molybdenum disulphide monolayers

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFET's with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFET's degraded by Fowler-Nordheim electron injection. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20I%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

For part I see ibid., vol.41, no.12, pp.2357-62 (1994). This paper reports the studies of the inversion layer mobilities in n-channel MOSFET's fabricated on Si wafers with three surface orientations ([100], [110], and [111]) from the viewpoint of the universal relationship against the effective field, E/sub eff/(=q(N/sub dpl/+/spl eta//spl middot/N/sub s/)//spl epsi/Si). It is found that the universality does hold for the electron mobilities on [110] and [111], when the value of /spl eta/ is taken to be 1/3, different from the electron mobility on [100], where /spl eta/ is 1/2. Also, the E/sub eff/ dependence of the electron mobility is found to differ among [100], [110], and [111] surfaces. This is attributed to the differences in the E/sub eff/ dependence of the mobility limited by surface roughness scattering among the orientations. The origins of E/sub eff/ and /spl eta/ are discussed on the basis of the relaxation time approximation for a 2DEG (2-dimensional electron gas). While the surface orientation dependence of /spl eta/ in phonon scattering can be understood in terms of the subband occupation, it is found that the theoretical formulation of surface roughness scattering, used currently, needs to be refined in order to explain the differences in E/sub eff/ dependence and the value of /spl eta/ among the three orientations. >

https://www-inst.eecs.berkeley.edu/~ee230/sp08/takagi%20universal%20mobility%20II%201994.pdf

On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer.

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

We propose a new experimental technique to study the transport properties of stress-induced leakage current (SILC). Based on the carrier separation measurement for p-channel MOSFETs, the quantum yield of impact ionization for electrons involved in the SILC process is evaluated directly from the change in the source and gate currents of p-MOSFETs before and after stressing. Since the relationship between the electron energy and the quantum yield is established for direct and FN tunneling currents, the electron energy of electrons involved in the SILC process can be determined from the quantum yield. The results reveal that the measured energy of electrons in the SILC process is lower roughly by 1.5 eV than the energy expected in the elastic tunneling process. Trap-assisted inelastic tunneling model is proposed as a conduction mechanism of SILC accompanied by energy relaxation. It is shown, through the evaluation of the substrate hole current in n-channel MOSFETs, that the contribution of trap-assisted valence electron tunneling, another possible mechanism to explain the energy relaxation, to SILC is small.

Experimental evidence of inelastic tunneling in stress-induced leakage current

The inversion-layer capacitance (C/sub inv/) in n-channel Si MOSFET's is studied experimentally and theoretically with emphasis on the surface carrier concentration (N/sub s/) dependence of C/sub inv/, which is important in the quantitative description of the inversion-layer capacitance Based on the experimental N/sub s/ and temperature dependencies, the physical origin of C/sub inv/ is discussed It is shown that, at lower N/sub s/, C/sub inv/ is determined by the finite effective density of states, while, at higher N/sub s/ C/sub inv/ is determined quantum mechanically by the finite inversion-layer thickness Also, the results of the surface orientation dependence of C/sub inv/ are presented as the first direct evidence for the fact that surface quantization plays a significant role in C/sub inv/ even at room temperature The self-consistent Poisson-Schrodinger calculation of C/sub inv/ is performed and found to represent the experimental results accurately The influence of C/sub inv/ on the gate capacitance is discussed in terms of the device scaling on basis of the experimental and calculated values of C/sub inv/

A. Toriumi

Papers

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

Experimental evidence of inelastic tunneling in stress-induced leakage current

Quantitative understanding of inversion-layer capacitance in Si MOSFET's