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Azita Emami-Neyestanak
Researcher at California Institute of Technology
Publications - 29
Citations - 1060
Azita Emami-Neyestanak is an academic researcher from California Institute of Technology. The author has contributed to research in topics: CMOS & Low-power electronics. The author has an hindex of 14, co-authored 26 publications receiving 957 citations. Previous affiliations of Azita Emami-Neyestanak include Columbia University.
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Journal ArticleDOI
A Nonuniform Sampler for Wideband Spectrally-Sparse Environments
Michael B. Wakin,Stephen Becker,E. B. Nakamura,Michael C. Grant,Emilio A. Sovero,D. Ching,Juhwan Yoo,Justin Romberg,Azita Emami-Neyestanak,Emmanuel J. Candès +9 more
TL;DR: A wide bandwidth, compressed sensing based nonuniform sampling (NUS) system with a custom sample-and-hold chip designed to take advantage of a low average sampling rate is presented.
Journal ArticleDOI
A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects
TL;DR: This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption and high-precision phase spacing at both the transmitter and receiver.
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A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition
Juhwan Yoo,C. Turnes,E. B. Nakamura,C. K. Le,Stephen Becker,Emilio A. Sovero,Michael B. Wakin,Michael C. Grant,Justin Romberg,Azita Emami-Neyestanak,Emmanuel J. Candès +10 more
TL;DR: A complete (hardware/ software) sub-Nyquist rate (× 13) wideband signal acquisition chain capable of acquiring radar pulse parameters in an instantaneous bandwidth spanning 100 MHz-2.5 GHz with the equivalent of 8 effective number of bits (ENOB) digitizing performance is presented.
Journal ArticleDOI
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE
Azita Emami-Neyestanak,A. Varzaghani,John F. Bulzacchelli,Alexander V. Rylyakov,Chih-Kong Ken Yang,Daniel J. Friedman +5 more
TL;DR: A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology and the signaling rate with BER<10-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces.
Journal ArticleDOI
Energy-Efficient Classification for Resource-Constrained Biomedical Applications
Mahsa Shoaran,Benyamin Allahgholizadeh Haghi,Milad Taghavi,Masoud Farivar,Azita Emami-Neyestanak +4 more
TL;DR: This work proposes an efficient hardware architecture to implement gradient boosted trees in applications under stringent power, area, and delay constraints, such as medical devices, and introduces the concepts of asynchronous tree operation and sequential feature extraction to achieve an unprecedented energy and area efficiency.