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Bernd Tillack
Researcher at Innovations for High Performance Microelectronics
Publications - 232
Citations - 3920
Bernd Tillack is an academic researcher from Innovations for High Performance Microelectronics. The author has contributed to research in topics: BiCMOS & Heterojunction bipolar transistor. The author has an hindex of 29, co-authored 220 publications receiving 3632 citations. Previous affiliations of Bernd Tillack include Leibniz Institute for Neurobiology & Korea University.
Papers
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Proceedings ArticleDOI
A 0.13µm SiGe BiCMOS technology featuring f T /f max of 240/330 GHz and gate delays below 3 ps
Holger Rucker,Bernd Heinemann,Wolfgang Winkler,R. Barth,J. Borngraber,J. Drews,G. G. Fischer,A. Fox,Thomas Grabolla,U. Haak,D. Knoll,F. Korndorfer,Andreas Mai,Steffen Marschmeyer,Peter Schley,D. Schmidt,J. Schmidt,K. Schulz,Bernd Tillack,D. Wolansky,Yuji Yamamoto +20 more
TL;DR: In this paper, a 0.13 µm SiGe BiCMOS technology for millimeter wave applications is presented, which features high-speed HBTs (f T =240 GHz, f max =330 GHz, BV CEO =1.7 V) along with high-voltage high-frequency HBT (fT =50 GHz, F max =130 GHz, BS CEO =3.7V) integrated in a dual-gate, triple-well RF-CMOS process.
Journal ArticleDOI
A D-Band Micromachined End-Fire Antenna in 130-nm SiGe BiCMOS Technology
Wasif Tanveer Khan,A. Cagri Ulusoy,Gaëtan Dufour,Mehmet Kaynak,Bernd Tillack,John D. Cressler,John Papapolymerou +6 more
TL;DR: In this article, the design of a radiation-efficient D-band end-fire on-chip antenna utilizing a localized back-side etching (LBE) technique, as well as an antenna-in-package (AiP) on a low-cost organic substrate, is presented.
Proceedings ArticleDOI
SiGe:C BiCMOS technology with 3.6 ps gate delay
H. Rucker,Bernd Heinemann,R. Barth,D. Bolze,J. Drews,Ulrich Haak,W. Hoppner,D. Knoll,K. Kopke,Steffen Marschmeyer,Harald H. Richter,Peter Schley,D. Schmidt,R. Scholz,Bernd Tillack,Wolfgang Winkler,H.-E. Wulf,Yuji Yamamoto +17 more
TL;DR: In this article, a high-speed SiGe:C HBT is presented that combines a new extrinsic base construction with a low-resistance collector design to simultaneously minimize base and collector resistances and base collector capacitance.
Patent
Layers in substrate wafers
TL;DR: In this paper, the authors proposed to provide layers in substrate wafers with which the drawbacks of conventional assemblies are overcome in order to achieve an adequate resistance to latch-up in highly scaled, digital CMOS circuits with comparatively low costs and, on the other hand, to ensure low substrate losses/couplings for analog high-frequency circuits and, in addition, to influence the component behavior in a nondestructive manner.
Journal ArticleDOI
A 0.8 THz $f_{\rm MAX}$ SiGe HBT Operating at 4.3 K
Partha S. Chakraborty,Adilson S. Cardoso,Brian R. Wier,Anup P. Omprakash,John D. Cressler,Mehmet Kaynak,Bernd Tillack +6 more
TL;DR: In this paper, the authors demonstrate record ac performance (0.8 THz) for a silicon-germanium heterojunction bipolar transistor (SiGe HBT) operating at cryogenic temperatures.