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Blaise Ravelo
Researcher at Nanjing University of Information Science and Technology
Publications - 233
Citations - 2399
Blaise Ravelo is an academic researcher from Nanjing University of Information Science and Technology. The author has contributed to research in topics: Group delay and phase delay & Microstrip. The author has an hindex of 21, co-authored 196 publications receiving 1727 citations. Previous affiliations of Blaise Ravelo include École Supérieure d'Ingénieurs en Génie Électrique & Nanjing University.
Papers
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The Design Method of the Active Negative Group Delay Circuits Based on a Microwave Amplifier and an RL-Series Network
TL;DR: This paper addresses a circuit theory regarding the negative group delay (NGD) principle and the methodology for characterizing this unfamiliar NGD function is described, with results in good agreement with the theoretical prediction obtained with simple lumped circuits.
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Magneto-dielectric properties of doped ferrite based nanosized ceramics over very high frequency range
TL;DR: In this paper, indium doped nano sized nickel zinc cobalt based ferrite ceramics with composition Ni 0.5 Zn 0.3 Co 0.4 Fe 1.6 O 4 were synthesized by a co-precipitation technique.
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Time-Domain Experimentation of NGD ActiveRC-Network Cell
TL;DR: A theoretical and experimental investigation of low-pass negative group delay (NGD) topology, composed of a low noise amplifier and RC-parallel series mounted lumped network, finds results in good agreement with the circuit theory.
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Design of Multi-Scale Negative Group Delay Circuit for Sensors Signal Time-Delay Cancellation
TL;DR: The developed NGD time-delay cancellation demonstrations open the potential applications for the sensor performance improvement and the synthesis equations enabling to calculate the NGD cell parameters as a function of the desired NGD and gain are formulated.
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Negative Group-Delay Phenomenon Analysis With Distributed Parallel Interconnect Line
TL;DR: In this paper, an original theory on negative group-delay (NGD) topology of parallel interconnect line (PIL) was described, which consists of a fully distributed circuit without lossy lumped components.