Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

/pdf/mos2-transistors-with-1-nanometer-gate-lengths-389j9ig3a6.pdf

MoS2 transistors with 1-nanometer gate lengths

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Rise of silicene: A competitive 2D material

During the past decade, two-dimensional materials have attracted incredible interest from the electronic device community The first two-dimensional material studied in detail was graphene and, since 2007, it has intensively been explored as a material for electronic devices, in particular, transistors While graphene transistors are still on the agenda, researchers have extended their work to two-dimensional materials beyond graphene and the number of two-dimensional materials under examination has literally exploded recently Meanwhile several hundreds of different two-dimensional materials are known, a substantial part of them is considered useful for transistors, and experimental transistors with channels of different two-dimensional materials have been demonstrated In spite of the rapid progress in the field, the prospects of two-dimensional transistors still remain vague and optimistic opinions face rather reserved assessments The intention of the present paper is to shed more light on the merits and drawbacks of two-dimensional materials for transistor electronics and to add a few more facets to the ongoing discussion on the prospects of two-dimensional transistors To this end, we compose a wish list of properties for a good transistor channel material and examine to what extent the two-dimensional materials fulfill the criteria of the list The state-of-the-art two-dimensional transistors are reviewed and a balanced view of both the pros and cons of these devices is provided

/pdf/two-dimensional-materials-and-their-prospects-in-transistor-22htc6r9e0.pdf

Two-dimensional materials and their prospects in transistor electronics

Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.

Junctionless nanowire transistor (JNT): Properties and design guidelines

All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Nanowire transistors without junctions

We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.

SOI gated resistor: CMOS without junctions

Characterisation of a novel electron beam lithography resist, SML and its comparison to PMMA and ZEP resists

The authors investigate the templated crystallization of thin-body Ge fin structures with high aspect ratios. Experimental variables include fin thickness and thermal treatments, with fin structures oriented in the 〈110〉 direction. Transmission electron microscopy determined that various crystal defects form during crystallization of amorphous Ge regions, most notably {111} stacking faults, twin boundaries, and small crystallites. In all cases, the nature of the defects is dependent on the fin thickness and thermal treatments applied. Using a standard 600 °C rapid-thermal-anneal, Ge structures with high aspect ratios crystallize with better crystal quality and fewer uncured defects than the equivalent Si case, which is a cause for optimism for thin-film Ge devices.

/pdf/the-curious-case-of-thin-body-ge-crystallization-ba11ou07wx.pdf

The curious case of thin-body Ge crystallization

Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU.

https://iopscience.iop.org/article/10.1088/0957-4484/25/35/355301/pdf

Brendan McCarthy

Papers

Nanowire transistors without junctions

SOI gated resistor: CMOS without junctions

Characterisation of a novel electron beam lithography resist, SML and its comparison to PMMA and ZEP resists

The curious case of thin-body Ge crystallization

High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask.