Scaling of silicon (Si) transistors is predicted to fail below 5-nanometer (nm) gate lengths because of severe short channel effects. As an alternative to Si, certain layered semiconductors are attractive for their atomically uniform thickness down to a monolayer, lower dielectric constants, larger band gaps, and heavier carrier effective mass. Here, we demonstrate molybdenum disulfide (MoS2) transistors with a 1-nm physical gate length using a single-walled carbon nanotube as the gate electrode. These ultrashort devices exhibit excellent switching characteristics with near ideal subthreshold swing of ~65 millivolts per decade and an On/Off current ratio of ~106 Simulations show an effective channel length of ~3.9 nm in the Off state and ~1 nm in the On state.

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MoS2 transistors with 1-nanometer gate lengths

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

Rise of silicene: A competitive 2D material

During the past decade, two-dimensional materials have attracted incredible interest from the electronic device community The first two-dimensional material studied in detail was graphene and, since 2007, it has intensively been explored as a material for electronic devices, in particular, transistors While graphene transistors are still on the agenda, researchers have extended their work to two-dimensional materials beyond graphene and the number of two-dimensional materials under examination has literally exploded recently Meanwhile several hundreds of different two-dimensional materials are known, a substantial part of them is considered useful for transistors, and experimental transistors with channels of different two-dimensional materials have been demonstrated In spite of the rapid progress in the field, the prospects of two-dimensional transistors still remain vague and optimistic opinions face rather reserved assessments The intention of the present paper is to shed more light on the merits and drawbacks of two-dimensional materials for transistor electronics and to add a few more facets to the ongoing discussion on the prospects of two-dimensional transistors To this end, we compose a wish list of properties for a good transistor channel material and examine to what extent the two-dimensional materials fulfill the criteria of the list The state-of-the-art two-dimensional transistors are reviewed and a balanced view of both the pros and cons of these devices is provided

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Two-dimensional materials and their prospects in transistor electronics

Conduction mechanisms in junctionless nanowire transistors (gated resistors) are compared to inversion-mode and accumulation-mode MOS devices. The junctionless device uses bulk conduction instead of surface channel. The current drive is controlled by doping concentration and not by gate capacitance. The variation of threshold voltage with physical parameters and intrinsic device performance is analyzed. A scheme is proposed for the fabrication of the devices on bulk silicon.

Junctionless nanowire transistor (JNT): Properties and design guidelines

All existing transistors are based on the use of semiconductor junctions formed by introducing dopant atoms into the semiconductor material. As the distance between junctions in modern devices drops below 10 nm, extraordinarily high doping concentration gradients become necessary. Because of the laws of diffusion and the statistical nature of the distribution of the doping atoms, such junctions represent an increasingly difficult challenge for the semiconductor industry. Here, we propose and demonstrate a new type of transistor in which there are no junctions and no doping concentration gradients. These devices have full CMOS functionality and are made using silicon nanowires. They have near-ideal subthreshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

Nanowire transistors without junctions

We report the fabrication of junctionless SOI MOSFETs. Such devices greatly simplify processing thermal budget and behave as regular multigate SOI transistors.

SOI gated resistor: CMOS without junctions

Short-Channel Junctionless Nanowire Transistors

In this paper, the contact resistivity of NiGe on n-doped Ge is extracted. Although phosphorus is the slowest n-type dopant in terms of diffusion in Ge, the corresponding contact resistivity data for this dopant are sparse. Contact resistivity dependence on implant dose will be determined, as well as a comparison of phosphorus- and arsenic-doped Ge layers. The impact of high contact resistance is evaluated for future technology n-type metal-oxide-semiconductor germanium devices.

NiGe Contacts and Junction Architectures for P and As Doped Germanium Devices

A new concept of vertical gallium nitride (GaN) Schottky barrier diode based on nanowire (NW) structures and the principle of dielectric REduced SURface Field (RESURF) is proposed in this paper. High-threading dislocation density in GaN epitaxy grown on foreign substrates has hindered the development and commercialization of vertical GaN power devices. The proposed NW structure, previously explored for LEDs offers an opportunity to reduce defect density and fabricate low cost vertical GaN power devices on silicon (Si) substrates. In this paper, we investigate the static characteristics of high-voltage GaN NW Schottky diodes using 3-D TCAD device simulation. The NW architecture theoretically achieves blocking voltages upward of 700 V with very low specific on-resistance. Two different methods of device fabrication are discussed. Preliminary experimental results are reported on device samples fabricated using one of the proposed methods. The fabricated Schottky diodes exhibit a breakdown voltage of around 100 V and no signs of current collapse. Although more work is needed to further explore the nano-GaN concept, the preliminary results indicate that superior tradeoff between the breakdown voltage and specific on-resistance can be achieved, all on a vertical architecture and a foreign substrate. The proposed NW approach has the potential to deliver low cost reliable GaN power devices, circumventing the limitations of today’s high electron mobility transistors (HEMTs) technology and vertical GaN on GaN devices.

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Mary White

Papers

Nanowire transistors without junctions

SOI gated resistor: CMOS without junctions

Short-Channel Junctionless Nanowire Transistors

NiGe Contacts and Junction Architectures for P and As Doped Germanium Devices

GaN Nanowire Schottky Barrier Diodes