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Brian J. Greene
Researcher at IBM
Publications - 86
Citations - 1418
Brian J. Greene is an academic researcher from IBM. The author has contributed to research in topics: Field-effect transistor & Layer (electronics). The author has an hindex of 19, co-authored 86 publications receiving 1393 citations. Previous affiliations of Brian J. Greene include GlobalFoundries & Chartered Semiconductor Manufacturing.
Papers
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Proceedings ArticleDOI
Chip-level power-performance optimization through thermally-driven across-chip variation (ACV) reduction
Xiaojun Yu,Oleg Gluschenkov,Noah Zamdmer,Jie Deng,B. A. Goplen,Howard S. Landis,L. R. Logan,J. A. Culp,Yue Liang,Ming Cai,Woo-Hyeong Lee,Nivo Rovedo,Frank D. Tamweber,D. Lea,Brian J. Greene,J. Sim,Dustin K. Slisher,Anthony I. Chou,Paul Chang,H. Trombley,E. J. Nowak,Sadanand V. Deshpande,William K. Henson,Anda Mocuta,K. Rim +24 more
TL;DR: In this paper, a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance is presented, where an optimized thermal anneal process was used to suppress ACV significantly, leading to a dramatic benefit in leakage power performance tradeoff.
Patent
Channel region dopant control in fin field effect transistor
TL;DR: In this article, a dummy gate structure straddling at least one semiconductor fin is formed on a substrate, and a planarization dielectric layer is formed over the dummy gate to provide a gate cavity.
Proceedings ArticleDOI
PMOSFET layout dependency with embedded SiGe Source/Drain at POLY and STI edge in 32/28nm CMOS technology
Liyang Song,Yue Liang,H. Onoda,C. W. Lai,Thomas A. Wallner,A. Pofelski,Christian Gruensfelder,Emmanuel Josse,T. Okawa,J. Brown,R.Q. Williams,Judson R. Holt,J.W. Weijtmans,Brian J. Greene,Henry K. Utomo,Shin-Ae Lee,Deleep R. Nair,Qintao Zhang,Chendong Zhu,X. Wu,Melanie J. Sherony,Y. M. Lee,William K. Henson,R. Divakaruni,E. Kaste +24 more
TL;DR: In this article, the eSiGe layout effect induced by PC-bounded or STI-Bounded eSiG shows impact on device performance and variability increase, and performance degradation could be explained by the mobility loss due to reducing ESiGe volume and less stress strength.
Patent
Semiconductor structure and manufacturing method
TL;DR: In this article, a dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material.
Patent
Constrained epitaxial source/drain regions on semiconductor-on-insulator finfet device
TL;DR: In this article, a method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconducting substrate, and forming a gate stack on the insulating layer.