Ultralow-Power Design in Near-Threshold Region
Dejan Markovic,Cheng C. Wang,Louis P. Alarcon,Tsung-Te Liu,Jan M. Rabaey +4 more
- Vol. 98, Iss: 2, pp 237-252
TLDR
This paper explores how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point, and introduces a pass-transistor based logic family that excels in this operational region.Abstract:
Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.read more
Citations
More filters
Proceedings ArticleDOI
The EDA Challenges in the Dark Silicon Era: Temperature, Reliability, and Variability Perspectives
TL;DR: New challenges as well as opportunities are described in the context of the interaction of dark silicon with thermal, reliability and variability concerns, and preliminary experimental evidence in their support is provided.
Journal ArticleDOI
Scalable Hardware Trojan Diagnosis
Sheng Wei,Miodrag Potkonjak +1 more
TL;DR: This work has developed a scalable HT detection and diagnosis approach that uses segmentation and gate level characterization (GLC) and is capable of detecting and diagnosing HTs accurately on large circuits.
Journal ArticleDOI
A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer
TL;DR: A novel level shifter, of which the operating range is from a deep subthreshold voltage to the standard supply voltage and includes upward and downward level conversion and is designed for practical applications.
Journal ArticleDOI
A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)
TL;DR: A novel 9T bitcell is presented, implementing a Supply Feedback concept to internally weaken the pull-up current during write cycles and thus enable low-voltage write operations, achieved without the need for additional peripheral circuits and techniques.
Proceedings ArticleDOI
VARIUS-NTV: A microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages
TL;DR: The first microarchitectural model of process variations for NTC is presented, called VARIUS-NTV, which extends the existing VARIus variation model and adopts a gate-delay model and an SRAM cell type that are tailored to NTC.
References
More filters
Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Journal ArticleDOI
An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications
TL;DR: In this article, a fully analytical MOS transistor model dedicated to the design and analysis of low-voltage, low-current analog circuits is presented, which exploits the inherent symmetry of the device by referring all the voltages to the local substrate.
Book
Logical Effort: Designing Fast CMOS Circuits
TL;DR: In this article, the authors derived the method of logical effort from design examples and calculated the logical effort of gates, and then calibrated the model to achieve equal rising and falling delays.
Journal ArticleDOI
Supply and threshold voltage scaling for low power CMOS
TL;DR: In this paper, the authors investigated the effect of reducing the supply and threshold voltage on the energy efficiency of CMOS circuits and showed that when the transistors are velocity saturated and the nodes have a high activity factor, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V.
Journal ArticleDOI
Modeling and sizing for minimum energy operation in subthreshold circuits
TL;DR: It is shown that minimum sized devices are theoretically optimal for reducing energy, and existing standard cell libraries offer a good solution for minimizing energy in subthreshold circuits.