Showing papers by "Chenming Hu published in 1993"

Future CMOS scaling and reliability

Abstract: The goals and constraints of MOSFET scaling are reviewed, and the role of reliability constraints is highlighted. It is concluded that judicial shrinking of MOSFET device dimensions can sustain the historical trend of scaling through the 0.09- mu m (4-Gb SRAM) generation of technology, which may be used for IC production in the year 2010. Power supply voltage reduction plus the desire for large transistor current will create a demand for ever thinner gate oxides that can withstand ever higher electric field. Built-in reliability must replace the traditional end-of-the-line reliability testing for future complex circuits. Circuit reliability simulation may be one of the necessary tools for achieving built-in reliability. >

Berkeley reliability tools-BERT

Abstract: Berkeley reliability tools (BERT) simulates the circuit degradation (drift) due to hot-electron degradation in MOSFETs and bipolar transistors and predicts circuit failure rates due to oxide breakdown and electromigration in CMOS, bipolar, and BiCMOS circuits. With the increasing importance of reliability in today's and future technology, a reliability simulator such as this is expected to serve as the engine of design-for-reliability in a building-in-reliability paradigm. BERT works in conjunction with a circuit simulator such as SPICE in order to simulate reliability for actual circuits, and, like SPICE, acts as an interactive tool for design. BERT is introduced and the current work being done is summarized. BERT is used to study the reliability of a BiCMOS inverter chain, and performance data are presented. >

Electromigration in Al(Cu) two-level structures: Effect of Cu and kinetics of damage formation

Abstract: The electromigration characteristics and kinetics of damage formation for Al(Cu,Si) line segments on a continuous W line and Al(Cu)/W two‐level interconnect structures have been investigated. The mass transport as a function of temperature was measured using a drift‐velocity technique. The flux divergence at the line/stud contact was found to be responsible for formation of open failure in the interconnect structure, as shown by a direct correlation observed between mass depletion at the contact and resistance increase of the line/stud chain. The depletion of Al at the stud contact is preceded by an incubation period during which Cu is swept out a threshold distance from the cathode of the line. This leads to a damage formation process which is controlled by both Cu electromigration along grain boundaries and dissolution of the Al2Cu precipitates. This is distinctly different from single‐level interconnects measured using a conventional electromigration test site. Measurements of the mean failure lifetime...

Electromigration characteristics of copper interconnects

Abstract: The electromigration characteristics of electroless plated copper interconnects have been investigated under DC and time-varying current stressing. A scheme for selected electroless Cu plating by using 150-AA Co as the seeding layer is reported. The Cu DC and pulse-DC lifetimes are found to be one and two orders of magnitude longer than that of Al-4% Cu/TiW and Al-2% Si interconnects at 275 degrees C, and the extracted Cu lifetime at 75 degrees C is about three and five orders of magnitude longer than that of Al-4% Cu/TiW and Al-2% Si, respectively. As previously reported for Al metallization, the Cu bipolar lifetimes were found to be orders of magnitude longer than their DC lifetimes under the same peak stressing current density because of the partial recovery of electromigration damage during the opposing phases of bipolar stressing. >

A capacitorless DRAM cell on SOI substrate

Abstract: We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100 /spl mu/Aspl mu/m), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is that of a transistor, which makes it very attractive for high density memory applications. Since the fabrication process of CDRAM is compatible with that of the general purpose SOI CMOS and complementary BiCMOS process, CDRAM can also be used for integrated on-chip memory and is an interesting candidate as the technology driver of SOI VLSI. >

Hole injection oxide breakdown model for very low voltage lifetime extrapolation

Abstract: An anode hole injection model for silicon dioxide breakdown characterization is presented. The model is valid for a large thickness range between 2.5 nm and at least 13 nm, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. The model extrapolation predicts Q/sub BD/ and t/sub BD/ behavior including a fluence in excess of 10/sup 7/ C/cm/sup 2/ at V/sub ox/=2.4 V for a 2.5-nm oxide. Moreover, it is fully complementary with the well-known thick oxide 1/E model, while offering the ability to predict oxide reliability for low voltages. >

Silicon dioxide breakdown lifetime enhancement under bipolar bias conditions

Abstract: The authors point out that time to breakdown (t/sub BD/) of silicon dioxide has a pronounced frequency dependence when it is measured under bipolar bias conditions. At high frequencies, bipolar t/sub BD/, can be enhanced by two orders of magnitude over the t/sub BD/, obtained using DC or unipolar pulse bias of the same frequency and electric field. The lifetime improvement is attributed to detrapping of holes. At high frequencies, the improvement is maximum because the trapped holes are concentrated at the interface where they can easily be removed upon field reversal. At low frequencies, there is less improvement because the trapped hole distribution extends further into the oxide. Two different mechanisms are proposed to explain the frequency-dependent spreading of the trapped hole distribution away from the interface. >

Antifuse structure suitable for VLSI application

Abstract: The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved by using lower thermal conductivity conductors for the electrodes or by using thinner electrodes to increase thermal resistance. According to a first aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrode materials having a relatively lower thermal conductivity than prior art electrode materials. According to a second aspect of the present invention, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing relatively thin electrodes, thus increasing their thermal resistance. According to a third aspect of the present invention, a relatively thin barrier layer is placed between one or both of the low thermal conductivity electrodes and the antifuse material in order to prevent reaction between the conductive electrodes and the antifuse material or the materials used in manufacturing such as the etch gas. According to a fourth aspect of the present invention low thermal conductivity conductors are used for both electrodes in the conductor-to-conductor antifuse in order to achieve enhanced reliability and freedom from switch-off. According to a fifth aspect of the present invention switch-off is cured in conductor-to-conductor antifuses without compromising low on-state resistance of the antifuse.

Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs)

Abstract: A hybrid mode of device operation, in which both bipolar and MOSFET currents flow simultaneously, has been experimentally investigated using quarter-micrometer-channel-length MOSFET's which were fabricated on SIMOX silicon-on-insulator substrates. This mode of device operation is achieved by connecting the gate of a non-fully-depleted SOI MOSFET to the edges of its floating body. Both the maximum G/sub m/ and current drive at 1.5* higher than the MOSFET's normal mode. Bipolar-junction-transistor (BJT)-like 60-mV/decade turn-off behavior is also achieved. This mode of operation is very promising for low-voltage, low-power, very-high-speed logic as well as for on-chip analog functions. >

A high-performance lateral bipolar transistor fabricated on SIMOX

Abstract: Double-diffused, lateral n-p-n bipolar transistors were fabricated in a simple CMOS-like process using SIMOX silicon-on-insulator (SOI) substrates. Excellent device characteristics were achieved, with peak h/sub FE/=120, BV/sub CEO/=10 V, and peak f/sub t/=4.5 GHz. The f/sub t/ versus BV/sub CEO/ trade-off was studied as a function of n/sup -/ collector width. f/sub t/>25 GHz is predicted for this structure with an improved device layout and optimized basewidth. This process may be easily extended in order to fabricate complementary BJTs in a C-BiCMOS thin-film SOI technology. >

Pseudo-nonvolatile memory incorporating data refresh operation

Abstract: A pseudo nonvolatile memory cell which may be operated in a pseudo-nonvolatile mode is achieved by utilizing a thin direct tunneling dielectric adjacent to the charge retaining region in a traditional nonvolatile memory cell such as an EPROM, EEPROM, flash EPROM, or flash EEPROM cell. The use of the direct tunneling dielectric allows for greatly enhanced write/erase cycles (exceeding 100 gigacycles) and reduced data write/erase time (under 1 microsecond). The direct tunneling dielectric also results in a reduced data retention period. Consequently, refresh circuitry is provided to maintain the non-volatility of the memory cell. A back-up battery is used to power the refresh circuitry when the system power is removed. This mode of operation provides an effectively nonvolatile memory system that is suitable for replacing traditional nonvolatile memory devices.

Modeling oxide thickness dependence of charging damage by plasma processing

Abstract: Develops a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The current is deduced from capacitance-voltage (CV) curves of metal-oxide-semiconductor (MOS) capacitors after plasma etch. The model predicts the oxide thickness dependence of plasma charging successfully. It is shown that plasma acting on a very thin oxide during processing may be modeled as essentially a current source. Thus the damage will not be greatly exacerbated as oxide thickness is further reduced in the future. Gate oxide breakdown voltage distribution of MOS capacitors after plasma processing can be predicted accurately from that of a control wafer by using a defect-induced breakdown model. >

Metal electromigration damage healing under bidirectional current stress

Abstract: The AC electromigration lifetime, without DC component, has been studied in a wide frequency range (mHz to 200 MHz) and found to be linearly proportional to the repetition frequency of the AC stressing current. This behavior is observed in both of the metallization systems (Al-2% Si and Cu) investigated. This provides further confirmation that AC lifetime is orders of magnitude longer than DC lifetime and that CMOS signal lines may be called upon to carry much larger current than allowed in present practice. >

A bidirectional NMOSFET current reduction model for simulation of hot-carrier-induced circuit degradation

Abstract: An approach for modeling hot-electron induced change in drain current that significantly improves the ease of parameter extraction and provides new capabilities for modeling the effect of bidirectional stressing and the asymmetrical I-V characteristics after stressing is presented. The change in the drain current, Delta I/sub D/ is implemented as an asymmetrical voltage-controlled current source and the new Delta I/sub D/ model is independent of the MOSFET model used for circuit simulation. The physical basis of the model, the analytical model equations, the implementation scheme in BERT (BErkeley Reliability Tools) simulator and simulation results for uni- and bidirectional circuit stressing are presented. >

Electromigration reliability of tungsten and aluminum vias and improvements under AC current stress

Abstract: The reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC, and AC stressing has been studied using Kelvin test structures. The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the intermetallic contact represents an undesirable flux divergence location for electromigration. Al vias are more reliable than W-plug vias with respect to electromigration failure. The unidirectional 50% duty factor pulse-DC lifetime is found to be twice the DC lifetime in the low-frequency region ( 10 kHz). The via lifetimes under bidirectional stressing current are found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and Al vias. All the observations are in agreement with a vacancy relaxation model. >

Electromigration failure due to interfacial diffusion in fine Al alloy lines

Abstract: Damage formation at grain boundary junctions has long been recognized as the dominant electromigration failure mechanism in metal lines. We report the results of drift‐velocity experiments on fine lines with no reservoirs and find that the interfacial mass transport, along the edges of the lines, is faster than that along grain boundaries. This causes mass depletion at the cathode end of the line, leading to electromigration failure. The result demonstrates a new failure mechanism due to electromigration in submicron lines with bamboo grain structures.

Observation of velocity overshoot in silicon inversion layers

Abstract: Employing a test structure, velocity overshoot in silicon inversion layers is observed at room temperature. For channel lengths longer than 0.3 mu m, the velocity/field relation follows the well-known behavior with no channel length dependence. The first indication of velocity overshoot is seen at a channel length of 0.22 mu m, while at L=0.12 mu m, drift velocities up to 35% larger than the long-channel value are measured. >

Hot-carrier-reliability design guidelines for CMOS logic circuits

Abstract: Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to CMOS circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict CMOS circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ft/sub rise/ and 10/ft/sub fall/ respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively. >

Impact of plasma charging damage and diode protection on scaled thin oxide

Abstract: The plasma charging stress can be quantified sensitively using differential pair circuits as well as MOSFETs. We have developed a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The model predicts the oxide thickness dependence of plasma charging successfully. A quantitative model of protection diodes for wafer charging effect on future thinner oxides is also presented. >

A high-quality stacked thermal/LPCVD gate oxide technology for ULSI

Abstract: By stacking thermal and high-quality LPCVD (low-pressure chemical vapor deposition) SiO/sub 2/ films, gate oxides with very low defect densities are demonstrated. Whereas previous reports suggested that a thick layer of LPCVD oxide can improve the stacked gate oxide defect density, it is demonstrated that even 25 AA of LPCVD oxide is sufficient to dramatically reduce the defect density compared to thermal oxide films. The projected scaling limit for this technology is estimated to be as low as 70 AA for the total stack thickness. An optimized thermal/LPCVD oxide technology is very promising as the gate dielectric for sub-half-micrometer CMOS technology. >

Monitoring plasma-process induced damage in thin oxide

Abstract: Plasma etching and resist ashing processes cause current to flow through the thin oxide and the resultant plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The oxide charging current produced by plasma processing increases with the 'antenna' size of the device structure. Oxide charge measurement such as CV or threshold voltage is a more sensitive technique for characterizing plasma-processing induced damage than oxide breakdown. The oxide charging current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. Although forming gas anneal can passivate the traps generated during plasma etching, subsequent Fowler-Nordheim stressing causes more traps to be generated in these devices than in devices that have not been through plasma etching. Using the measured charging current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. Oxide shorts density of a single large test capacitor is found to be higher than that in a multiple of separated small capacitors having the same total oxide area. This would lead to overly pessimistic oxide defect data unless care is taken. >

Temperature dependence of MOSFET substrate current

Abstract: Hitherto, theoretical models for MOSFET substrate current predicted that substrate current is a strong function of temperature. However, experimental data presented in this and previous studies show that the ratio of substrate current to drain current is insensitive to temperature over the range 77 to 300 K. The authors propose a modified model for an electron mean-free path (MFP) in the substrate current based on the concept of energy relaxation. The different between the energy and momentum relaxation MFP is clarified, and it is shown that a substrate current model with modified MFP can explain the temperature dependence of the substrate current. >

Thickness and other effects on oxide and interface damage by plasma processing

Abstract: The authors point out that plasma induced oxide charging occurs mainly during the overetch time. There is no measurable additional damage during the moment of plasma turn-on and turn-off. Plasma acts more like a current source than a voltage source. This is fortunate for future thinner oxides. There is a latent interface damage remaining after the forming gas anneal. A discrepancy between the defect densities measured in test structures and in circuits is explained. >

Octagonal washer DC SQUIDs and integrated susceptometers fabricated in a planarized sub- mu m Nb-AlO/sub x/-Nb technology

Abstract: The authors have designed, fabricated, and measured a number of Nb-AlO/sub x/-Nb octagonal washer DC superconducting quantum interference devices (SQUIDs) and miniature DC SQUID susceptometers having minimum feature size down to 0.5 mu m. With SQUID inductance values on the order of 100 pH, typical noise performance is better than 1 mu Phi /sub 0// square root Hz. The small minimum feature size of input coils and pickup loop structures will facilitate tight coupling to a wide variety of systems ranging from submicron particles and structures to conventional approximately mu H input circuits. A single-washer SQUID with an 80-turn 0.5- mu m-linewidth, 630-nH input coil has user-friendly V- Phi (voltage-flux) curves and a coupled energy sensitivity of 20 h at 4.2 K. Susceptometers with pickup loops ranging from 20- mu m to 0.8- mu m across have very user-friendly V- Phi curves and a resolution of order 100 mu /sub B// square root Hz at 4.2 K for devices with the smallest loops. >

Projecting CMOS circuit hot-carrier reliability from DC device lifetime

Abstract: We present generalized hot-carrier-reliability technology qualification and circuit design rules The inverse duty factors, ie DC to AC time conversion factors for N- and P-MOSFETS are found to be 4/ft/sub rise/, and 10/ft/sub fall/ or 120 and 300 respectively Typically, /spl Deltaspl tau/spl tau/ of an inverter is 1/4 /spl Delta/I/sub dI/sub d/ of NMOSFET minus 1/2 /spl Delta/I/sub dI/sub d/ of PMOSFET The proposed design rules are valid for both 5 V and 33 V technologies and can be easily incorporated into existing DC lifetime prediction routines >

A robust physical and predictive model for deep-submicrometer MOS circuit simulation

Abstract: An efficient physical and predictive model (the Berkeley short-channel insulated-gate FET model, or BSIM3) for deep-submicrometer MOSFETs is presented with emphasis on both digital and analog applications. BSIM3 has extensive built-in dependences of important dimensional and processing parameters such as channel length, width, gate oxide thickness, junction depth, substrate doping concentration, and LDD (lightly doped drain) structures. The model is compact, and time-consuming functions are excluded. The ease of parameter extraction was a major consideration. The number of parameters is small (/spl sim/25), and every parameter has a physical meaning; the effects of parameters on output characteristics are very predictive. This feature of BSIM3 makes statistical study of the device fabrication process possible. BSIM3 has been implemented in SPICE3 and the divergence problem is also greatly improved.

Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs

Abstract: A new Recess-Channel technology has been developed which significantly reduces the source/drain series resistance. This technology is potentially very useful for ultra-thin-film fully depleted SOI MOSFET fabrication with arbitrary silicon film thickness. Silicide technology may also be used in conjunction with the Recess-Channel technique to further reduce the source/drain series resistance and increase the current drive. >